8752CY www.icst.com/products/hiperclocks.html REV. B OCTOBER 19, 2005
1
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM PIN ASSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
QB0
VDDO
VDDO
QA3
QA2
GND
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
GND
FB_IN
VDDO
QA1
QA0
GND
CLK1
VDD
VDDA
CLK_SEL
VDDO
QB2
QB3
GND
GND
nc
PLL_SEL
VDD
ICS8752
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
÷2
÷4
÷6
÷8
÷12
PLL
PHASE
DETECTOR
PLL_SEL
FB_IN
CLK0
CLK1
CLK_SEL
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
MR/nOE
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
0
1
1
0
00
01
10
11
00
01
10
11
VCO
GENERAL DESCRIPTION
The ICS8752 is a low voltage, low skew
LVCMOS clock generator and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. With output fre-
quencies up to 240MHz, the ICS8752 is tar-
geted for high performance clock applications. Along
with a fully integrated PLL, the ICS8752 contains fre-
quency configurable outputs and an external feedback
input for regenerating clocks with “zero delay”.
Dual clock inputs, CLK0 and CLK1, support redundant
clock applications. The CLK_SEL input determines
which reference clock is used. The output divider val-
ues of Bank A and B are controlled by the DIV_SELA0:1,
and DIV_SELB0:1, respectively.
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
FEATURES
•Fully integrated PLL
•Eight LVCMOS outputs, 7Ω typical output impedance
•Selectable LVCMOS CLK0 or CLK1 inputs for
redundant clock applications
•Input/Output frequency range: 18.33MHz to 240MHz
at VCC = 3.3V ± 5%
•VCO range: 220MHz to 480MHz
•External feedback for “zero delay” clock regeneration
•Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
•Output skew: 100ps (maximum)
•Bank skew: 55ps (maximum)
•Full 3.3V or 2.5V supply voltage
•0°C to 70°C ambient operating temperature
•Available in both standard and lead-free RoHS-compliant
packages
HiPerClockS™
ICS