DS1339U-33+T&R - Maxim - Datasheet.Live

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GENERAL DESCRIPTION

The DS1339 serial real-time clock (RTC) is a low-

power cl ock/date devi ce wit h two programm able time-

of-day alarms and a programmable square-wave

output. Address and data are transferred serially

through an I2C bus. The clock/date provides seconds,

minutes, hours, day, date, month, and year

information. The date at the end of the month is

automatically adjusted for months with fewer than 31

days, including corrections for leap year. The clock

operates in either the 24-hour or 12-hour format with

AM/PM indicator. The DS1339 has a built-in power-

sense circuit that detects power failures and

automatically switches to the backup supply,

m aintaining time, dat e, and alarm oper ation.

APPLICATIONS

Handhelds (G P S , POS Termi nals)

Consumer E lectr onics (Set-Top Box, Digital

Recording, Network Appli anc e)

Offic e Equi pm ent (Fax/Printers, Copier )

Medi c al (G lucom eter, Medicine Dispenser)

Telecommunicati ons (Rout er s, S witches, S ervers)

Ot her ( Utility Meter, Vending Mac hine, Thermostat,

Modem)

FEATURES

 Real-Time Clock (RT C) Counts Seconds, M inutes,

Hours, Day, Date, Month, and Year wit h Leap-

Year Compensation Valid Up to 2100

 Availabl e in a Surf ac e-M ount Pac k age with an

Int egr ated Cry stal ( DS 1339C)

 I2C Seri al Interfac e

 Two Time-of-Day Al arms

 Program mable S quar e-Wave Output

 Osci llat or St op Flag

 Autom atic Power-Fail Detect and Swit c h Cir c uitry

 Trickle-Charge Capabilit y

 Under wri ters Laborator ies (UL) Recogniz ed

Pin Con fig urati ons appe ar at end of data sheet.

ORDERING INFORMATION

PART

TEMP RANGE

VOLTAGE (V)

PIN-PACKAGE

TOP MARK†

DS1339C-2# -40°C to +85°C 2.0 16 SO (300 mils) DS1339C-2

DS1339C-3#

-40°C to +85°C

3.0

16 SO (300 mils)

DS1339C-3

DS1339C-33#

-40°C to +85°C

3.3

16 SO (300 mils)

DS1339C-33

DS1339U-2+ -40°C to +85°C 2.0 8 µSOP 1339 rr-2

DS1339U-3+ -40°C to +85°C 3.0

SOP

1339 rr-3

DS1339U-33+ -40°C to +85°C 3.3 8 µSOP 1339 rr-33

+Denotes a lead(Pb)-free/RoHS-compliant package.

#Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements . The lead finish is JESD97 c ate gory

e3, and is compatible with both lead-bas e d an d lea d-free soldering processes.

†A “+” anywhere on the top mark indicates a lead(Pb)-free devi ce. A “#” denotes a RoHS-complian t device. rr = second line, revision code

DS1339

C Serial Real-Time Clock

19-5770; Rev 4/11

DS1339 I2C S er ial Real-Time Clock

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ABSOLUTE MAXIMUM RATINGS

Vol tage Range on Any Pin Relativ e to Ground…… …………………………………………………………-0.3V to +6.0V

Operating Temper ature Range (Nonc ondensi ng) … … ………… ………………………………………….-40°C to +85°C

Storage Temperature Range………………………………………………………………………………..-55°C to +125°C

Lead Temper ature (soldering, 10s)...…………………………………………………………………………………+260°C

Soldering Temperature (reflow).……………………………………………………………………………………….+260°C

Stres ses bey ond th ose list ed un der “A bso lute M ax imum Rat ings ” m ay c ause per mane nt dam age t o the d ev ice. Th ese are s tres s r ating s only,

and f unc t io nal operation of t h e devic e at thes e or a ny oth er c on d it io n s bey ond those ind ica te d in th e o per ationa l sec tions of the s pecif ic ations is

not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

µSOP

Junction-to-Ambient Therm al Resistance (θJA).…………………...……………………………………….206.3°C/W

Junction-to-Case Thermal Resistance ( θJC)……………………………………………………………………42°C/W

Junction-to-Ambient Therm al Resistance (θJA).……………………………………………………………….73°C/W

Junction-to-Case Thermal Resistance ( θJC)……………………………………………………………………23°C/W

Not e 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

RECOMMENDED DC OPERATING CONDITIONS

(TA = -40°C to +85°C) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Suppl y V oltage VCC

DS1339-2 1.8 2.0 5.5

DS1339-3 2.7 3.0 5.5

DS1339-33 2.97 3.3 5.5

Backup S upply Volt age VBACKUP 1.3 3.0 3.7 V

Logic 1 VIH 0.7 x

VCC VCC +

0.3 V

Logic 0 VIL -0.3 +0.3 x

VCC V

Power-Fail Voltage VPF

DS1339-2 1.58 1.70 1.80

V DS1339-3 2.45 2.59 2.70

DS1339-33 2.70 2.85 2.97

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DC ELECTRICAL CHARACTERISTICS

(VCC = MIN to MAX, TA = -40°C t o +85° C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leak age ILI (Note 3) 1 µA

I/ O Leakage ILO (Note 4) 1 µA

Logic 0 Out

VOL = 0.4V; VCC > VCC MIN ( -3, -33);

VCC ≥ 2.0V (-2) IOL (Note 4) 3 mA

Logic 0 Out

VOL = 0.2 (VCC);

1.8V < V CC < 2.0V (DS 1339-2) IOL (Note 4) 3 mA

Logic 0 Out

VOL = 0.2 (VCC);

1.3V < V CC < 1.8V (DS 1339-2) IOL (Note 4) 250 µA

VCC Active Current ICCA (Note 5) 450 µA

VCC Standby Current (Note 6) ICCS

-2: VCC = 2.2V 60 100

µA

-3: VCC = 3.3V 80 150

-33: VCC = 5.5V 200

Trickle-Charger Resistor Register

10h = A 5h, VCC = Typ, VBACKUP = 0V R1 (Note 7) 250 Ω

Trickle-Charger Resistor Register

10h = A 6h, VCC = Typ, VBACKUP = 0V R2 2000 Ω

Trickle-Charger Resistor Register

10h = A 7h, VCC = Typ, VBACKUP = 0V R3 4000 Ω

VBACKUP Leakage Current IBKLKG 25 100 nA

DC ELECTRICAL CHARACTERISTICS

(VCC = 0V, TA = -40°C to +85°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VBACKUP Current EOSC = 0, SQW Off IBKOSC (Note 8) 400 700 nA

VBACKUP Current EOSC = 0, SQW O n IBKSQW (Note 8) 600 1000 nA

VBACKUP Current EOSC = 1 IBKDR 10 100 nA

DS1339 I2C S er ial Real-Time Clock

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AC ELECTRICAL CHARACTERISTICS

(VCC = MIN to MAX, TA = -40°C t o +85° C.) (Note 9)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

SCL Cl oc k Fr equenc y fSCL Fast mode 100 400 kHz

Standard mode 100

Bus Free Time Between a STO P

and STA RT Conditi on tBUF Fast mode 1.3 µs

Standard mode 4.7

Hold Time (Repeated) S TART

Condition (Note 10) tHD:STA Fast mode 0.6 µs

Standard mode 4.0

LOW Period of S CL Cloc k tLOW Fast mode 1.3 µs

Standard mode 4.7

HIG H P eri od of SCL Cloc k tHIGH Fast mode 0.6 µs

Standard mode 4.0

Setup Time for a Repeated

STA RT Conditi on tSU:STA Fast mode 0.6 µs

Standard mode 4.7

Data Hold Time (Notes 11, 12) tHD:DAT Fast mode 0 0.9 µs

Standard mode 0

Data Setup Time (Note 13) tSU:DAT Fast mode 100 ns

Standard mode 250

Rise Tim e of Both SDA and SCL

Si gnals (Not e 14) tR Fast mode 20 + 0. 1CB 300 ns

Standard mode 20 + 0.1CB 1000

Fall Time of Both SDA and SCL

Si gnals (Not e 14) tF Fast mode 20 + 0.1CB 300 ns

Standard mode 20 + 0.1CB 300

Setup Time for STOP Condition tSU:STO Fast mode 0.6 µs

Standard mode 4.0

Capacitive Load for Each Bus

Line ( Note 14) CB 400 pF

I/ O Capacitance ( S DA, S CL) CI/O (Note 9) 10 pF

Osci llator Stop Flag (OSF) Delay tOSF (Note 15) 100 ms

DS1339 I2C S er ial Real-Time Clock

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POWER-UP/DOWN CHARAC TERISTICS

(TA = -40°C to +85°C) (Note 2, Figure 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Recovery at Power-Up tREC (Note 16) 2 ms

VCC Fall Time; VPF(MAX) to V PF(MIN) tVCCF 300 µs

VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0 µs

WARNING: Und er no circumstances are negative undershoo t s, of any ampli tude, allowed when device is in

battery-backup mode.

Note 2: Li mits at -40°C are guaranteed by design and are not production tested.

Note 3: SCL onl y.

Note 4: SDA and SQW/INT.

Note 5: ICCA—S CL at fSC max, VIL = 0.0V , VIH = VCC, trickle charger disabled .

Note 6: S p ecif ied w it h the I2C bus inactive, V IL = 0.0V, VIH = VCC, trickle charger disabled.

Note 7: VCC must be less than 3.63V if the 250Ω resistor is selected.

Note 8: U s ing rec om m ended crystal on X1 and X2.

Note 9: Guaranteed by design; not production tested.

Note 10:

After this period, the first clock pulse is generated.

Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge

the undefined region of the falli ng edge of SCL.

No t e 12: The maximum tHD:DAT need onl y b e met if th e de vice d oes n ot stretch the LOW period (tLOW) of the SC L s ignal.

No t e 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250 ns before th e SC L line

is released.

No t e 14: CB—total capacitance of one bus line in pF.

No t e 15: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤

VCC ≤ VCCMAX and 1.3V ≤ VBACKUP ≤ 3.7V.

No t e 16:

This delay applies only if the o scillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.

Figure 1. Power-Up/Down Timin g

OUTPUTS

PF(MAX)

PF(MIN)

INPUTS

HIGH-Z

DON'T CARE

VALID

RECOGNIZED

VALID

VCCF

VCCR

REC

DS1339 I2C S er ial Real-Time Clock

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Figure 2. Timing Diagram

Figure 3. Block Diagram

ALARM,

TRICKLE

CHARGE, AND

CONTROL

REGISTERS

SERIAL BUS

INTERFACE AND

ADDRESS

CONTROL

LOGIC

1Hz

1Hz/4.096kHz/8.192kHz/32.768kHz MUX/

BUFFER

USER BU FFER

(7 BYTES)

CLOCK AND

CALENDAR

REGISTERS

Power Control

DS1339

SQW/INT

VCC

VBACKUP

SCL

SDA

GND

Oscillator

and

divider

"C" version only

DS1339 I2C S er ial Real-Time Clock

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TYPICAL OPERATING CHARACTERISTICS

(VCC = 3.3v, TA = + 25° C, unless other wise noted.)

BACKUP

vs. V

BACKUP

300

350

400

450

500

550

600

650

700

750

800

850

900

1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

BACKUP

(V)

SUPPLY CURRENT (nA

VCC=0V

RS1=RS0=1

IBATOSC2

(SQWE = 1)

IBATOSC1

(SQWE = 0)

BACKUP

vs. Temper at ur e

BACKUP

= 3.0V

300

350

400

450

500

550

600

650

-40 -20 020 40 60 80

TEMPERATURE (°C)

SUPPLY CURRENT (nA

VCC=0V

INTCN = 0

RS2 = RS1 = 1

INTCN = 0

vs. V

100

150

200

250

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

(V)

SUPPLY CURRENT (uA

SCL=400kHz

ICCA

SCL=SDA=0Hz

ICCS

Oscil lator Fr equency vs. Supply Vol t age

32768.0

32768.1

32768.2

32768.3

32768.4

32768.5

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Oscillator Supply Voltage (V)

FREQUENCY (Hz)

DS1339 I2C S er ial Real-Time Clock

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PIN DESCRIPTION

NAME FUNCTION

µSOP

1 — X1

Connections for Standar d 32.768kHz Quartz Crystal. The int er nal oscillator

ci r c uitry is designed for oper ation wit h a crystal hav ing a specif ied load

capacit anc e ( CL) of 6pF. An ext er nal 32.768kHz oscillator can also drive the

DS1339. In t his confi gur ati on, t he X1 pi n is connected to the ext er nal oscill ator

signal and the X2 pin is l eft unc onnec ted.

For m or e information about cry stal sel ec tion and cr y stal lay out consi der ati ons,

refer to Appli c ation Note 58: Cry stal Cons ider ations with Dallas Real-Time

Clocks.

2 — X2

3 14 VBACKUP

Secondary P ower Supply. Supply v oltage must be held between 1.3V and 3.7V

for proper operati on. T his pi n can be connected t o a primary cell, such as a

lithium button cell. A dditionally, this pi n c an be connected to a r ec har geable c ell

or a super cap when used in conjunc tion with the trickl e-charge feature. Diodes

should not be plac ed in series between the backup sour c e and the VBACKUP input,

or improper oper ation will result. If a back up suppl y is not r equired, VBACKUP must

be grounded. UL r ec ogniz ed to ensure against r everse charging cur r ent when

used with a lithium cell. For more in formation, visit www.maxim-ic.com/qa/info/ul.

4 15 GND Gr ound. DC power is provided t o the devic e on these pins.

5 16 SDA

Serial Dat a Input /O utput. SDA i s the input/ output pin for the I2C serial interfac e.

The SDA pin is an open-drain out put and requires an ext er nal pullup r esi stor .

The pull up voltage may be up t o 5.5V regardless of the voltage on VCC.

6 1 SCL

Serial Clock Input . SCL is used to synchroni z e data mov em ent on t he I2C serial

interface. The pull up voltage may be up to 5. 5V regardless of the v oltage on

VCC.

7 2 SQW/INT

Square-Wave/Interrupt Output. Progr ammable square-wave or interrupt output

signal. The SQW/INT pin is an open-drain out put and requires an ext er nal pullup

resistor. T he pull up volt age m ay be up to 5. 5V regardles s of the volt age on VCC.

If not used, t his pi n may be left unconnected.

8 3 VCC

Primary Power Supply. When voltage is appli ed within normal limit s, the devi c e

is fully accessible and data c an be wri tt en and r ead. When a back up suppl y is

connect ed and V CC is bel ow VPF, r eads and writ es are inhibited. T he timek eeping

and alarm f unctions operat e when the device is powered by V

or V

BACKUP

— 4–13 N.C. No Connection. These pins are unused and must be c onnected to ground.

TYPICAL OPERATING CIRCUIT

DS1339

CPU

VCC

1 2

SDA

SCL

GND

X2X1

VCC

RPU RPU CRYSTAL

SQW/INT

VBACKUP 3

DS1339 I2C S er ial Real-Time Clock

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DETAILED DESCRIPTION

The DS1339 serial real-time clock (RTC) is a low-power clock/date device with two programmable time-of-day

alarms and a programmable square-wave output. Address and data are transferred serially through an I2C bus.

The cl ock/dat e prov ides second s, m inut es, hours, day, dat e, mont h, and year i nform ation. The date at the end of

the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The

clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1339 has a built-in power-

sense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date,

and alarm operation.

OPERATION

The DS1339 oper ates as a slave dev ic e on the serial bus. Ac c es s is obtained by implementing a ST A RT conditi on

and providing a device identification code followed by data. Subsequent registers can be accessed sequentially

until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is

greater than VPF. Howev er, when VCC falls below VPF, the internal clock registers are blocked from any access. If

VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is

greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The

registers are maintained from the VBACKUP source until VCC is returned to nominal levels. The block diagram in

Figure 3 shows t he main elements of the serial r eal-time c lock.

POWER CONTROL

The power-control function is provided by a precise, temperature-compensated voltage reference and a

comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read

when VCC i s great er than VPF. However, when VCC falls below VPF, the internal cloc k r egister s are blocked from any

access. If VPF is less than VBACKUP, the devi ce power i s swit ched fr om VCC to VBACKUP when VCC dr ops belo w V PF. If

VPF i s greater t han V BACKUP, the dev i ce power i s swit ched f rom VCC to VBACKUP when VCC drops b elow VBACKUP. The

regi ster s are maint ained from the VBACKUP s ource until VCC i s ret ur ned to nominal l ev els (Table 1). After VCC returns

abov e V PF, read and write acces s is al lowed after tREC (Figure 1). On the first application of power to the device the

time and date register s are reset to 01/01/00 01 00: 00:00 (M M /DD/YY DOW HH:MM: SS).

Table 1. Power Control

SUPPLY CONDITIO N READ/WRITE

ACCESS POWERED

VCC < VPF, VCC < VBACKUP No VBACKUP

< V

, V

> V

BACKUP

No V

> V

, V

< V

BACKUP

Yes V

VCC > VPF, VCC > VBACKUP Yes VCC

OSCILLATOR CIRCUIT

The DS1339 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or

capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a

functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal

with t he specif ied c har ac teristics.

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Table 2. Crystal Specifications*

PARAMETER SYMBOL MIN TYP MAX UNITS

Nomi nal Frequenc y fO 32.768 kHz

Series Resistance ESR 50 kΩ

Load Capaci tance CL 6 pF

*The cryst al, traces, and crystal inp ut pi ns should be isolated from RF ge nerating si gnals . Refer to

Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.

CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between

the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional

error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the

oscillator circuit may result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the

crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time

Clocks for detailed i nform ation

DS1339C ONLY

The DS1339C i nt egrates a standard 3 2,768Hz crystal in t he package. T ypical acc uracy at nominal VCC and +25°C

is approxim ately 10ppm . Ref er to Applic ation Note 58 for inform ation about c r y stal ac c ur ac y vs. temperature.

Figure 4. Typical PC Board Layout for Crystal

LOCAL GROUND PLANE (LAYER 2)

CRYSTAL

GND

NOTE: AVOID ROUTING SIGNALS IN

THE CROSSHATCHED AREA (UPPER

LEFT-

HAND QUADRANT) OF THE

PACKAGE UNLESS THERE IS A

GROUND PLANE BETWEEN THE

SIGNAL LI N E AN D TH E PAC KAGE.

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ADDRESS MAP

Table 3 shows the address map for the DS1339 registers. During a multibyte access, when the address pointer

reaches the end of t he register space (10h) , it wraps ar ound to l ocati on 00h. On an I2C START, STOP, or address

pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time

inf orm ati on is read f rom these secondary regi sters, whi le the clock may continue to run. This elim inates the need

to re-r ead the register s i n c ase of an update of the main regi ster s during a read.

Table 3. Timekeeper Registers

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE

00h 0 10 Seconds Seconds Seconds 00–59

01h 0 10 Minutes Minutes Minutes 00–59

02h 0 12/24 AM/PM 10 Hour Hour Hours

1–12

+AM/PM

00–23

20 Hour

03h

Day

1–7

04h

10 Date

Date

01–31

05h Century 0 0

Month

Month/

Century

01–12 +

Century

06h 10 Year Year Year 00–99

07h A1M1 10 Seconds Seconds

Alarm 1

Seconds

00–59

08h A1M2 10 Minutes Minutes

Alarm 1

Minutes

00–59

09h A1M3 12/24 AM/PM 10 Hour Hour Alarm 1

Hours

1–12 +

AM/PM

00–23

20 Hour

0Ah A1M4 DY/DT 10 Date Day, Date

Alarm 1

Day,

Alarm 1

Date

1-7, 1-31

0Bh A2M2 10 Minutes Minutes

Alarm 2

Minutes

00–59

0Ch A2M3 12/24 AM/PM 10 Hour Hour Alarm 2

Hours

1–12 +

AM/PM

00–23

20 Hour

0Dh A2M4 DY/DT 10 Date Day, Date

Alarm 2

Day,

Alarm 2

Date

1–7, 1–31

0Eh EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE Control —

0Fh OSF 0 0 0 0 0 A2F A1F Status —

10h TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0

Trickle

Charger

—

Note: Unless otherwi se specified, the state of the registers are not defined when power is first applied or when VCC and V BACKUP falls below the

VBACKUP(MIN).

DS1339 I2C S er ial Real-Time Clock

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TIME AND DATE OPERATION

The time and date information is obtained by reading the appropriate register bytes. Table 3 shows the RTC

regi sters. The tim e and date are set or initi alized by writi ng the appropri ate regi ster bytes. The c ontent s of the tim e

and date regi sters are in t he BCD f orm at. The DS1339 can be run i n either 12-hour or 24-hour m ode. Bit 6 of the

hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour m ode is selected. In the

12-hour m ode, bi t 5 is the AM/PM bit with logi c high bei ng PM . I n the 24-hour m ode, bit 5 i s the 20-hour bit (20 t o

23 hours). All hours values, including the alarms, must be re-entered whenever the 12/24-hour mode bit is

changed. The centur y bit (bit 7 of the m onth regi ster) is toggled when the year s regi ster ov erflows fr om 99 to 00.

The day-of-week r egister inc rem ents at m idni ght. V alues that cor respo nd to t he day of week are u ser-defi ned, but

m ust be sequential (i.e., if 1 equals Sunday, then 2 equals Monday and so on). I llogical time and dat e entries result

in undefined operati on.

W hen readi ng or writi ng the tim e and dat e regi sters, secondar y (user ) buffers are used to prev ent error s when the

internal registers update. When reading the time and date registers, the user buffers are synchronized to the

int ernal registers on any START or STOP, and when the addre ss poi nter roll s ov er to zero. The countdown chai n

is reset whenever the seconds register is written. Write transfers occurs on the acknowledge pulse from the

devi c e. T o av oid rollover issues, once t he c ountdown chain i s reset, the remaining time and dat e r egisters must be

written within one second. If enabled, the 1Hz square-wav e output transitions high 500ms after the seconds data

transfer , prov ided the oscillator i s al r eady r unning.

ALARMS

The DS1339 contai ns two time of day/ date al arm s. Alarm 1 can be set by writing t o registers 07h to 0Ah. Alarm 2

can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the Alarm Enable and INTCN

bit s of t he Control Register) to activ ate t he SQW/INT output on an al arm m atch c ondition. Bit 7 of each of the t im e

of day/date alarm registers are mask bits (Table 4). W hen all the mask bits for each alarm are logic 0, an alarm

only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time of

day/dat e al arm register s. The al arms can al so be progr amm ed to repeat ev ery second, mi nut e, hour, day, or date.

Table 4 shows the possible settings. Confi gur ations not listed i n the tabl e r esul t in illogical oper ati on.

The DY/ DT bits (bi t 6 of t he alarm day/dat e registers) control whether the alarm v alue stored in bit s 0 to 5 of that

regi ster r eflect s the day of the week or the date of the month. If DY/DT is writ ten to a logic 0, t he alarm is the r esul t

of a match wit h date of the month. If DY /DT is wri tten to a logic 1, the al arm is the result of a match wit h day of t he

week.

The device checks for an alarm match once per second. When the RTC register values match alarm register

settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is set to logic 1. If the corresponding Alarm Interrupt

Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the

SQW/INT) signal . If the BBSQI bit is set to 1, the INT out put activates while the part is being powered by VBACKUP.

The alarm output remains active until the alarm fl ag is cleared by the user.

DS1339 I2C S er ial Real-Time Clock

13 of 20

Table 4. Alarm Mask Bits

DY/

ALARM 1 REGISTER MASK BITS

(Bit 7)

ALAR M RATE

A1M4

A1M3

A1M2

A1M1

Al arm once per second

Al arm when second s mat c h

Al arm when minutes and seconds m atch

Al arm when hours, m inutes, and seconds mat c h

0 0 0 0 0

Al arm when date, hour s, m inutes, and seconds

match

1 0 0 0 0 Al arm when day, hours, m inutes, and seconds mat c h

DY/

ALARM 2 REGISTER MASK BITS

(Bit 7)

ALAR M RATE

A2M4

A2M3

A2M2

Al arm once per mi nute (00 sec. of every min.)

Al arm when minutes m atch

Al arm when hours and minut es match

Al arm when date, hour s, and m inutes mat c h

Al arm when day, hours, and m inutes mat c h

SPECIAL-PURPOSE REGISTERS

The DS1339 has two additional registers (control and status) that control the RTC, alarms, and square-wave

output.

CONTROL REGISTER (0Eh)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE

Bit 7: Enable Oscillator (EOSC). T hi s bit when set t o logi c 0 start s the o scill ator . W hen t his bi t i s set t o a l ogi c 1,

the osci llator is stopped. T his bi t is enabled (l ogic 0) when power i s fir st applied.

Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to a logic 1 enables the

square wave or interrupt output when VCC is absent and the DS1339 is being powered by the VBACKUP pin. W hen

BBSQI is a l ogic 0, the SQW/INT pin goes high impedance when VCC falls bel ow the po wer-fail trip poi nt. This bit is

disabl ed ( logic 0) when power is first applied.

Bits 4 an d 3: Rate Sel ect (RS2 and RS1). T hese bit s control the frequency of the square-wav e output when t he

square wave has been enabl ed. Table 5 shows the squar e-wave frequenc ies that can be select ed with t he RS bits.

These bits are both set to logic 1 (32k Hz ) when power is first applied.

Table 5. SQW/INT Output

INTCN RS2 RS1

SQW/INT

OUTPUT

A2IE A1IE

1Hz

4.096kHz

8.192kHz

32.768kHz

A1F

A2F

A1F

DS1339 I2C S er ial Real-Time Clock

14 of 20

Bit 2: Interrupt Control (INTCN). This bit cont r ols the rel ationship bet ween the t wo alar ms and the interrupt output

pins. When the I NTCN bi t i s set to l ogi c 1, a m at ch between t he ti m ekeepi ng regi sters and the al arm 1 or al arm 2

registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a

square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied.

Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the

status re gister to a s sert S QW/INT (when INTCN = 1). When the A2IE bit is set to logi c 0 or INT CN is set to lo gic 0,

the A2F bit does not initiate an interr upt signal. The A2IE bit is disabled (l ogic 0) when power is first applied.

Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the

status re gister to a s sert S QW/INT (when INTCN = 1). When the A1IE bit is set to logi c 0 or INT CN is set to lo gic 0,

the A1F bit does not initiate an interr upt signal. The A1IE bit is di sabl ed (l ogic 0) when power is first applied.

STATUS REGISTER (0Fh)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OSF 0 0 0 0 0 A2F A1F

Bit 7: Oscillator Stop Flag (OSF). A logic 1 in t his bi t indicates that the oscillator eit her is stopped or was stopped

f or som e period of time and may be used to judge t he vali dity of the clock and date data. Thi s bit is edge tri ggered

and is set to logi c 1 when the o scil lator stops. The followi ng ar e examples of conditions that c an c ause the O S F bit

to be set:

1) The first time power is applied.

2) The v oltage on bot h VCC and VBACKUP are insuffici ent t o support oscill ation.

3) The EOSC bit is tur ned off .

4) External infl uenc es on the c r y stal ( e.g., noise, leak age, etc.) .

This bit rem ains at logic 1 until writt en to logic 0. T his bit c an only be wri tt en to a logic 0.

Bit 1: Alarm 2 F lag ( A2F). A logic 1 in t he Al arm 2 Fl ag bit indi c ates that the t im e m atched t he alarm 2 registers. If

the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared

when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value

unchanged.

Bit 0: Alarm 1 F lag ( A1F). A logic 1 in t he Al arm 1 Fl ag bit indi c ates that the t im e m atched t he alarm 1 registers. If

the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared

when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value

unchanged.

DS1339 I2C S er ial Real-Time Clock

15 of 20

TRICKLE CHARGER REGISTER (10h)

The sim plified schemati c in Figure 5 sho ws the ba sic com ponents of the trickle charger. The trickl e-charge sel ect

(TCS ) bits (bi ts 4 to 7) c ontrol t he sel ec ti on of the trickle charger . To pr event accidental enabling, onl y a patt ern on

1010 enables the t r ickl e c har ger . All ot her patt er ns di s able t he trickl e c har ger . The tric k le charger is di sabl ed when

power i s first applied. The diode-select (DS) bits (bits 2 and 3) selec t whet her or not a diode is c onnec ted b etween

VCC and VBACKUP. T he ROUT bits (bits 0 and 1) selec t the value of the resi stor c onnec ted between VCC and VBACKUP.

Table 6 shows the bit values.

Table 6. Trickle Charger Register (10h)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FUNCTION

TCS3

TCS2

TCS1

TCS0

DS1

DS0

ROUT1

ROUT0

Disabled

No diode, 250

Ω

resistor

One diode, 250

Ω

resistor

No diode, 2k

Ω

resistor

One diode, 2k

Ω

resistor

No diode, 4k

Ω

resistor

One diode, 4k

Ω

resistor

Initi al power-up va lues

Warning: The ROUT value of 250Ω must not be selected whenever VCC is greater than 3.63V.

The user determines diode and resistor selection according to the maximum current desired for battery or super

cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume

that a 3.3V sy stem power supply i s appl i ed to VCC and a super cap i s connect ed to VBACKUP. Al so assum e that t he

trickl e charger has been enabl ed with a diode and resistor R2 between VCC and VBACKUP. The maximu m current IMAX

would therefore be calculated as follows:

IMAX = (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) / 2kΩ ≈ 1.3mA

As the super cap or battery charges, the voltage drop between VCC and VBACKUP decreases and therefore the

charge cur r ent decr eases.

DS1339 I2C S er ial Real-Time Clock

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Figure 5. Programmable Trickle Charger

I2C SERIAL DATA BUS

The DS1339 s uppor ts the I2C bus protoc ol. A dev ic e that sends data onto t he bus is d efi ned as a transm itt er and a

devi ce receiv ing dat a as a receiv er. T he dev ice t hat control s the message i s call ed a master . T he dev ices that are

contr olled by the m aster are ref erred to as sl av es. T he bus must be control led by a m aster device that generates

the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1339

operates as a slav e on the I 2C bus. Wit hin t he bus spec ifi cati ons, a standard m ode (100kHz c ycl e rat e) and a f ast

m ode ( 400k Hz cycle r ate) ar e defined. The DS 1339 works in both modes. Connec ti ons to the bus are made via the

open-drai n I/O lines SDA and S CL.

The f ollowing bus prot oc ol has been defined (Figure 6):

 Data t r ansfer may be initiat ed only when the bus is not busy.

 During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the

data line while the clock line is HIGH are inter pr eted as cont r ol si gnals.

Accor dingly , t he following bus conditions have been def ined:

Bus not busy: Both data and clock lines remain HIG H.

START dat a transf er: A change i n the state of the data l ine, f rom HIGH to LOW, whil e the cl ock is HIG H,

defines a STA RT condition.

STOP data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is

HIG H, defi nes the S TO P c ondition.

Data vali d: The stat e of the data line represents v ali d data when, after a START conditi on, the data li ne is

stable for t he dur ati on of the HIG H peri od of the clock signal . T he data on the line must be c hanged during

the LOW peri od of the clock si gnal. There is one cloc k pulse per bit of data.

1 OF 16 SELECT

NOTE: ONLY 1010 ENABLES CHARGER

1 OF 2

SELECT

1 OF 3

SELECT

TCS3

TCS2

TCS1

TCS0

DS1

DS0

ROUT1

ROUT0

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

250Ω

2kΩ

4kΩ

TRICKLE CHARGE REGISTER

TCS

0-3

= TRICKLE CHARGER SE LECT

0-1

= DIODE SELECT

ROUT

0-1

= RESISTOR SELECT

BACKUP

DS1339 I2C S er ial Real-Time Clock

17 of 20

Each dat a transf er i s initi ated wit h a START condition and t ermi nated wit h a STOP conditi on. T he num ber

of data bytes transferred between START and STOP conditions is not limited, and is determined by the

m aster dev ic e. T he inform ation is transfer r ed by te-wise and each receiver acknowledges with a ni nth bit .

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the

recept ion of each byte. The master devi ce must generate an ex tra cl ock pul se that is associated with thi s

acknowledge bit .

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of

course, setup and hol d times m ust be taken int o ac c ount. A m aster must si gnal an end of data t o the slave

by not gener ati ng an acknowledge bi t on the l ast byte that has been cl ocked out of t he slav e. In thi s case,

the slave must leave the dat a line HIG H to enable the master to generate t he STOP c ondition.

Figure 6. Data Transfer on I2C Serial Bus

Depending upon the stat e of the R/W bi t, two types of data t r ansfer are possibl e:

1) Data tran sfer from a master transmitter to a slave receiver. T he fi rst byte t ransmi tted by the m aster is

the slav e address. Nex t foll ows a num ber of data byt es. T he slav e returns an ackno wledge bit after each

received by te. Data is transfer r ed with the most signifi cant bit (MSB) first.

2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is

transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave

transm itting a number of dat a byt es. T he m aster ret urns an acknowledge bi t aft er all received bytes other

than t he last by te. A t t he end of the last received byte, a “not ac k nowledge” is ret ur ned. The master devic e

generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a

STOP condition or with a repeated START condition. Since a repeated START condition is also the

beginning of the next serial transfer, t he bus is not released. Dat a is transfer r ed with the most significant bit

(MSB) first.

The DS1339 c an oper ate in t he following two modes:

1) Sl ave Receiver Mod e ( Wri t e Mode): S eri al data and clock ar e received through S DA and S CL. Aft er eac h

byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the

beginning and end of a serial tr ansfer . Address recog nit ion is perform ed by har dware after rec eption of the

slave address and direction bit (Figure 7). The slave address byte is the first byte received after the

STA RT condition i s generated by the master . The slave address byte contai ns the 7-bit DS1339 address,

which is 110100 0, followed by t he dir ection bit (R/W), whi ch is 0 f or a write. Aft er receiv ing and decoding

the slave address byte the slave outputs an acknowledge on the SDA line. After the DS1339

acknowledges the slave address + write bit, the master transmits a register address to the DS1339. This

DS1339 I2C S er ial Real-Time Clock

18 of 20

sets the register pointer on the DS1339, with the DS1339 acknowledging the transfer. The master may

then transmit zero or more bytes of data, with the DS1339 acknowledging each byte received. The

address point er i ncrem ents af t er each data byt e is transf err ed. The master gener ates a STO P conditi on to

terminate the data writ e.

2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver

m ode. Howev er, in this mode, the direction bit i ndicates that the transfer di rection i s reversed. Seri al dat a

is tr ansmit ted on SDA by the DS 1339 whi l e the seri al cl ock is input on SCL. S TART and STO P conditi ons

are recogni zed a s the be gi nning and end of a seri al t ransf er (Figure 8). The sl ave address byte is the f i rst

byte receiv ed aft er the ST ART conditi on is generated by t he master. T he slav e address byte contai ns the

7-bit DS1339 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After

receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The

DS1339 then begi ns to t ran smit data starti ng with t he register addres s pointed t o by t he regi ster poi nter. If

the regi ster poi nt er i s not wri tt en to bef or e the i ni tiati on of a read m ode t he fi rst addres s that i s read is the

last one stored in the register pointer. The address pointer is incremented after each byte is transferred.

The DS1339 m ust r ec eive a “not acknowledge” to end a read.

Figure 7. Data Write—Slave Receiver Mode

Figure 8. Data Read (from Current Pointer Location)—Slav e Transm itter Mode

Figure 9. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit

...AXXXXXXXXAS 0 XXXXXXXX AXXXXXXXX AXXXXXXXX A P

S - Sta rt

A - Acknowledge (ACK)

P - Sto p

<R/W>

DATA TRANSFERR ED

(X+1 BYTES + ACKNOWLEDGE)

1101000

Master to slave

Slave to master

...AXXXXXXXXA

1101000S 1 XXXXXXXX AXXXXXXXX XXXXXXXX AP

<Data(n+2)> <Data(n+X)>

S - Sta rt

A - Acknowledge (ACK)

P - Sto p

A - Not Acknowledge (NACK)

<RW>

DATA TRANSFERR ED

(X+1 BYTES + ACKNOWLEDGE)

NOTE: LAST DATA BYTE I S FOLLOWED BY A NACK

Master to slave

Slave to master

...AXXXXXXXX XXXXXXXX AXXXXXXXX AXXXXXXXX AP

S - Sta rt

Sr - Repeated Start

A - Acknowledge (ACK)

P - Sto p

A - Not Acknowledge (NACK)

DATA TRANSFERR ED

(X+1 BYTES + ACKNOWLEDGE)

NOTE: LAST DATA BYTE I S FOLLOWED BY A NACK

AXXXXXXXXA1101000S0

<RW>

1101000Sr 1

<RW>

<Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>

Master to slave

Slave to master

DS1339 I2C S er ial Real-Time Clock

19 of 20

HANDLING, PCB LAYOUT, AND ASSEMBLY

The DS1339C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but

precaut ions should be taken to ensure that ex cessiv e shocks are av oided. Ultrasonic cleaning should be avoided

to prevent dam age to the crystal .

Avoid running signal traces under the package, unless a ground plane is placed between the package and the

signal line. All N.C. (no connect) pins must be connec ted to ground.

Moisture-sensitiv e packages are shipped f rom the factory dry-packed. Handling instructions listed on the package

label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020B standard for

moisture-sensi tive devi c e (MSD) classific ations.

PIN CONFIGURATIONS

CHIP INFORMATION

PROCE S S: CMOS

PACKAGE INFORMATION

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.

Note t hat a “+”, “#”, or “ -” in the package c ode indicat es RoHS stat us only . Pack age dr awings may show a differ ent

suffix c har acter , but the drawing per tains to t he pac k age regardless of RoHS status.

PA CKA GE TYPE PACKAGE CO DE OUTLINE NO. LAND PATTERN NO.

8 µSOP U8+1 21-0036 90-0092

16 SO W16#H2 21-0042 90-0107

SOP

SQW/INT

GND

VCC

SCL

SDA

VBACKUP

DS1339

TOP VIEW

SQW/

INT

SCL

SDA

GND

BACKUP

N.C.

DS1339C

SO (300 mil s)

TOP VIEW

DS1339 I2C S er ial Real-Time Clock

20 of 20

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim

reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

REVISION HISTORY

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

100108

Rem ov ed leaded par t number s fr om the Ordering Inf or m ation table. 1

Removed the pullup resistor voltage spec from the Recommended DC

Operating Condit ions table and added it to t he pin descriptions.

2, 8

Rem ov ed Note 7 from the I

BKDR

specification in the DC Electrical Characteristics

table.

Updated t he bloc k di agr am (Fi gur e 3) to show t hat SQW/I NT is open drai n. 6

Added the UL link to the VBACKUP description in the Pin Description table. 8

Removed the duplicate O s c illator Cir c uit section. 9

Added the initial POR state for time and date register s i n the Power Cont r ol

section.

Changed the seri es resistanc e ( E S R) v alue in Tabl e 2 f rom 45kΩ to 50kΩ. 10

Added the overbar to the “A” legend f or NACK i n Figure 8. 18

4/11

Updated t he sol der ing temperature and added lead temperature inf ormation to

the A bs olute Max im um Ratings sect ion; added t he P ackage T her m al

Characteristics section and updated the µSOP θJA and θJC number s; c hanged

the VCC m ax numbers fr om 2.2V to 5.5V for DS1339-2 and 3.3V to 5.5V for

DS1339-3 i n the Recommended DC Oper ating Condit ions table.

Updated t he ICCS param eter in the DC Electrical Characteristics table. 3

Changed the 10 Hour bit to 20 Hour bit for 02h, 09h, and 0Ch in Tabl e 1 and the

Time and Date Operat ion section. 11, 12

Updated t he Handling, PCB Lay out, and Assem bly secti on; remov ed the

transi stor c ount f r om the Chip Inf or m ation section; added the land patter n

num ber s to the Package Infor m ation table. 19