Data Sheet: ACD82112 INTRODUCTORY Advanced Communication Devices Data Sheet: ACD82112 12 Ports 10/100 Fast Ethernet Switch Please check ACD's website for update information before starting a design Web site: http://www.acdcorp.com or Contact ACD at: Email: support@acdcorp.com Tel: 408-433-9898 Fax: 408-545-0930 ACD Confidential Material For ACD authorized customer use only. No reproduction or redistribution without ACD's prior permission. 1 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Rev.1.3.4.I Last Update: March 20, 1999 Subject to Chnage Data Sheet: ACD82112 Page 1 2 3 4 5 6 7 8 9 10 11 General Description Main Features System Block Diagram System Description Functional Description Interface Description Register Description Pin Description Timing Description Electrical Specifications Packaging 3 3 3 4 4 11 16 25 28 34 35 A1 Appendix Address Resolution Logic (The built-in ARL) 36 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Section INTRODUCTORY Table of Contents 2 A complete 12 port 10/100 switch can be built with the use of the ACD82112, 10/100 PHY and SRAM. The MAC addresses space can be expanded from the builtin 2K to 11K by using ACD's external ARL (Address Resolution Logic), the ACD80800. Advanced network management features can be supported with the use of ACD's MIB (Management Information Base, ACD80900) chip. * * * * * * * * * * * * * * * * * * * 12 - 10/100 Mbps, auto-sensing ports with MII interface Full / half duplex operation 2.4 Gbps aggregated throughput True non-blocking switch architecture Shared buffer with starvation control algorithm Built-in storage of 2,048 MAC addresses Automatic source address learning Optional back-pressure (half duplex) flow control 802.3x pause frame (full duplex) flow control Store-and-forward switch mode Port based VLAN support UART type CPU management interface Supports up to 11K addresses with External ARL controller, the ACD80800 RMON and SNMP support with External MIB controller, the ACD80900 Status LEDs: Link, Speed, Full/Half Duplex, Transmit, Receive, Collision and Frame Error Reversible MII option for CPU and expansion port interface, with hardware based flow control Wire speed forwarding rate 388-pin PBGA package (including 36 Thermal Ground pins at the center) 3.3V power, 3.3V I/O with 5V tolerance INTRODUCTORY The ACD82112 is a single chip implementation of a 12 port 10/100 Ethernet switch system intended for IEEE 802.3 and 802.3u compatible networks. The device includes 12 independent 10/100 MACs. Each MAC interfaces with an external PMD/PHY device through a standard MII interface. Speed can be automatically configured through the MDIO or the optional CPU UART. Each port can operate at either 10Mbps or 100Mbps, in halfduplex or full-duplex mode. The core logic of the ACD82112, implemented with patent pending BASIQ (Bandwidth Assured Switching with Intelligent Queuing) technology, can simultaneously process 12 asynchronous 10/100Mbps traffics. The Queue Manager inside the ACD82112 provides the capability of routing traffic with the same order of sequence, without any packet loss. Data Sheet: ACD82112 2. MAIN FEATURES 1. GENERAL DESCRIPTION PMD/ PHY-0 PMD/ PHY-1 FIFO Buffer MAC-0 FIFO Lookup Engine (2K MAC Addr.) Buffer FIFO BIST Handler LED Controller Buffer MAC-1 FIFO Buffer MX Queue Manager DMX PMD/ PHY-10 PMD/ PHY-11 FIFO Buffer MAC-10 FIFO Buffer FIFO Buffer ARL Interface SRAM Interface MIB Interface ARL ACD80800 (11K MAC Addr.) (optional) SRAM MIB ACD80900 (optional) MAC-11 FIFO Buffer ACD82112 3 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. 3. SYSTEM BLOCK DIAGRAM The ACD82112 Ethernet switch contains three major functional blocks: the Media Access Controller (MAC), the Queue Manager, and the Lookup Engine. There are 12 independent MACs within the ACD82112. The MAC controls the receiving, transmitting, and deferring process of each individual port, in accordance to the IEEE 802.3 and 802.3u standards. The MAC logic also provides framing, FCS checking, error handling, status indication and flow control functions. Each MAC interfaces with an external transceiver through a standard MII interface. The device utilizes ACD's proprietary BASIQ (Bandwidth Assured Switching with Intelligent Queuing) technology. It is a technology to efficiently enforce the firstin-first-out rule of Ethernet Bridge-type devices. The technology enables a true non-blocking frame switching operation at wire speeds for a high throughput and high port density Ethernet switch. The on-chip Lookup Engine implements a 2,048 entries MAC address lookup table. It maps each destination address into a corresponding port. Each MAC address is automatically learned by the LOOKUP ENGINE after an error-free frame is received. Therefore, the ACD82112 alone can be used to build a complete Fast Ethernet switch with up to 2,048 host connections. (For detailed information about the built-in ARL, please refer to the ACD80800 data sheet.) The System CPU can access various registers inside the ACD82112 through a serial CPU management interface. The CPU can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers. The CPU can also access the registers of external transceiver (PHY) devices through the CPU management interface. 5. FUNCTIONAL DESCRIPTION The MAC controller performs transmit, receive, and defer functions, in accordance to the 802.3 and 802.3u specification. The MAC logic also handles frame detection, frame generation, error detection, error handling, status indication and flow control functions. Under fullduplex mode, the flow control is implemented in compliance with IEEE 802.3x standard. Frame Format The ACD82112 assumes that the received data packet will have the following format: Preamble SFD DA SA Type/Len Data FCS For workgroup or backbone switches, the ACD82112 can support more MAC addresses per port through the use of an external ARL chip, the ACD80800. The ACD82112 has a glueless ARL interface that allows a supporting chip (ACD80800) to provide up to 11K MAC addresses per switch. System designers can also use this ARL interface to implement a vendor-specific address resolution algorithm. The ACD82112 provides management support through its MIB (Management Information Base) interface. The MIB interface can be used to monitor all traffic activities of the switch system. The supporting chip (the ACD80900) provides a full set of statistical counters to support both SNMP and RMON network management functions. System designers can also use the MIB in- Where, Preamble is a repetitive pattern of `1010....' of any length with nibble alignment. The SFD (Start Frame Delimiter) is defined as an octet pattern of 10101011. The DA (Destination Address) is a 48-bit field that specifies the MAC address of the destined DTE. If the first bit of DA is 1, the ACD82112 will treat the frame as a broadcast/multicast frame and will forward the frame to all ports within the source port's VLAN except the source port itself or BPDU address. 4 Data Sheet: ACD82112 Among the 12 MII interfaces, 5 of them can be configured as reversed MII, to connect directly with standalone MAC controller devices. A MAC in the ACD82112 can be viewed logically as a PHY device if it is configured as the reversed MII interface. Reversed MII is intended for a CPU network interface, or an expansion port interface. INTRODUCTORY The ACD82112 is a single chip implementation of a 12port Fast Ethernet switch. Together with external SRAM devices and transceiver devices, it can be used to build a complete 10/100 Mbps Fast Ethernet switch. Each individual port can be either auto-sensing or manually selected to run at 10 Mbps or 100 Mbps speed rates and under Full or Half-duplex mode. terface to implement vendor-specific network management functionality. ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. 4. SYSTEM DESCRIPTION The Data is the encapsulated information within the Ethernet Packet. The ACD82112 does not process any of the data information in this field. The FCS (Frame Check Sequence) is a 32-bit field of CRC (Cyclic Redundancy Check) value based on the destination address, the source address, the type/length and the data field. The ACD82112 will verify the FCS field for each frame. The procedure for computing FCS is described in the section "FCS Calculation." Source Address and Destination Address After a frame is received by the ACD82112, the embedded destination address and source address are retrieved. The destination address is passed to the lookup table to find the destination port. The source address is automatically stored into the address lookup table. For applications that uses an external ARL, the ACD82112 will disable the internal lookup table and pass the DA and SA to the external ARL for address lookup and learning. Start of Frame Detection When a port's MAC is idle, assertion of the RXDV in the MII interface will cause the port to go into the receive state. The MII presents the received data in 4-bit nibbles that are synchronous to the receive clock (25Mhz or 2.5MHz). The ACD82112 will convert this data into a serial bit stream, and attempt to detect the occurrence of the SFD (10101011) pattern. All data prior to the detection of SFD are discarded. Once SFD is detected, the following frame data are forwarded and stored in the buffer of the switch. During the receive process, the Lookup Engine will attempt to match the destination address with the addresses stored in the address table. If there is a match found, a link between the source port and the destination port is then established. If an external ARL is used, the ACD82112 indicates the presence of 48-bit DA through the status line of the ARL interface. The external ARL will use the value of DA for address comparison and return a result of the lookup to the ACD82112. Frame Data Frame Reception Under normal operating conditions, the ACD82112 expects a received frame to have a minimum inter frame gap (IFG). The minimum IFG required by the device is 64 BT. In the event the ACD82112 receives a packet with IFG less than 64 BT, the ACD82112 does not guarantee to be able to receive the frame. The packet will be dropped if the ACD82112 cannot receive the frame. The device will check all received frames for errors such as symbol error, FCS error, short event, runt, long event, jabber, etc. Frames with any kind of error will not be forwarded to any port. Data Sheet: ACD82112 The preamble bit in the header of each frame will be used to synchronize the MAC logic with the incoming bit stream. The minimum length of the preamble is 0 bits and there is no limitation on the maximum length of preamble. After the receive data valid signal RXDV is asserted by the external PHY device, the port will wait for the occurrence of the SFD pattern (10101011) and then start a frame receiving process. Frame data are transparent to the ACD82112. The ACD82112 will forward the data to destination port(s) without interpreting the content of the frame data field. FCS Calculation Each port of the ACD82112 has a CRC checking logic to verify if the received frame has a correct FCS value. A wrong FCS value is an indication of a fragmented frame or a frame with frame bit error. The method of calculating the CRC value is using the following polynomial, G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 as a divider to divide the bit sequence of the incoming frame, beginning with the first bit of the destination address field, to the end of the data field. The result of the 5 INTRODUCTORY The Type/Len field is a 2-byte field that specifies the type (DIX Ethernet frame) or length (IEEE 802.3 frame) of the frame. The ACD82112 does not process this information. Preamble Bit Processing ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. The SA (Source Address) is a 48-bit field that contains the MAC address of the source DTE that is transmitting the frame to the ACD82112. After a frame is received with no error, the SA is learned as the port's MAC address. During the receiving process, the MAC will monitor the length of the received frame. Legal Ethernet frames should have a length of not less than 64 bytes and no more than 1518 bytes. If the carrier-sense signal of a frame is asserted for less than 76 BT, the frame is flagged with short event error. If the length of a frame is less then 512 BT, the frame is flagged with runt error. In order to support an application where extra byte length is required, an Extra long frame option is provided. When the Extra long frame option is enabled (Table-7.24, bit7), only frames longer than 1530 bytes are marked with a long event error. Frame length is measured from the first byte of DA to the last byte of FCS. In the event that there are more than 16 consecutive collisions, the ACD82112 will reset the counter to zero and retransmit the packet. This implementation insures there is no packet loss even under channel capture situation. However, the ACD82112 has an option to drop the packet on excessive collisions. When this option is enabled (Table-7.24, bit-11), the frame will be dropped after 16 consecutive collisions. If a port has encountered 256 consecutive collisions, it is assumed to be non-functional and will be partitioned. The partitioned port will not receive any frame. It will still transmit new frames, but without retry after encountering a collision. The partition port will be released once a new frame is transmitted without incurring a collision, which indicates that, the port has regained normal functions. False Carrier Events Frame Filtering Frames with any kind of error will be filtered. Types of error include code error (indicated by assertion of RXER signal), FCS error, alignment error, short event, runt, and long event. Any frame heading to its own source port will be filtered. When external ARL is used, the filtering decision will be made by the ARL. The ACD82112 will act in accordance with the ARL's direction. If the Spanning Tree Support option is enabled, frames containing DA equal to any reserved Bridge Management Group Address specified in Table 3.5 of the IEEE 802.1D will not be forwarded to any ports, except Port11, which may receive BPDU frames. If spanning tree support is not enabled, frames with DA equal to the reserved Group Address for PBDU will be broadcasted to all ports in the same VLAN of the source port. Jabber Lockup Protection If a receiving port is active continuously for more than 50,000 bit times, the port is considered to be jabbering. A jabbering port will automatically be partitioned from the switch system in order to prevent it from impairing the performance of the network. The partitioned port If the signal in the MII interface is asserted but the receive data valid (RXDV) signal is not, and the RXD shows 1110 at the same time, the port is considered to have a false carrier event. If a port has more than two consecutive false carrier events, the port will automatically be partitioned from the switch system. The partitioned port will be re-activated if it has been idling for 33,000 BT or it has received 500 bits of valid data after a minimum 64 BT idle period. Frame Forwarding If the first bit of the destination address is 0, the frame is handled as a unicast frame. The destination address is passed to the Address Resolution Logic; which returns a destination port number to identify which port the frame should be forwarded to. If the Address Resolution Logic cannot find any match for the destination address, the frame will be treated as a frame with unknown DA. The frame will be processed in one of two ways. If the option flood-to-all-port is enabled, the switch will forward the frame to all ports within the same VLAN of the source port, except the source port itself. If the option is not enabled, the frame will be forwarded to the `dumping port' of the source port VLAN only. The dumping port is determined by the VLAN ID of the source port. If the source port belongs to multiple VLANs, a frame with unknown DA will then be forwarded to multiple dumping ports of the VLANs. 6 Data Sheet: ACD82112 Excessive Collision INTRODUCTORY Illegal Frame Length will be re-activated as soon as the offending signal discontinues. ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. calculation, which is the residue after the polynomial division, is the value of the frame check sequence. This value should be equal to the FCS field appended at the end of the frame. If the value does not match the FCS field of the frame, the Frame Bit Error LED of the port will be turned on once and the packet will be dropped. The order of all broadcast frames with respect to the unicast frames is strictly enforced by the ACD82112. Shared Buffer All ports of the ACD82112 work in Store-And-Forward mode so that all ports can support both 10Mbps and 100Mbps data speeds. The ACD82112 utilizes a global memory buffer pool, which is shared by all ports. The device has a unique architecture that inherits the advantage of both output buffer-based and input bufferbased switches. The output buffer-based switches store the received data only once into the memory, and hence has a short latency. Whereas input buffer based switches typically have more efficient flow control. Data Sheet: ACD82112 If the first bit of the destination address is a 1, the frame is handled as a multicast or broadcast frame. The ACD82112 does not differentiate a multicast packet from a broadcast packet except for the reserved bridge management group address, as specified in Table 3.5 of IEEE 802.1D standard. The destination ports of a broadcast frame are all ports within the same VLAN except the source port itself. Starvation Control Scheme The MAC logic will abort the transmit process if a collision is detected through the assertion of the Col signal of the MII. Re-transmission of the frame is scheduled in accordance to the IEEE 802.3's truncated binary exponential backoff algorithm. If the transmit process has encountered 16 consecutive collisions, an excessive collision error is reported, and the ACD82112 will try to re-transmit the frame, unless the drop-on-excessivecollision option of the port is enabled. It will first reset the number of collisions to zero and then start the transmission after a 96 bit time of inter frame gap. If dropon-excessive-collision is enabled, the ACD82112 will not try to re-transmit the frame after 16 consecutive collisions. If collision is detected after 512 BT of the transmission, a late collision error will be reported, but the frame will still be retransmitted after proper backoff time. All frames received by the ACD82112 will be stored into a common physical frame buffer pool. In order to make sure all ports have fair access to the network, a buffer allocation scheme (starvation control) is used to prevent active ports from occupying all the buffers and starve off the less active ports. The frame buffer pool is divided into 3 portions: the reserved pool, the common pool and the extra pool, as shown in Figure-5.1: Figure-5.1: Buffer Partition Extra Pool (shared by all full duplex ports with flow control capability) ~80% Common Pool (shared by all the ports) ~50% Frame Generation During a transmit process, frame data is read out from the memory buffer and is forwarded to the destination port's PHY device in nibbles. 7 bytes of a preamble signal (10101010) will be generated first followed by the SFD (10101011), and then the frame data and 4 bytes of FCS are sent out at last. Reserved Pool (dedicated to each port) 7 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. The ACD82112 transmits all frames in accordance to IEEE 802.3 standard. The ACD82112 will send the frames with a guaranteed minimum interframe gap of 96 BT, even if the received frames have an IFG less than the minimum requirement. Before the transmit process is started, the MAC logic will check if the channel has been silent for more than 64 BT. Within the 64 BT silent window, the transmission process will defer on any receiving process. If the channel has been silent for more than 64 BT, the MAC will wait an additional 32 BT before starting the transmit process. In the event that the carrier sense signal is asserted by the MII during the wait period, the MAC logic will generate a JAM signal to cause a forced collision. INTRODUCTORY Frame Transmission The extra pool is reserved only for ports with pause frame based flow control capacity. It takes the remaining 20% of the total buffer. It is used to minimize the chance of frame dropping by buffering for the latency of the pause frame based flow control scheme. It is used only after a flow control mechanism is triggered. Flow Control Scheme Flow control activity is triggered when the buffer utilization exceeds certain thresholds specified by the dedicated registers. Register-10 is used to specify the Upper and the Lower Thresholds of the reserved buffer slot for each port. Register-11 is used to specify the Upper and the Lower thresholds of the broadcast queue. Under full duplex operation, if the buffer utilization of a port has exceeded the upper threshold of the reserved buffer slot, and the common pool has been used up, a max-pause-frame ( a pause frame with a maximum time interval of FFFFh) will be sent to the sending party to stop it from sending new frames. If pauseframe based flow control is not enabled at that port, the frame will be dropped. Once a max-pause-frame is sent, if the utilization of the reserved buffer slot of the port drops below the lower threshold, a minipause-frame (a pause frame with minimum time interval of 0) will be sent to the linking party to enable new frame transmission. Under half duplex operation, if the buffer utilization of a port has exceeded the upper threshold of the reserved buffer slot, and the common pool has been used up, the port will execute back-pressure based flow control by sending a jam pattern on each incoming frame. If backpressure flow control of the port is not enabled, the frame will be dropped. If the broadcast flow control is enabled (when bit-13 of register-25 is set), flow control will be triggered when Data Sheet: ACD82112 VLAN Support (Registers 23 & 24) The ACD82112 can support up to 4 port-based security VLANs. Each port of the ACD82112 can be assigned to up to four VLAN. On power up, every port is assigned to VLAN-I as the default VLAN. Frames from the source port will only be forwarded to destination ports within the same VLAN domain. A broadcast/multicast frame will be forwarded to all ports within the VLAN(s) of the source port. A unicast frame will be forwarded to the destination port only if the destination port is in the same VLAN as the source port. Otherwise, the frame will be treated as a frame with unknown DA. Each VLAN can be assigned with a dedicated dumping port. Multiple VLANs can also share a dumping port. Unicast frames with unknown destination addresses will be forwarded to the dumping port of the source port VLAN. Security VLAN can be disabled by setting the corresponding bit in the system configuration register (bit 8 of Register 16, see Table 7.15). When security VLAN is disabled, each VLAN becomes a Leaky VLAN and is equivalent to a broadcast domain. Four dumping ports of four different Leaky VLANs can be grouped together to form a fat pipe uplink (for example, port 0, port 1, port 2, and port 3 can be grouped to form an 800 Mbps uplink port). When multiple dumping ports are grouped as a single pipe, each port has to be assigned to one and only one VLAN. A unicast frame with a matched DA will be forwarded to any destination port, even if the VLAN ID is different. All unmatched DA packets will be forwarded to the designated dumping port of the source port VLAN. The broadcast and multicast packets will only be forwarded to the ports in the same VLAN of the source port. Therefore, a 200 to 800 Mbit/s pipe can be established by carefully grouping the dumping ports, and directly connecting with any segmentation switches. Dumping Port Each VLAN can be assigned with a dedicated dumping port. Multiple VLANs can share a dumping port. Each dumping port can be used for an up-link connection or for a DTE connection. That is, the dumping port can be used to connect the switch with a computer repeater 8 INTRODUCTORY The common pool provides a deep buffer for the busy ports (e.g. server port) to serve multiple low speed ports (e.g. client port) simultaneously. It helps to avoid head-of-line blocking. It takes about 30% of the total buffer and is shared by all ports. It stores the congested traffics before the flow control mechanism is triggered. the broadcast queue is longer than the upper threshold specified by Register-11. All full duplex ports with pause-frame capability will send a max-pause-frame to its linking party. All half-duplex ports with backpressure capability will jam incoming frames. After a max-pause-frame is sent, and if the broadcast queue is shorten below the lower threshold specified by Register-11, a mini-pause-frame will be sent to release the hold on transmission. ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. The reserved pool guarantees each port will have a fair network access possibility, even under the worst traffic congestion situation. It takes about 50% of the total buffer and is evenly allocated to each port as its dedicated buffer slot. The dedicated slot is not shared with other ports. * * A frame with a unicast destination address that does not match with any port's source address within the VLAN of the source port. A frame with a broadcast/multicast destination address*. Queue Management Each port of the ACD82112 has its own individual transmission queue. All frames coming into the ACD82112 are stored into the shared memory buffer, and are lined up in the transmission queues of the corresponding destination port. The order of all frames, unicast or broadcast, is strictly enforced by the ACD82112. The ACD82112 is designed with a non-blocking switching architecture. It is capable of achieving wire speed forwarding rates and can handle maximum traffic loads. Data Sheet: ACD82112 hub, a workgroup switch, a router, or any type of interconnection device compliant with IEEE 802.3 standard. ACD82112 will direct the following frames to the dumping port: *See Spanning Tree Support Mode of Operation (Register 18) All ports of the ACD82112 can work in half duplex mode or full duplex mode. If auto-negotiation is enabled, the mode is determined by the PHY device. Otherwise, the mode is assigned by the Full Duplex mode indication/ assignment register. MII Interface The MAC of each port of the ACD82112 interfaces with the port's PHY device through the standard MII interface. For reception, the received data (RXD) is sampled by the rising edge of the receive clock (RXCLK). Assertion of the receive data valid (RXDV) signal will cause the MAC to look for the start of SFD. For transmission, the transmit data enable (TXEN) signal is asserted when the first preamble nibble is sent on the transmit data (TXD) lines. The transmit data are clocked out by the falling edge of the transmit clock (TXCLK). INTRODUCTORY If the device is configured to work under Flood-to-AllPort mode (Register 25, bit 8), the frames with unknown DA will be forwarded to all the ports in the VLAN(s) of the source port except the source port itself. PHY Management The ACD82112 supports the Spanning Tree protocol. When Spanning Tree Support is enabled (Register-16 bit 1, see Table 7.15), frames from the CPU port (port 11) having a DA value equal to the reserved Bridge Management Group Address for BPDU will be forwarded to the port specified by the CPU. Frames from all other ports with a DA value equal to the Reserved Group Address for BPDU will be forwarded to the CPU port if the port is in the same VLAN of the CPU port. Port 11 is designed as the default CPU port. When Spanning Tree Support is disabled, all reserved group addresses for Bridge Management is treated as broadcast address, with the exception of the reserved multicast addresses for pause frame specified by IEEE802.3x. Every port of the ACD82112 can be set to block-andlisten mode through the CPU interface. In this mode, incoming frames with a DA value equal to the reserved Group Address for BPDU will be forwarded to the CPU port. Incoming frames with all other DA values will be dropped. Outgoing frames with a DA value equal to the Group Address for BPDU will be forwarded to the attached PHY device; all other outgoing frames will be filtered. The ACD82112 supports PHY device management through the serial MDIO and MDC signal lines. The ACD82112 can continuously poll the status of the PHY devices through the serial management interface, without CPU intervention. The ACD82112 will also configure the PHY capability field to ensure proper operation of the link. The ACD82112 also enables the CPU to access any registers in the PHY devices through the CPU interface. The ID of the PHY device can start from either "1" or "4", depending on the setting of bit-10 of register-25. Reversed MII Interface Five of the ACD82112's 12 ports can be configured with reversed MII interface. Reversed MII behaves as a PHY MII: the TXCLK, COL, RXD<3:0>, RXCLK, RXDV, CRS signals (names specified by IEEE 802.3u) become output signals of the ACD82112, and the TXER, TXD<3:0>, TXEN, RXER signals (names specified by IEEE 802.3u) become input signals of the ACD82112. The Reversed MII interface enables an external MAC device to be connected directly with the ACD82112. 9 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Spanning Tree Support The ACD82112 requires the use of ASRAM, or Flowthrough SSRAM as a memory buffer. Each read or write cycle takes up to 20 ns. For ASRAM, the access time should be at or less than 12 ns. For SSRAM, the speed should be at or higher than 100MHz. The SRAM interface contains a 52-bit data bus, a 17-bit address bus and 4 chip-select signals. The ACD82112 provides a wide variety of LED indicators for simple system management. The update of the LED is completely autonomous and merely requires low speed TTL or CMOS devices as LED drivers. The status display is designed to be flexible to allow the system designer to choose those indicators appropriate for the specification of the equipment. CPU Interface The ACD82112 does not require any microprocessor for operation. Initialization and most configurations can be done with the pull-up or pull-down of designated hardware pins. A CPU interface is provided for a microprocessor to access the control registers and status registers. The microprocessor can send a read command to retrieve the status of the switch, or send a write command to configure the switch through the interface. The interface is a commonly used UART type interface. The CPU interface can also be used to access the registers inside each PHY device connected with the ACD82112. There are two LED control signals, LEDVLD0 and LEDVLD1. They are used to indicate the start and end of the LED data signal presented on nLED0-nLED3. The LEDCLK signal is a 2.5MHz clock signal. The rising edge of LEDCLK should be used to latch the LED data signal into the LED driver circuitry. The LED data signals contain Lnk, Xmt, Rcv, Col, Err, Fdx and Spd, which represent Link status, Transmit status, Receive status, Collision indication, Frame error indication, Full duplex operation and Operational Speed status respectively. These status signals are sent out sequentially from port 11 to port 0, once every 50ms. For details about the timing diagrams of the LED signals, refer to the chapter of "Timing Description " ARL Interface Data Sheet: ACD82112 LED Interface INTRODUCTORY SRAM Interface The ACD82112 continuously sends out life pulses to the WCHDOG pin when it is operating properly. In a catastrophic event, the ACD82112 will not send the life pulse to cause the external watchdog circuitry to timeout and reset the switch system. The external ARL is connected through the ARL interface (Table-7.24, bit-9). It can tap the value of DA out of the memory interface bus, and execute a lookup process to map the value of the DA into a port number. It can also learn the SA values embedded in the received frames. The value of SA is used to build the address lookup table inside the ACD80800. MIB Interface Traffic activities on all ports of the ACD82112 can be monitored through the MIB interface. Through the MIB interface, a MIB device can view the frames transmitted from or received by any port. Therefore, the MIB device can maintain a record of traffic statistics for each port to support network management. Since all received data are stored into the memory buffer, and all transmitted data are retrieved from the memory buffer, the data of the activities can also be captured from the memory interface data bus. The status of each data transaction between the ACD82112 and the SRAM is displayed by dedicated status signal pins of the ACD82112. 10 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Life Pulse The ACD82112 has a built-in MAC address storage for up to 2,048 source addresses. If more than 2,048 addresses are needed, an external ARL (e.g. ACD80800) can be used to expand the address space to 11K entries. 6. INTERFACE DESCRIPTION Table-6.1: MII Interface Signals Name PxCRS PxRXDV PxRXCLK PxRXERR PxRXD0 PxRXD1 PxRXD2 PxRXD3 PxCOL PxTXEN PxTXCLK PxTXD0 PxTXD1 PxTXD2 PxTXD3 Type I I I I I I I I I O I O O O O Description Carrier sense Receive data valid Receive clock (25/2.5 MHz) Receive error Receive data bit 0 Receive data bit 1 Receive data bit 2 Receive data bit 3 Collision indication Transmit data valid Transmit clock (25/2.5 MHz) Transmit data bit 0 Transmit data bit 1 Transmit data bit 2 Transmit data bit 3 Type O I O I I I I I PxCOLR* O PxTXENR PxTXCLKR PxTXD0R PxTXD1R PxTXD2R PxTXD3R O O O O O O Description Carrier sense Transmit data valid Transmit clock (25/2.5 MHz) Transmit-Not-Ready Transmit data bit 0 Transmit data bit 1 Transmit data bit 2 Transmit data bit 3 Collision Indication/ Receive-Not-Ready* Receive data valid Receive clock (25/2.5 MHz) Receive data bit 0 Receive data bit 1 Receive data bit 2 Receive data bit 3 *Collision Indication for half-duplex, Receive-Not-Ready for full duplex only. For MII interface, signal PxRXDV, PxRXER and PxRXD0 through PxRXD3 are sampled by the rising edge of PxRXCLK. Signal PxTXEN, and PxTXD0 through PxTXD3 are clocked out by the falling edge of PxTXCLK. The detailed timing requirement is described in the chapter of "Timing Description" Ports 0, 1, 2, 3 and 11 can be configured as reversed MII ports (Register 28, the Reversed MII Enable register). These ports, when configured as "normal" MII, have the same characteristics as all other MII ports. However, when configured as reversed MII interface, they will behave logically like a PHY device, and can interface directly with a MAC device. The signal of reversed MII interface are described by Table-6.2: For reversed MII interface, signal PxRXDVR, and PxRXD0R through PxRXD3R are clocked out by the falling edge of PxRXCLKR. Signal PxTXENR, and PxTXD0R through PxTXD3R can be sampled by the falling edge or rising edge of PxTXCLKR, depends on the setting of bit 9 of Register-16. The timing behavior is described in the chapter of "Timing Description." PHY Management Interface All control and status registers of the PHY devices are accessible through the PHY management interface. The interface consists of two signals: MDC and MDIO, which are described in table-6.3. Table-6.3: PHY Management Interface Signals Name MDC MDIO Type O I/O Description PHY management clock (1.25MHz) PHY management data Frames transmitted on MDIO has the following format (Table-6.4): Table-6.4: MDIO Format Operation Write Read PRE 1...1 1...1 ST 01 01 OP 01 10 PHY-ID aaaaa aaaaa REG-AD rrrrr rrrrr TA 10 Z0 DATA d...d d...d IDLE Z Z 11 INTRODUCTORY The ACD82112 communicates with the external 10/100 Ethernet transceivers through standard MII interface. The signals of MII interface are described in Table-6.1: Name PxCRSR PxRXDVR PxRXCLKR PxRXERR PxRXD0R PxRXD1R PxRXD2R PxRXD3R ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. MII Interface (MII) Data Sheet: ACD82112 Table-6.2: Reversed MII Interface Signals Table-6.6: CPUDI Format Operation Write Read Command 0010XX11 0010XX01 Address 8-bit 8-bit Prior to any transaction, the ACD82112 will output thirtytwo bits of `1' as preamble signal. After the preamble, a 01 signal is used to indicate the start of the frame. For a write operation, the device will send a `01' to signal a write operation. Following the `01' write signal will be the 5 bit ID address of the PHY device and the 5 bit register address. A `10' turn around signal is then followed. After the turn around, the 16 bit of data will be written into the register. After the completion of the write transaction, the line will be left in a high impedance state. For a read operation, the ACD82112 will output a `10' to indicate read operation after the start of frame indicator. Following the `10' read signal will be the 5-bit ID address of the PHY device and the 5-bit register address. Then, the ACD82112 will cease driving the MDIO line, and wait for one bit time. During this time, the MDIO should be in a high impedance state. The ACD82112 will then synchronize with the next bit of `0" driven by the PHY device, and continue on to read 16 bits of data from the PHY device. The system designer can set the ID of the PHY devices as 1 for port 0, 2 for port 1, ... and 12 for port 11, when the PHYID option (Bit-10 of Register-25) is set to "0". If the PHYID option is set to "1", the corresponding PHY ID should set to 4 through 15. The detailed timing requirements on PHY management signals are described in the chapter of "Timing Description." Index 8-bit 8-bit Data 24-bit 24-bit Checksum 8-bit 8-bit A command sent by CPU comes through the CPUDI line. The command consists of 8 octets. Command frames transmitted on CPUDI have the following format (Table-6.6): The byte order of data in all fields follows the big-endian convention, i.e. most significant octet first. The bit order is the least significant order first. The Command octet specifies the type of the operation. Bit 2 and bit 3 of the command octet is used to specify the device ID of the chip. They are set by bit 16 and bit 17 of the Register 25 at power on strobing. The address octet specifies the type of the register. The index octet specifies the index of the register in a register array. For write operation, the Data field is a 3-octet value to specify what to write into the register. For read operation, the Data field is a 3-octet 0 as padded data. The checksum value is an 8-bit value of exclusive-OR of all octets in the frame, starting from the Command octet. For each valid command heading to it, the ACD82112 will always send a response. Response from the ACD82112 is sent through the CPUDO line. Response frames sent by the ACD82112 has the following format (Table-6.7): Table-6.7: Switch Response Format Response Write Read Command Result 00100011 8-bit 00100001 8-bit Data 24-bit 24-bit Checksum 8-bit 8-bit CPU Interface The ACD82112 includes a CPU interface to enable an external CPU to access the internal registers of the ACD82112. The signal used in the CPU is UART. The baud rate can be from 1200 bps to 76800 bps. The ACD82112 automatically detects the baud rate for each command, and returns the result at the same baud rate. The signals in CPU interface are described in Table6.5. Table-6.5: CPU Interface Signals Name CPUDI CPUDO CPUIRQ Type I O O Description CPU data input CPU data output CPU interrupt request The command octet specifies the type of the response. The result octet specifies the result of the execution. The Result field in a response frame is defined as: * * * * 00 for no error 01 for Checksum 10 for address incorrect 11 for MDIO waiting timeout For response to a read operation, the Data field is a 4octet value to indicate the content of the register. For response to a write operation, the Data field is 32 bits of 0. The checksum value is an 8-bit value of exclusive-OR of all octets in the response frame, starting from the Command octet. 12 CPUIRQ is used to notify the CPU that some special status has been encountered by the ACD82112, like port partition, fatal system error, etc. By clearing the appropriate bit in the interrupt mask register, one can stop the specific source from generating an interrupt request. Reading the interrupt source register retrieves the source of the interrupt request and clears the interrupt source register. All received frames are stored into the shared memory buffer through the SRAM interface. When the destination port is ready to transmit the frame, data is read from the shared memory buffer through the SRAM interface. The signals in SRAM interface are described in Table-6.8. Table-6.8: SRAM Interface Name Type Description DATA0 - DATA51 I/O memory data bus ADDR0 - ADDR16 O memory address bus nOE O output enable, low active nWE O write enable, low active nCS0 - nCS3 O chip select signals, low active. Data is written into the SRAM or read from the SRAM in 52-bit wide words. The data is a 48 bit wide value and the control is a 4 bit wide value. ADDR specifies the address of the word, and DATA contains the content of the word. Bit 0 ~ 47 of DATA bus are used to pass 48bit frame data. Bit 48 are used to indicate the start and end of a frame. Bit 49~51 are used to indicate the length of the data shown on first 48 bit of DATA bus. nOE and nWE are used to control the timing of read or write operation respectively. nCSx selects the SRAM chip corresponding to the word address. The timing requirement on SRAM access is described in "Timing Description" (Chapter-9). ARL Interface The ARL interface provides a communication path between the ACD82112 and an ARL device, which can provide up to 11K of address lookup. As the ACD82112 receives a frame, the destination address and source address of the frame are displayed on the ARLDO data lines for the external ARL device. After the external ARL finds the corresponding destination port, it returns the result through the ARLDIx lines to the ACD82112. The timing requirement on ARL signals is described in Chapter 9, "Timing Description." Table-6.9 shows the asso- ciated signals in ARL interface. The data signal is tapped from the DATA bus of the SRAM interface. Since all data of the received frames will be written into the shared memory through the DATA bus, the bus can be used to monitor occurrences of DA and SA values, indicated by the status signal of ARLSTAT. Therefore, ARLD0 through ARLD51 are the same signals of DATA0 through DATA51. The ARLDIR1 and ARLDIR0 are used to indicate the direction of data on the ARLDO bus: * 00: Idle * 01: For receiving data * 10: For transmitting data * 11: Header The ARLSYNC is used to indicate port 0 is driving the DATA bus. Since the bus is pre-allocated in time division multiplexing manner, the ARL device can determine which port is driving the DATA bus. The ARLSTAT are used to indicate the status of the data shown on the first 48 bit of DATA bus. The 4-bit status is defined as: * * * * * * * * * * * * * * 0000 - Idle 0001 - First word (DA) 0010 - Second word (SA) 0011 - Third through last word 0100 - Filter Event 0101 - Drop Event 0110 - Jabber 0111 - False Carrier/Deferred Transmission* 1000 - Alignment error/Single Collision* 1001 - Flow Control/Multiple Collision* 1010 - Short Event/Excessive Collision* 1011 - Runt/Late Collision* 1100 - Symbol Error 1101 - FCS Error 13 INTRODUCTORY SRAM Interface ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Name Type Description ARLDO0-RLDO51 O ARL data output, shared with DATA 0 - DATA 51 ARLDIR1-ARLDIR0 O ARL data direction indicator 00 for idle 01 for receive 10 for transmit 11 for control ARLSYNC O ARL port synchronization ARLSTAT0O ARL data state indicator ARLSTAT3 ARLCLK O ARL clock ARLDI0 - ARLDI3 I ARL data input ARLDIV I ARL input data valid Data Sheet: ACD82112 Table-6.9: ARL Interface Signals * * Type O O O O O O O Description LED signal valid #0 LED signal valid #1 2.5 MHz LED clock Dual purpose indicator Dual purpose indicator Dual purpose indicator Dual purpose indicator Signal Group 1 1 0 address learning status full duplex indication port speed (1=10Mbps,0=100Mbps) Link status 1110 - Long Event 1111 - Reserved LED Interface *Note: error type depends on the port is receiving or transmitting. ARLDIx is used to receive the lookup result from the external ARL. The result is returned by external ARL device through the ARLDIx lines. Returned data can be sampled by the rising or the falling edges of ARLCLK, depending on the setting of Bit-18 of Register-25. The ARL results have the following format: SID Signal Group 2 0 1 frame error indicator collision indication receiving activity transmit activity RSLT The signals in the LED interface is described in Table6.10: The status of each port is displayed on the LED interface for every 50ms. LEDVLD0 and LEDVLD1 are used to indicate the start and end of the LED data. LED data is clocked out by the falling edge of LEDCLK, and should be sampled by the rising edge of LEDCLK. LED data of port-11 are clocked out first, followed by port-10 down to port-0. All LED signals are low active. DID ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Where * SID is a 5-bit ID of the source port (0 - 11) * RSLT is a 2-bit result, defined as: 00 - reserved 01 - matched 10 - not matched 11 - forced discard * DID is a 5-bit ID of the destination port (0 - 11) INTRODUCTORY Name LEDVLD0 LEDVLD1 nLEDCLK nLED0 nLED1 nLED2 nLED3 Data Sheet: ACD82112 Table-6.10: LED Interface Signals The start of each ARL result is indicated by assertion of ARLDIV signal. 14 The default values of certain register bits are set by internal pull-high/pull-low with 75K Ohm resistors. These default values can be overwritten by external pull-high/ pull-low of certain designated pins with 4.7K Ohm external resistors. Table-6.11 lists all the available pins. The meanings of the register bits are described in the chapter of "Register Description." Table-6.12: Other Interface Name CLK50 nRESET WCHDOG VDD VSS Type I I O - Description 50 MHz clock input hardware reset watch dog life pulse signal 3.3 V power ground Data Sheet: ACD82112 Configuration Interface Table-6.11: Configuration Interface 30 20, inside the Internal ARL Default The CLK50 should come from a clock oscillator, with 0.01% (100 ppm) accuracy. The nRESET is a low-active hardware reset pin. Assertion of this pin will cause the ACD82112 to go through the power-up initialization process. All registers are set to their default value after reset. The VDD is 3.3V power supply. The WCHDOG pin is used to handle exceptional cases. A normal working ACD82112 sends out continuous life pulses from the WCHDOG pin, which can be monitored by an external watchdog circuit. If no life pulse is detected , the external watchdog circuit may force reset of the switch system. It is a safeguard against unforeseeable situations. INTRODUCTORY Other Interface (Table-6.12) ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. 25 Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 3 1 See Table-7.25 Register # See Table-7.30 Pin Name P7TXD0 P7TXD1 P7TXD2 P7TXD3 P6TXD0 P6TXD1 P6TXD2 P6TXD3 LEDCLK LEDVLD0 LEDVLD1 nLED3 nLED2 nLED1 nLED0 P5TXD0 P5TXD1 P5TXD2 P5TXD3 P0TXD0 P0TXD1 P0TXD2 P0TXD3 P1TXD0 P1TXD1 P1TXD2 P1TXD3 P2TXD3 P2TXD2 The VSS is power ground. 0 1 15 7. REGISTER DESCRIPTION Bit 0 1 2 3 4 5 6 7 Registers in the ACD82112 are used to define the operation mode of various function modules of the switch controller and the peripheral devices. Default values at power-on are defined by the factory. The management CPU (optional) can read the content of all registers and modify some of the registers to change the operation mode. Table-7.0 lists all the registers inside the switch controller. Description System initialization completed System error occurred Port partition occurred ARL Interrupt Default 0 Reserved Data Sheet: ACD82112 Table-7.1: INTSRC Register INTSRC register (register 1) SYSERR register (register 2) The SYSERR register indicates the presence of system errors. It is automatically cleared after each read. Table-7.2 lists all kind of system error. Table-7.0: Register List Name Reserved INTSRC SYSERR PAR PMERR ACT Reserved Reserved SAL SAH UTH BTH MAXL MAXH MINL MINH SYSCFG INTMSK SPEED LINK nFWD nBP nPORT PVID VPID POSCFG PAUSE DPLX RVSMII nPM ERRMSK CLKADJ PHYREG Reserved Type R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Size 8 Bit 12 Bit 12 Bit 12 Bit 12 Bit 24 Bit 24 Bit 16 Bit 16 Bit 16 Bit 16 Bit 16 Bit 16 Bit 16 Bit 8 Bit 12 Bit 12 Bit 12 Bit 12 Bit 12 Bit 4 Bit 5 Bit 20 Bit 12 Bit 12 Bit 5 Bit 12 Bit 8 Bit 4 Bit 16 Bit - Depth 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 4 1 1 1 1 1 1 1 * - Description Interrupt Source System Error Port Partition Indication PHY Management Error Port Avtivity Source Address, bit 23:0 Source Address, bit 47:24 Unicast Threshold Broadcast Threshold FCS of Max-Pause-Frame, bit 15:0 FCS of Max-Pause-Frame, bit 31:16 FCS of Min-Pause-Frame, bit 15:0 FCS of Min-Pause-Frame, bit 31:16 System Configuration Interrupt Mask Port Speed Port Link Port Forward Disable Port Back Pressure Disable Port Disable Port VLAN ID VLAN Dumping Port Power-On-Strobe Configuration Port Pause Frame Disable Port Duplex Mode Reversed MII Selection Port PHY Management Disable Error Mask ARL Clock Delay Adjustment Pointer to Registers in PHY devices - ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32-43 44-63 INTRODUCTORY The INTSRC register indicates the source of the interrupt request. Before the CPU starts to respond to an interrupt request, it should read this register to find out the interrupt source. This register is automatically cleared after each read. Table-7.1 lists all the bits of this register. 16 Description BIST failure indication Reserved Default The PMERR register indicates the presence of PHYs that have failed to respond to the PHY Management command issued through the MDIO line. This register is automatically cleared after each read. Table-7.4 describes all the bit of this register. 0 Table-7.4: PMERR Register 1 PAR register (register 3) 2 The PAR register indicates the presence of the partitioned ports and the port ID. A port can be automatically partitioned if there is a consecutive false carrier event, an excessive collision or a jabber. This register is automatically cleared after each read. Table-7.3 lists all the bits of this register. 3 4 5 6 Table-7.3: PAR Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 Description 0 - Port 0 is not partitioned. 1 - Port 0 is partitioned. 0 - Port 1 is not partitioned. 1 - Port 1 is partitioned. 0 - Port 2 is not partitioned. 1 - Port 2 is partitioned. 0 - Port 3 is not partitioned. 1 - Port 3 is partitioned. 0 - Port 4 is not partitioned. 1 - Port 4 is partitioned. 0 - Port 5 is not partitioned. 1 - Port 5 is partitioned. 0 - Port 6 is not partitioned. 1 - Port 6 is partitioned. 0 - Port 7 is not partitioned. 1 - Port 7 is partitioned. 0 - Port 8 is not partitioned. 1 - Port 8 is partitioned. 0 - Port 9 is not partitioned. 1 - Port 9 is partitioned. 0 - Port 10 is not partitioned. 1 - Port 10 is partitioned. 0 - Port 11 is not partitioned. 1 - Port 11 is partitioned. Default 7 8 9 10 11 Description 0 - Port 0's PHY responded 1 - Port 0's PHY failed to respond 0 - Port 1's PHY responded 1 - Port 1's PHY failed to respond 0 - Port 2's PHY responded 1 - Port 2's PHY failed to respond 0 - Port 3's PHY responded 1 - Port 3's PHY failed to respond 0 - Port 4's PHY responded 1 - Port 4's PHY failed to respond 0 - Port 5's PHY responded 1 - Port 5's PHY failed to respond 0 - Port 6's PHY responded 1 - Port 6's PHY failed to respond 0 - Port 7's PHY responded 1 - Port 7's PHY failed to respond 0 - Port 8's PHY responded 1 - Port 8's PHY failed to respond 0 - Port 9's PHY responded 1 - Port 9's PHY failed to respond 0 - Port 10's PHY responded 1 - Port 10's PHY failed to respond 0 - Port 11's PHY responded 1 - Port 11's PHY failed to respond Default 0 0 ACT register (register 5) The ACT register indicates the presence of transmit or receive activities of each port since the register was last read. This register is automatically cleared after each read. Table-7.5 describes all the bits of this register. 17 INTRODUCTORY Bit 0 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Bit 0 1 2 3 4 5 6 7 8 Data Sheet: ACD82112 PMERR register (register 4) Table-7.2: SYSERR Register 2 3 4 5 6 7 8 9 10 11 Default Table-7.10: UTH Register Bit Description Default* 7:0 Lower threshold of unicast utilization. 4,8,16,32 15:8 Higher threshold of unicast utilization. 8,24,64,144 * Note: The default value is related to the memory size specified by bit[6:5] of register 25. 0 SAL & SAH register (register 8,9) The SAL and SAH registers together contain the complete Source Address for pause frame generation. SAL contains the least significant 24 bit of the MAC address. SAH contains the most significant 24 bit of the MAC address. The default locally managed source address for pause frame generation is FEh-FFh-FFh-FFh-FFhFFh a. Table-7.8 and table-7.9 describes all the bits of these two registers. Table-7.8: SAL Register Bit 7:0 15:8 23:16 Description Default Bit 47:40 of the switch's MAC address. FEh Bit 39:32 of the switch's MAC address. FFh Bit 31:24 of the switch's MAC address. Table-7.9: SAH Register Bit 7:0 15:8 23:16 Description Default Bit 23:16 of the switch's MAC address. FFh Bit 15:8 of the switch's MAC address. Bit 7:0 of the switch's MAC address. BTH register (register 11) The BTH register contains the broadcast queue buffer threshold for each port. When the upper threshold is exceeded, the MAC may generate a max-pause-frame. When the lower threshold is crossed, the MAC may generate a mini-pause-frame. Table-7.11 describes each bit in this register. Table-7.11: BTH Register Bit 7:0 15:8 Description Lower threshold of broadcast queue Higher threshold of broadcast queue Default 16 48 MINL & MINH register (register 12,13) The MINL and MINH registers together contain the 32bit Frame Check Sequence (FCS) of the mini-pauseframe. MINL contains the least significant 16 bit of the FCS. MINH contains the most significant 16 bit of the FCS. The default FCS value assumes the default source address for the mini-pause-frame. Table-7.12 and table7.13 describe all the bits of these two registers. Table-7.12: MINL Register Bit 7:0 15:8 Description Default Bit 31:24 of the mini-pause-frame's FCS 89 Bit 23:16 of the mini-pause-frame's FCS O3 Table-7.13: MINH Register UTH register (register 10) The UTH register contains the unicast buffer thresholds for each port. When the upper threshold is exceeded, the MAC may generate a max-pause-frame. When the Bit 7:0 15:8 Description Bit 15:18 of the mini-pause-frame's FCS Bit 7:0 of the mini-pause-frame's FCS INTRODUCTORY 1 Description 0 - Port 0 no activity 1 - Port 0 has activity 0 - Port 1 no activity 1 - Port 1 has activity 0 - Port 2 no activity 1 - Port 2 has activity 0 - Port 3 no activity 1 - Port 3 has activity 0 - Port 4 no activity 1 - Port 4 has activity 0 - Port 5 no activity 1 - Port 5 has activity 0 - Port 6 no activity 1 - Port 6 has activity 0 - Port 7 no activity 1 - Port 7 has activity 0 - Port 8 no activity 1 - Port 8 has activity 0 - Port 9 no activity 1 - Port 9 has activity 0 - Port 10 no activity 1 - Port 10 has activity 0 - Port 11 no activity 1 - Port 11 has activity Default D7 A9 18 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Bit 0 lower threshold is crossed, the MAC may generate a mini-pause-frame. Table-7.10 describes each bit in this register. Data Sheet: ACD82112 Table-7.5: ACT register MAXL & MAXH register (register 14,15) Bit 7:0 15:8 Default 0 - BIST enabled; 1 - BIST disabled. 0 - Spanning Tree support disabled; 1 - Spanning Tree support enabled 0 - rising edge of RXCLK to latch RXD for MII 1 - falling edge of RXCLK to latch RXD for MII Reserved. Reserved. 0 - wait for CPU. 1 - system ready to start *This bit is used by the CPU when bit-15 of register-25 is set as "0" (for system with control CPU). The system will wait for CPU to set this bit. 0 - PHY Management not completed 1 - PHY Management completed. *This bit is used by the CPU when bit-15 of register-25 is set as "0" (for system with a control CPU). The MAC will not start until this bit is set sy the CPU. 0 - Watchdog function enabled. 1 - Watchdog function disabled. 0 - Secure VLAN checking rule enforced. 1 - Leaky VLAN checking rule enforced. 0 - Rising edge of RXCLK to latch data. 1 - Falling edge of RXCLK to latch data. *For Reversed MII port only. 0 - Late Back-Pressure scheme disabled 1 - Late Back-Pressure scheme enabled *When enabled, the MAC will generate backpressure only after reading the first bit of DA 0 - special handling of broadcast frames disabled 1 - special handling of broadcast frames enabled *When enabled, all broadcast frames from non-CPU port are forwarded to the CPU port only, and all broadcast frames from the CPU port are forwarded to all other ports. Software Reset: "1" to start a system reset to innitialize all state machines. Hardware Reset: "1" to stop the life pulse on the watchdog pin, which in turn will trigger the external watchdog circuitry to reset the whole system. Reserved Reserved 0 1 2 3 4 5 Description Default Bit 31:24 of the max-pause-frame's FCS 0D Bit 23:16 of the max-pause-frame's FCS 68 6 Table-7.15: MAXH Register Bit 7:0 15:8 Description Bit 15:8 of the max-pause-frame's FCS Bit 7:0 of the max-pause-frame's FCS Default D8 D0 7 8 SYSCFG register (register 16) The SYSCFG register specifies certain system configurations. The system options are described in the chapter of "Function Description." Table-7.16 describes all the bit of this register. INTMSK register (register 17) 9 10 11 The INTMSK register defines the valid interrupt sources allowed to assert interrupt request pin. Table-7.17 lists all the bits of this register. Table-7.17: INTMSK Register Bit 0 1 2 3 4 5 6 7 Description Enable "system initialization completion" to interrupt Enable "internal system error" to interrupt Enable "port partition event" to interrupt Enable "Internal ARL" to interrupt ARL Interupt Enable 12 Default 13 1 14 15 INTRODUCTORY Table-7.14: MAXL Register Description 0 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. The MAXL and MAXH registers together contain the 32-bit Frame Check Sequence (FCS) of the max-pauseframe. MAXL contains the least significant 16 bit of the FCS. MAXH contains the most significant 16 bit of the FCS. The default FCS value assumes the default source address for the max-pause-frame. Table-7.14 and table7.15 describe all the bits of these two registers. Data Sheet: ACD82112 Table-7.16: SYSCFG Register Bit Reserved 19 SPEED register (register 18) 1 2 3 4 Table-7.18: SPEED Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 Description 0 - Port 0 at 10Mbps 1 - Port 0 at 100Mbps 0 - Port 1 at 10Mbps 1 - Port 1 at 100Mbps 0 - Port 2 at 10Mbps 1 - Port 2 at 100Mbps 0 - Port 3 at 10Mbps 1 - Port 3 at 100Mbps 0 - Port 4 at 10Mbps 1 - Port 4 at 100Mbps 0 - Port 5 at 10Mbps 1 - Port 5 at 100Mbps 0 - Port 6 at 10Mbps 1 - Port 6 at 100Mbps 0 - Port 7 at 10Mbps 1 - Port 7 at 100Mbps 0 - Port 8 at 10Mbps 1 - Port 8 at 100Mbps 0 - Port 9 at 10Mbps 1 - Port 9 at 100Mbps 0 - Port 10 at 10Mbps 1 - Port 10 at 100Mbps 0 - Port 11 at 10Mbps 1 - Port 11 at 100Mbps 5 Default 6 7 8 9 10 11 0 Description 0 - Port 0 link not established 1 - Port 0 link established 0 - Port 1 link not established 1 - Port 1 link established 0 - Port 2 link not established 1 - Port 2 link established 0 - Port 3 link not established 1 - Port 3 link established 0 - Port 4 link not established 1 - Port 4 link established 0 - Port 5 link not established 1 - Port 5 link established 0 - Port 6 link not established 1 - Port 6 link established 0 - Port 7 link not established 1 - Port 7 link established 0 - Port 8 link not established 1 - Port 8 link established 0 - Port 9 link not established 1 - Port 9 link established 0 - Port 10 link not established 1 - Port 10 link established 0 - Port 11 link not established 1 - Port 11 link established Default 0 spanning tree algorithm discovers redundant links, the control CPU will allow only one link remaining in forwarding mode and force all other links into block-andlisten mode. Setting the associated bit in this register will put the port into block-and-listen mode. Table-7.20 Table-7.20: nFWD Register Bit 0 1 2 LINK register (register 19) 3 The LINK register specifies or indicates the link status of each port. It is read-only, unless bit-12 of register-25 is set (through POS, to disable automatic PHY management). At read-only mode, it indicates the result achieved by PHY management. At write-able mode, the control CPU can assign link status for each port. Table7.19 describes all the bit of this register. 4 5 6 7 8 nFWD register (register 20) 9 The nFWD register defines the forwarding mode of each port. Under forwarding mode, a port can forward all frames. Under block-and-listen mode, a port will not forward regular frames, except BPDU frames. If the 10 11 Description 0 - Port 0 in forwarding state. 1 - Port 0 in block-and-listen state. 0 - Port 1 in forwarding state. 1 - Port 1 in block-and-listen state. 0 - Port 2 in forwarding state. 1 - Port 2 in block-and-listen state. 0 - Port 3 in forwarding state. 1 - Port 3 in block-and-listen state. 0 - Port 4 in forwarding state. 1 - Port 4 in block-and-listen state. 0 - Port 5 in forwarding state. 1 - Port 5 in block-and-listen state. 0 - Port 6 in forwarding state. 1 - Port 6 in block-and-listen state. 0 - Port 7 in forwarding state. 1 - Port 7 in block-and-listen state. 0 - Port 8 in forwarding state. 1 - Port 8 in block-and-listen state. 0 - Port 9 in forwarding state. 1 - Port 9 in block-and-listen state. 0 - Port 10 in forwarding state. 1 - Port 10 in block-and-listen state. 0 - Port 11 in forwarding state. 1 - Port 11 in block-and-listen state. Default 0 20 INTRODUCTORY Bit 0 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. The SPEED register specifies or indicates the speed rate of each port. It is read-only, unless the bit-12 of register-25 is set (through POS to disable automatic PHY management). At read-only mode, it indicates the speed achieved through PHY management. At the writeable mode, the control CPU will be able to assign speed rate for each port. Table-7.18 describes all the bit of this register. Data Sheet: ACD82112 Table-7.19: LINK Register nBP register (register 21) 1 The nBP register defines back-pressure flow control capability for each port. Table-7.21 describes all the bit of this register. 2 3 Table-7.21: nBP Register Bit Description Default 0 0 - Port 0 back-pressure scheme enabled 1 - Port 0 back pressure scheme disabled 1 0 - Port 1 back-pressure scheme enabled 1 - Port 1 back pressure scheme disabled 2 0 - Port 2 back-pressure scheme enabled 1 - Port 2 back pressure scheme disabled 3 0 - Port 3 back-pressure scheme enabled 1 - Port 3 back pressure scheme disabled 4 0 - Port 4 back-pressure scheme enabled 1 - Port 4 back pressure scheme disabled 5 0 - Port 5 back-pressure scheme enabled 1 - Port 5 back pressure scheme disabled 0 6 0 - Port 6 back-pressure scheme enabled 1 - Port 6 back pressure scheme disabled 7 0 - Port 7 back-pressure scheme enabled 1 - Port 7 back pressure scheme disabled 8 0 - Port 8 back-pressure scheme enabled 1 - Port 8 back pressure scheme disabled 9 0 - Port 9 back-pressure scheme enabled 1 - Port 9 back pressure scheme disabled 10 0 - Port 10 back-pressure scheme enabled 1 - Port 10 back pressure scheme disabled 11 0 - Port 11 back-pressure scheme enabled 1 - Port 11 back pressure scheme disabled 4 5 6 7 8 9 10 11 Description 0 - Port 0 enabled 1 - Port 0 disabled 0 - Port 1 enabled 1 - Port 1 disabled 0 - Port 2 enabled 1 - Port 2 disabled 0 - Port 3 enabled 1 - Port 3 disabled 0 - Port 4 enabled 1 - Port 4 disabled 0 - Port 5 enabled 1 - Port 5 disabled 0 - Port 6 enabled 1 - Port 6 disabled 0 - Port 7 enabled 1 - Port 7 disabled 0 - Port 8 enabled 1 - Port 8 disabled 0 - Port 9 enabled 1 - Port 9 disabled 0 - Port 10 enabled 1 - Port 10 disabled 0 - Port 11 enabled 1 - Port 11 disabled Default 0 INTRODUCTORY Bit 0 Table-7.23: PVID Register Bit 0 1 2 3 Description 0 - port not in VLAN-I. 1 - port in VLAN-I. 0 - port not in VLAN-II. 1 - port in VLAN-II. 0 - port not in VLAN-III. 1 - port in VLAN-III. 0 - port not in VLAN-IV. 1 - port in VLAN-IV. Default 1 0 nPORT register (register 22) VPID register (register 24) The nPORT register is used to isolate ports from the network. Setting the associated bit in this register will stop a port from receiving or transmitting any frame. Table-7.22 describes all the bits of this register. The VPID registers specify the dumping port for each VLAN. There are 4 VPID 5-bit registers, one for each VLAN. A valid VPID are "0" through "11" (other values are reserved and should not used). Table-7.24 describes all the bits of this register. PVID register (register 23) Table-7.24: VPID Registers (4 registers) The PVID registers assign VLAN IDs for each port. There are 12 PVID registers, one for each port. A PVID consists of 4 bits, each corresponding to one of the 4 VLANs. A port can belong to more than one VLAN at the same time. Table-7.23 describes all the bits of this register. Data Sheet: ACD82112 Table-7.22: nPORT Register Bit 4:0 4:0 4:0 4:0 Description Dumping port ID for VLAN-1 Dumping port ID for VLAN-2 Dumping port ID for VLAN-3 Dumping port ID for VLAN-4 Default "00000" "11111" dumping port not defined 21 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. describes all the bit of this register. 6:5 7 8 9 10 11 12 13 14 15 17:16 18 POSCFG register (register 25) The POSCFG register specifies a certain configuration setting for the switch system. The default values of this register can be changed through pull-up/pull-down of specific pins, as described in the "Configuration Interface" section of the "Interface Description" chapter. Table-7.25 describes all the bit of this register. 22 INTRODUCTORY 4 Description Default 8 timing adjustment levels for SRAM Read data latching: 0000 0000 - no delay 0001 - level 1 delay 0011 - level 2 delay 0101 - level 3 delay 0111 - level 4 delay 1001 - level 5 delay 1011 - level 6 delay 1101 - level 7 delay 1111 - level 8 delay 0 - Absolute address mode: 1 row of 512K words, nCS2=ADDR17, nCS3=ADDR18 0 1 - Chip-Select address mode: 4 rows of 128K words, nCS[3:0] to select 4 rows of memory SRAM size selection: 01 00 - 64K words 01 - 128K words 10 - 256k words 11 - 512K words 0 - Long Event defined as frame longer than 1518 byte. 1 1 - Long Event defined as frame longer than 1530 byte. 0 - Frames with unknown DA forwarded to the dumping port. 1 1 - Frames with unknown DA forwarded to all ports. 0 - Internal ARL selected (2K MAC address entry). 0 1 - External ARL selected (11K MAC address entry). 0 - PHY IDs start from 1, range from 1 to 12. 1 1 - PHY IDs start from 4, range from 4 to 15. 0 - Re-transmit after excessive collision. 0 1 - Drop after excessive collision. 0 - Automatic PHY Management enabled 0 1 - Automatic PHY Management disabled: the control CPU need to update the SPEED, LINK, DPLX and nPAUSE registers Reserved 0 0 - Sysem errors will trigger software reset 0 1 - Sysem errors will trigger hardware reset 0 - System start itself without a control CPU 0 1 - System start after system-ready bit in register-16 is set by the control CPU 2-bit device ID for UART communication. The device responses only to UART commands with 00 matching ID 0 - Rising edge of ARLCLK to latch ARLDI. 1 1 - Falling edge of ARLCLK to latch ARLDI. ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Bit 3:0 Data Sheet: ACD82112 Table-7.25: POSCFG Register PAUSE register (register 26) 1 2 Table-7.26: PAUSE Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 Description 0 - Port 0 Pause-Frame disabled 1 - Port 0 Pause-Frame enabled 0 - Port 1 Pause-Frame disabled 1 - Port 1 Pause-Frame enabled 0 - Port 2 Pause-Frame disabled 1 - Port 2 Pause-Frame enabled 0 - Port 3 Pause-Frame disabled 1 - Port 3 Pause-Frame enabled 0 - Port 4 Pause-Frame disabled 1 - Port 4 Pause-Frame enabled 0 - Port 5 Pause-Frame disabled 1 - Port 5 Pause-Frame enabled 0 - Port 6 Pause-Frame disabled 1 - Port 6 Pause-Frame enabled 0 - Port 7 Pause-Frame disabled 1 - Port 7 Pause-Frame enabled 0 - Port 8 Pause-Frame disabled 1 - Port 8 Pause-Frame enabled 0 - Port 9 Pause-Frame disabled 1 - Port 9 Pause-Frame enabled 0 - Port 10 Pause-Frame disabled 1 - Port 10 Pause-Frame enabled 0 - Port 11 Pause-Frame disabled 1 - Port 11 Pause-Frame enabled Default 3 4 5 6 7 8 1 9 10 11 Description 0 - Port 0 under half duplex mode 1 - Port 0 under full duplex mode 0 - Port 1 under half duplex mode 1 - Port 1 under full duplex mode 0 - Port 2 under half duplex mode 1 - Port 2 under full duplex mode 0 - Port 3 under half duplex mode 1 - Port 3 under full duplex mode 0 - Port 4 under half duplex mode 1 - Port 4 under full duplex mode 0 - Port 5 under half duplex mode 1 - Port 5 under full duplex mode 0 - Port 6 under half duplex mode 1 - Port 6 under full duplex mode 0 - Port 7 under half duplex mode 1 - Port 7 under full duplex mode 0 - Port 8 under half duplex mode 1 - Port 8 under full duplex mode 0 - Port 9 under half duplex mode 1 - Port 9 under full duplex mode 0 - Port 10 under half duplex mode 1 - Port 10 under full duplex mode 0 - Port 11 under half duplex mode 1 - Port 11 under full duplex mode Default 0 INTRODUCTORY Bit 0 RVSMII register (register 28) The RVSMII register defines the reversed MII mode for each port. Table-7.28 describes all the bits of this register. Table-7.28: RVSMII register DPLX register (register 27) The DPLX register specifies or indicates the half/fullduplex mode of each port. It is read-only, unless bit-12 of register-25 is set (through POS, to disable automatic PHY management). At read-only mode, it indicates the result achieved by the PHY management. At write-able mode, the control CPU can assign a half-duplex or fullduplex mode for each port. Table-7.27 describes all the bits of this register. Bit 0 1 2 3 4 Description 0 - Port 0 under normal MII mode 1 - Port 0 under reversed MII mode 0 - Port 1 under normal MII mode 1 - Port 1 under reversed MII mode 0 - Port 2 under normal MII mode 1 - Port 2 under reversed MII mode 0 - Port 3 under normal MII mode 1 - Port 3 under reversed MII mode 0 - Port 11 under normal MII mode 1 - Port 11 under reversed MII mode Default 0 23 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. The PAUSE register defines the pause-frame based flow control capability of each port. Table-7.26 describes all the bits of this register. Data Sheet: ACD82112 Table-7.27: DPLX Register CLKADJ register (register 31) The nPM register indicates the automatic PHY management capability of each port. If a bit is set in this register, the corresponding SPEED, LINK, DPLX, and PAUSE status registers of a port will remain unchanged. Table-7.29 describes all the bits of this register. The CLKADJ register defines the delay time of the ARLCLK relative to the transition edge of the data signals. The ARLCLK provides reference timing for supporting chips, such as the ACD80800 and the ACD80900, which need to snoop the data bus for certain activities. Table-7.31 describes all the bits of this register. Table-7.29: nPM Register Description 0 - Port 0's status update enabled 1 - Port 0's status update disabled 0 - Port 1's status update enabled 1 - Port 1's status update disabled 0 - Port 2's status update enabled 1 - Port 2's status update disabled 0 - Port 3's status update enabled 1 - Port 3's status update disabled 0 - Port 4's status update enabled 1 - Port 4's status update disabled 0 - Port 5's status update enabled 1 - Port 5's status update disabled 0 - Port 6's status update enabled 1 - Port 6's status update disabled 0 - Port 7's status update enabled 1 - Port 7's status update disabled 0 - Port 8's status update enabled 1 - Port 8's status update disabled 0 - Port 9's status update enabled 1 - Port 9's status update disabled 0 - Port 10's status update enabled 1 - Port 10's status update disabled 0 - Port 11's status update enabled 1 - Port 11's status update disabled 2 3 4 5 6 7 8 9 10 11 Table-7.31: CLKADJ Register Bit 0 3:1 0 Description 0 - ARLCLK not inverted 1 - ARLCLK inverted ARLCLK delay levels: 000 - level 0 delay 001 - level 1 delay 010 - level 2 delay 011 - level 3 delay 100 - level 4 delay 101 - level 5 delay 110 - level 6 delay 111 - level 7 delay Default 0 000 PHYREG register (register 32-44) The PHYREG refers to the registers residing on the PHY devices. The ACD82112 merely provides an access path for the control CPU to access the registers on the PHYs. For detailed information about these registers, please refer to the PHY data sheet. ERRMSK register (register 30) The ERRMSK register defines certain errors as system errors. It is reserved for factory use only. Table7.30 lists all the error masks specified by this register. Register-32 through Register-44 are assigned to PHY0 through PHY-11 respectively. The contents of these registers are the register IDs inside the corresponding PHYs. For example, a "4" in Register-44 will point to the Control Register-4 inside PHY-11. Table-7.30: ERRMSK register Bit 0 1 2 3 4 5 6 7 INTRODUCTORY 1 Default Description Default Reserved 1 24 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Bit 0 Data Sheet: ACD82112 nPM register (register 29) Data Sheet: ACD82112 8. PIN DESCRIPTIONS Figure-8.1: Pin Diagram/Bottom View 26 25 24 23 22 21 INTRODUCTORY 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AE AB AC Y W V U T R P N M L K J H G F E D C B A ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. AD AF AA Table-8.1: Thermal Ground Pins Pin L[11:16] M[11:16] N[11:16] P[11:16] R[11:16] T[11:16] Signal I/O Type VSS Ground/Thermal 25 Table-8.2: Pin List By Location 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I/O I/O O O O O O O O O O O O O O O I O I/O I I I O I I I I/O I/O O O O O O O O I/O O O O O O I I/O O O I I I O I I I I/O I/O 3.3V I 3.3V I 3.3V I 3.3V O 3.3V I 3.3V I 3.3V 3.3V I/O O 3.3V 3.3V 3.3V I O O 3.3V 3.3V 3.3V 3.3V 3.3V I I I/O I/O I 3.3V I 3.3V I D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E01 E02 E03 E04 E23 E24 E25 E26 F 01 F 02 F 03 F 04 F 23 F 24 F 25 F 26 G01 G02 G03 G04 G23 G24 G25 G26 H01 H02 H03 H04 H23 H24 H25 H26 J01 J02 J03 J04 J23 J24 J25 J26 K 01 K 02 K 03 K 04 K 23 K 24 K 25 K 26 L 01 L 02 L 03 L 04 L 23 L 24 L 25 L 26 M01 M02 M03 M04 M23 M24 M25 M26 N01 N02 N03 N04 N23 N24 N25 N26 AR L S Y NC VS S VS S P 11R X D3R VS S P 11R X D1R VS S P 11T X ENR P 11COL R VS S P 10R X ER P 10T X D2 VS S P 9R X D0 P 9T X D1 P 9T X D2 DAT A43 DAT A42 AR L DIR 0 AR L DIR 1 P 9R X DV P 9T X EN P 9COL P 9CR S DAT A41 DAT A40 VDD VS S P 9T X D0 P 9T X D3 P 8R X D3 P 8R X D2 DAT A39 DAT A38 VDD VS S VS S VDD P 8R X DV P 8R X CL K DAT A37 DAT A36 L ED2 L ED3 P 8R X D1 P 8R X D0 P 8R X ER P 8T X D0 DAT A35 DAT A34 VDD VS S P 8T X CL K P 8T X EN P 8T X D1 P 8T X D2 DAT A33 DAT A32 VDD VS S VS S VDD P 8T X D3 P 8COL DAT A31 DAT A30 L ED1 L ED0 P 8CR S P 7R X D3 P 7R X D2 P 7R X D1 DAT A29 DAT A28 VDD VS S P 7R X D0 P 7R X DV P 7R X CL K P 7R X ER DAT A27 DAT A26 L EDVL D1 L EDVL D0 VS S VDD P 7T X CL K P 7T X EN 3.3V O 3.3V I 3.3V I 3.3V 3.3V O I/O 3.3V 3.3V I O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I O O I/O I/O O O I O I I I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V O O I I I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I I I/O I/O I/O I/O I I I O I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I O O O I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V O I I/O I/O I/O I/O I I I I I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I I I I I/O I/O I/O I/O 3.3V 3.3V I O P 01 P 02 P 03 P 04 P 23 P 24 P 25 P 26 R 01 R 02 R 03 R 04 R 23 R 24 R 25 R 26 T 01 T 02 T 03 T 04 T 23 T 24 T 25 T 26 U01 U02 U03 U04 U23 U24 U25 U26 V01 V02 V03 V04 V23 V24 V25 V26 W01 W02 W03 W04 W23 W24 W25 W26 Y 01 Y 02 Y 03 Y 04 Y 23 Y 24 Y 25 Y 26 AA01 AA02 AA03 AA04 AA23 AA24 AA25 AA26 AB 01 AB 02 AB 03 AB 04 AB 23 AB 24 AB 25 AB 26 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 DAT A25 DAT A24 VDD VS S P 7T X D0 P 7T X D1 P 7T X D2 P 7T X D3 DAT A23 DAT A22 VDD VS S P 7COL P 7CR S P 6R X D3 P 6R X D2 DAT A21 DAT A20 L EDCL K CP UIR Q P 6R X D1 P 6R X D0 P 6R X DV P 6R X CL K DAT A19 DAT A18 VDD VS S VS S VDD P 6R X ER P 6T X CL K DAT A17 DAT A16 VDD VS S P 6T X D0 P 6T X EN P 6T X D1 P 6T X D2 DAT A15 DAT A14 CP UDO CP UDI P 6CR S P 6COL P 6T X D3 P 5R X D3 DAT A13 DAT A12 VDD VS S VS S VDD P 5R X D1 P 5R X D2 DAT A11 DAT A10 MDIO WCHDOG P 5T X CL K P 5R X ER P 5R X DV P 5R X D0 DAT A9 MDC DAT A8 VS S P 5T X D3 P 5T X D0 P 5T X EN P 5R X CL K DAT A7 DAT A6 nR ES ET VS S P 0COL R P 0T X ENR VS S P 0R X D3R P 1T X D1R VS S P 1R X D0R P 2CR S R P 2T X D1R VS S P 2R X DVR P 2R X D3R 3.3V 3.3V I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I/O I/O I/O I/O I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I I I I I/O I/O I/O O I I I I I/O I/O 3.3V 3.3V 3.3V 3.3V I I I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I/O O I/O I/O I/O I/O I/O I I I I/O I I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I I I/O I/O I/O O I I I I I/O O I/O I I/O I/O O I I/O I/O I 3.3V 3.3V I/O O 3.3V 3.3V I I/O 3.3V 3.3V 3.3V I I/O O 3.3V 3.3V I I AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF 01 AF 02 AF 03 AF 04 AF 05 AF 06 AF 07 AF 08 AF 09 AF 10 AF 11 AF 12 AF 13 AF 14 AF 15 AF 16 AF 17 AF 18 AF 19 AF 20 AF 21 AF 22 AF 23 AF 24 AF 25 AF 26 VS S P 3T X ENR P 3R X D0R VS S P 4T X D1 P 4R X CL K VS S P 5COL P 5T X D2 P 5T X D1 DAT A5 DAT A4 VDD P 0CR S R P 0T X D1R P 0T X CL K R VDD P 1CR S R P 1T X D0R VDD P 1R X DVR P 1R X D3R P 2T X D2R VDD P 2R X CL K R P 2R X D2R VDD P 3T X D0R P 3R X DVR VDD P 4COL P 4T X D0 P 4R X DV VDD P 4R X D3 P 5CR S DAT A3 DAT A2 VS S P 0T X D3R P 0T X D0R P 0R X CL K R P 0R X D0R P 1COL R P 1T X D2R P 1T X CL K R P 1R X CL K R P 1R X D2R P 2T X D3R P 2T X ENR P 2R X ER R P 2R X D1R P 3COL R P 3T X D2R P 3T X CL K R P 3R X CL K R P 3R X D2R P 4CR S P 4T X D2 P 4R X ER P 4R X D1 P 4R X D2 DAT A1 DAT A0 CL K 50 P 0T X D2R P 0R X ER R P 0R X DVR P 0R X D1R P 0R X D2R P 1T X D3R P 1T X ENR P 1R X ER R P 1R X D1R P 2COL R P 2T X D0R P 2T X CL K R P 2R X D0R P 3CR S R P 3T X D3R P 3T X D1R P 3R X ER R P 3R X D1R P 3R X D3R P 4T X D3 P 4T X EN P 4T X CL K P 4R X D0 3.3V 3.3V O I 3.3V 3.3V O I 3.3V 3.3V 3.3V 3.3V 3.3V I I/O I/O I/O I/O 3.3V 3.3V 3.3V I/O I/O I/O 3.3V 3.3V I/O I/O 3.3V 3.3V 3.3V I I O 3.3V 3.3V I/O I 3.3V 3.3V O I 3.3V 3.3V 3.3V I O I 3.3V 3.3V 3.3V 3.3V I I I/O I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I/O I/O I/O I I/O I/O I/O I/O I O O I I I/O O I/O I/O I I O I I I I/O I/O I I/O I I I I I/O O I I I/O O I/O I I/O O O I I I O O I I 26 INTRODUCTORY DAT A51 DAT A50 S T AT 1 S T AT 3 ADDR 9 ADDR 8 ADDR 7 ADDR 6 ADDR 5 nWE nCS 0 ADDR 4 ADDR 3 ADDR 2 ADDR 1 ADDR 0 P 11R X ER R P 11T X D1R P 11CR S R P 10R X D3 P 10R X D1 P 10R X DV P 10T X D0 P 10COL P 9R X D3 P 9R X D1 DAT A49 DAT A48 S T AT 0 S T AT 2 ADDR 10 ADDR 11 ADDR 12 ADDR 13 ADDR 14 nOE ADDR 15 ADDR 16 nCS 2 nCS 3 nCS 1 P 11R X DVR P 11R X CL K R P 11T X D0R P 11T X D2R P 10R X D2 P 10R X D0 P 10T X CL K P 10T X D1 P 10CR S P 9R X D2 P 9R X ER DAT A47 DAT A46 VDD AR L DIV VDD AR L DI2 VDD AR L DI0 VDD VDD AR L CL K VDD VDD P 11R X D2R VDD P 11R X D0R VDD P 11T X CL K R P 11T X D3R VDD P 10R X CL K P 10T X EN P 10T X D3 VDD P 9R X CL K P 9T X CL K DAT A45 DAT A44 VS S VS S AR L DI3 VS S VS S AR L DI1 VS S VS S ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B 01 B 02 B 03 B 04 B 05 B 06 B 07 B 08 B 09 B 10 B 11 B 12 B 13 B 14 B 15 B 16 B 17 B 18 B 19 B 20 B 21 B 22 B 23 B 24 B 25 B 26 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 Data Sheet: ACD82112 Pin Signal Name I/O Type Pin Signal Name I/O Type Pin Signal Name I/O Type Pin Signal Name I/O Type Pin Signal Name 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V A16 A15 A14 A13 A12 A09 A08 A07 A06 A05 B 05 B 06 B 07 B 08 B 09 B 11 B 12 C11 C08 D08 C06 D05 E03 E04 C04 D11 AF 03 W04 W03 T 04 AF 02 AF 01 AE02 AE01 AD02 AD01 AC02 AC01 AB 03 AB 01 AA02 AA01 Y 02 Y 01 W02 W01 V02 V01 U02 U01 T 02 T 01 R 02 R 01 P 02 P 01 N02 N01 M02 M01 L 02 L 01 K 02 K 01 J02 J01 H02 H01 G02 G01 F 02 F 01 E02 E01 D02 D01 C02 C01 B 02 B 01 A02 A01 L 04 L 03 H03 H04 T 03 N04 L EDVL D1 MDC MDIO nCS 0 nCS 1 nCS 2 nCS 3 nOE nR ES ET nWE P 0COL R P 0CR S R P 0R X CL K R P 0R X D0R P 0R X D1R P 0R X D2R P 0R X D3R P 0R X DVR P 0R X ER R P 0T X CL K R P 0T X D0R P 0T X D1R P 0T X D2R P 0T X D3R P 0T X ENR P 1COL R P 1CR S R P 1R X CL K R P 1R X D0R P 1R X D1R P 1R X D2R P 1R X D3R P 1R X DVR P 1R X ER R P 1T X CL K R P 1T X D0R P 1T X D1R P 1T X D2R P 1T X D3R P 1T X ENR P 2COL R P 2CR S R P 2R X CL K R P 2R X D0R P 2R X D1R P 2R X D2R P 2R X D3R P 2R X DVR P 2R X ER R P 2T X CL K R P 2T X D0R P 2T X D1R P 2T X D2R P 2T X D3R P 2T X ENR P 3COL R P 3CR S R P 3R X CL K R P 3R X D0R P 3R X D1R P 3R X D2R P 3R X D3R P 3R X DVR P 3R X ER R P 3T X CL K R P 3T X D0R P 3T X D1R P 3T X D2R P 3T X D3R P 3T X ENR P 4COL P 4CR S P 4R X CL K P 4R X D0 P 4R X D1 P 4R X D2 P 4R X D3 P 4R X DV P 4R X ER P 4T X CL K P 4T X D0 P 4T X D1 P 4T X D2 P 4T X D3 P 4T X EN P 5COL P 5CR S P 5R X CL K O O O O O O O O O O O O O O O O O O I I I I O O I O I I I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I/O O I/O O O O O I/O I O I/O I/O I/O I I I I I I I/O I/O I/O I/O I/O O I/O I/O I/O I I I I I I I/O I/O I/O I/O I/O O I/O I/O I/O I I I I I I I/O O O O O O I/O I/O I/O I I I I I I I/O O O O O O I I I I I I I I I I O O O O O I I I Pin Signal Name N03 AB 02 AA03 A11 B 15 B 13 B 14 B 10 AC03 A10 AC05 AD04 AE06 AE07 AF 07 AF 08 AC08 AF 06 AF 05 AD06 AE05 AD05 AF 04 AE04 AC06 AE08 AD08 AE11 AC11 AF 12 AE12 AD12 AD11 AF 11 AE10 AD09 AC09 AE09 AF 09 AF 10 AF 13 AC12 AD15 AF 16 AE16 AD16 AC16 AC15 AE15 AF 15 AF 14 AC13 AD13 AE13 AE14 AE17 AF 17 AE20 AC19 AF 21 AE21 AF 22 AD19 AF 20 AE19 AD18 AF 19 AE18 AF 18 AC18 AD21 AE22 AC22 AF 26 AE25 AE26 AD25 AD23 AE24 AF 25 AD22 AC21 AE23 AF 23 AF 24 AC24 AD26 AB 26 P 5R X D0 P 5R X D1 P 5R X D2 P 5R X D3 P 5R X DV P 5R X ER P 5T X CL K P 5T X D0 P 5T X D1 P 5T X D2 P 5T X D3 P 5T X EN P 6COL P 6CR S P 6R X CL K P 6R X D0 P 6R X D1 P 6R X D2 P 6R X D3 P 6R X DV P 6R X ER P 6T X CL K P 6T X D0 P 6T X D1 P 6T X D2 P 6T X D3 P 6T X EN P 7COL P 7CR S P 7R X CL K P 7R X D0 P 7R X D1 P 7R X D2 P 7R X D3 P 7R X DV P 7R X ER P 7T X CL K P 7T X D0 P 7T X D1 P 7T X D2 P 7T X D3 P 7T X EN P 8COL P 8CR S P 8R X CL K P 8R X D0 P 8R X D1 P 8R X D2 P 8R X D3 P 8R X DV P 8R X ER P 8T X CL K P 8T X D0 P 8T X D1 P 8T X D2 P 8T X D3 P 8T X EN P 9COL P 9CR S P 9R X CL K P 9R X D0 P 9R X D1 P 9R X D2 P 9R X D3 P 9R X DV P 9R X ER P 9T X CL K P 9T X D0 P 9T X D1 P 9T X D2 P 9T X D3 P 9T X EN P 10COL P 10CR S P 10R X CL K P 10R X D0 P 10R X D1 P 10R X D2 P 10R X D3 P 10R X DV P 10R X ER P 10T X CL K P 10T X D0 P 10T X D1 P 10T X D2 P 10T X D3 P 10T X EN P 11COL R I/O Type Pin Signal Name I/O Type Pin 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V AA26 Y 25 Y 26 W26 AA25 AA24 AA23 AB 24 AC26 AC25 AB 23 AB 25 W24 W23 T 26 T 24 T 23 R 26 R 25 T 25 U25 U26 V23 V25 V26 W25 V24 R 23 R 24 M25 M23 L 26 L 25 L 24 M24 M26 N25 P 23 P 24 P 25 P 26 N26 K 26 L 23 G26 H24 H23 F 26 F 25 G25 H25 J23 H26 J25 J26 K 25 J24 E25 E26 C25 D24 A26 B 25 A25 E23 B 26 C26 F 23 D25 D26 F 24 E24 A24 B 24 C21 B 21 A21 B 20 A20 A22 D21 B 22 A23 B 23 D22 C23 C22 D19 P 11CR S R P 11R X CL K R P 11R X D0R P 11R X D1R P 11R X D2R P 11R X D3R P 11R X DVR P 11R X ER R P 11T X CL K R P 11T X D0R P 11T X D1R P 11T X D2R P 11T X D3R P 11T X ENR S T AT 0 S T AT 1 S T AT 2 S T AT 3 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S WCHDOG 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower P ower 3.3V 3.3V Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground 3.3 V I/O I/O I I I I I I I/O O O O O O O O O O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I I A19 B 17 C16 D16 C14 D14 B 16 A17 C18 B 18 A18 B 19 C19 D18 B 03 A03 B 04 A04 AD03 AD07 AD14 AD20 AD24 C03 C05 C09 C12 C13 C15 C20 C24 G03 J03 N24 P 03 R 03 Y 24 AD17 C10 K 03 K 24 U03 U24 Y 03 AD10 C07 C17 F 03 G24 M03 V03 AB 04 D03 D09 D12 D15 D20 G04 AC04 AC14 AC23 D04 D10 D13 K 04 K 23 P 04 R 04 Y 04 AC07 AC10 AC17 AC20 AE03 D06 D07 D17 D23 F 04 G23 J04 M04 N23 U04 U23 V04 Y 23 AA04 I I I I I I I I/O I/O I/O I/O O I I I I I I I I I I I/O I/O I/O I/O O I I I I I I I I I I I/O I/O I/O I/O O I I I I I I I I I I O O O O O I I I I I I I I I I O O O O O I I I I I I I I I I O O O O O I/O O 27 INTRODUCTORY ADDR 0 ADDR 1 ADDR 2 ADDR 3 ADDR 4 ADDR 5 ADDR 6 ADDR 7 ADDR 8 ADDR 9 ADDR 10 ADDR 11 ADDR 12 ADDR 13 ADDR 14 ADDR 15 ADDR 16 AR L CL K AR L DI0 AR L DI1 AR L DI2 AR L DI3 AR L DIR 0 AR L DIR 1 AR L DIV AR L S Y NC CL K 50 CP UDI CP UDO CP UIR Q DAT A0 DAT A1 DAT A2 DAT A3 DAT A4 DAT A5 DAT A6 DAT A7 DAT A8 DAT A9 DAT A10 DAT A11 DAT A12 DAT A13 DAT A14 DAT A15 DAT A16 DAT A17 DAT A18 DAT A19 DAT A20 DAT A21 DAT A22 DAT A23 DAT A24 DAT A25 DAT A26 DAT A27 DAT A28 DAT A29 DAT A30 DAT A31 DAT A32 DAT A33 DAT A34 DAT A35 DAT A36 DAT A37 DAT A38 DAT A39 DAT A40 DAT A41 DAT A42 DAT A43 DAT A44 DAT A45 DAT A46 DAT A47 DAT A48 DAT A49 DAT A50 DAT A51 L ED0 L ED1 L ED2 L ED3 L EDCL K L EDVL D0 I/O Type ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Signal Name Data Sheet: ACD82112 Table-8.3: Pin List By Name Data Sheet: ACD82112 9. TIMING DESCRIPTION MII Receive Timing INTRODUCTORY RXCLK RXDV RXD[3:0] RXER t1 T# t1 t2 t2 Description: RX_DV, RXD, RX_ER setup time RX_DV, RXD, RX_ER hold time MIN 5 5 TYP - MAX - UNIT ns ns ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. MII Transmit Timing TXCLK t1 t2 TXEN TXD[3:0] T# Desciption Min Typ Max Unit t1 TXEN, TXD setup time 10 - - ns t2 10 - - ns TXEN, TXD hold time 28 Data Sheet: ACD82112 Reversed MII Receive Timing RXCLK t2 INTRODUCTORY t1 RXDV RXD[3:0] T# t1 T2 Description: RXDV, RXD setup time RXDV, RXD hold time MIN 10 10 TYP - MAX UNIT ns ns ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Reversed MII Transmit Timing TXCLK TXEN TXD[3:0] t1 T# t1 T2 Description: RXDV, RXD setup time RXDV, RXD hold time t2 MIN 5 5 TYP - MAX UNIT ns ns 29 Data Sheet: ACD82112 Reversed MII Packet Timing (Start of Packet) RXCLK INTRODUCTORY RXDV t1 RXD[3:0] T# Desciption Min Typ Max Unit t1 RXD to RXDV 0 - - ns ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Reversed MII Packet Timing (End of Packet) RXCLK t1 RXDV RXD[3:0] T# Desciption t1 PXD to RXDV delay time Min Typ 0 - Max Unit - ns 30 Data Sheet: ACD82112 PHY Management Read Timing t2 MDC INTRODUCTORY MDIO t1 T# Description t1 MDIO setup time t2 MDC cycle MIN TYP MAX UNIT 0 300 ns 800 ns ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. PHY Management Write Timing MDC t1 t2 t5 t3 t4 MDIO T# D es cript ion MIN T Y P t1 MDC High time 300 - MAX U NIT 500 ns t2 MDC L ow time 300 - 500 ns t3 MDC period - 800 - ns t4 MDIO s et up time 10 - - ns t5 MDIO hold time 10 - - ns 31 Data Sheet: ACD82112 SR AM Read Tim ing t1 ADDRESS t2 t3 __ OE t4 __ CE SRAM Read T im ing HIGH-Z DATA HIGH-Z VALID DATA t7 t8 t9 t5 T# t1 t2 t3 t4 t5 t6 t7 t8 t9 INTRODUCTORY t6 D es c rip tio n R ea d cycle tim e A d dre ss ac ce s s tim e O utp ut h old tim e O E a cc e ss tim e C E a cc e ss tim e O E to L o w-Z o utp ut C E to L o w-Z o u tp u t O E to H igh -Z o utp ut C E to H igh -Z o utp ut M IN 0 0 0 - TYP 20 - M AX 12 12 12 6 6 U N IT ns ns ns ns ns ns ns ns ns ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. S R AM W rite T im ing t1 ADDRESS t2 t4 __ CE t5 ___ WE t3 t6 t7 t8 VALID DATA DATA T# t1 t2 t3 t4 t5 t6 t7 t8 D escription W rite cycle tim e A ddress Setup to W rite E nd tim e A ddress hold for W rite E nd tim e C E to W rite E nd tim e A ddress S etup tim e W E pulse width D ata Setup to W rite E nd D ata Hold for W rite E nd M IN 12 0 12 4 8 8 0 TY P 20 - M AX - U NIT ns ns ns ns ns ns ns ns 32 Data Sheet: ACD82112 CPU Command Timing t4 t1 t2 idle state start stop bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit bit CPUDI stop bit CPUDO bit bit stop 6 7 bit INTRODUCTORY t3 start bit0 bit T# D es cript ion t1 CP U idle time MIN T Y P 0 t2 CP U command bit time t3 Res pons e time t4 Command time MAX U NIT - - us 10 - 1000 us 0 - 20 ms - - 20 ms ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. ARL Result Timing ARLCLK ARLDO DA1 DA2 t1 ARLDI Result2 Result1 t2 t3 T# D es cript ion t1 time between DAs MIN T Y P 0 - MAX U NIT - t2 time for ARL res ult 0 - 200 ns t3 time between res ults 0 - - ns ns 33 Data Sheet: ACD82112 LED Signal Timing LEDCLK LEDVLD0 nLED0 ERR ERR ERR ERR ERR ERR nLED1 FDX FDX FDX FDX FDX FDX COL COL COL COL COL COL nLED2 SPD SPD SPD SPD SPD SPD RCV RCV RCV RCV RCV RCV nLED3 LNK LNK LNK LNK LNK LNK XMT XMT XMT XMT XMT XMT P10 P11 P2 P9 P0 P1 P10 P11 P2 P9 INTRODUCTORY LEDVLD1 P0 P1 10. ELECTRICAL SPECIFICATION Absolute Maximum Ratings DC Supply voltage : VDD DC input current: Iin DC input voltage: Vin DC output voltage: Vout Storage temperature: Tstg ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Operation at absolute maximum ratings is not implied exposure to stresses outside those listed could cause permanent damage to the device. -0.3V ~ +5.0V +/-10 mA -0.3 ~ VDD + 0.3V -0.3 ~ VDD + 0.3V -40 to +125oC Recommended Operation Conditions Supply voltage: VDD Operating temperature: Ta Maximum power consumption 3.3V, +/-0.3V 0oC -70 oC 3.3W 34 Data Sheet: ACD82112 11. PACKAGING Top View 35 30 INTRODUCTORY Advanced Comm. Devices FLLLLL SMAYYWW ACD82112 Side View 2.33 0.56 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. 0.6 Bottom View 31.75 1.27 0.635 0.75 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 35 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Address Resolution Logic INTRODUCTORY Appendix-A1 (The built-in ARL with 2048 MAC Addresses) 36 Data Sheet: ACD82112 The internal Address Resolution Logic (ARL) of ACD's switch controllers automatically builds up an address table and maps up to 2,048 MAC addresses into their associated port. It can work by itself without any CPU intervention in an UN-managed system. * * For a managed system, the management CPU can configure the operation mode of the ARL, learn all the address in the address table, add new address into the table, control security or filtering feature of each address entry etc. The ARL is designed with such a high performance that it will never slow down the frame switching operation. It helps the switch controllers to reach wire speed forwarding rate under any type of traffic load. The address space can be expanded to 11K entries by using the external ARL, the ACD80800. * * * * * * * * * Supports up to 2,048 MAC address lookup Provides UART type of interface for the management CPU Wire speed address lookup time. Wire speed address learning time. Address can be automatically learned from switch without the CPU intervention Address can be manually added by the CPU through the CPU interface Each MAC address can be secured by the CPU from being changed or aged out Each MAC address can be marked by the CPU from receiving any frame Each newly learned MAC address is notified to the CPU Each aged out MAC address is notified to the CPU Automatic address aging control, with configurable aging period Figure-1. ARL Block Diagram Address Aging Engine Control Registers Command Registers ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Address Learning Engine Data Registers CPU Interface Address Registers Switch Interface Data Sheet: ACD82112 2. FEATURES INTRODUCTORY 1. SUMMARY Address Lookup Engine CPU Interface Engine Address Table (2048 Entries) 37 Address Lookup The ARL provides Address Resolution service for ACD's switch controllers. Figure 2 is a block diagram of the ARL. Each destination address is passed to the Address Lookup Engine of the ARL. The Address Lookup Engine checks if the destination address matches with any existing address in the address table. If it does, the ARL returns the associated Port ID to ACD's switch controller through the output data bus. Otherwise, a no match result is passed to ACD's switch controller through the output data bus. CPU Interface The CPU can access the registers of the ARL by sending commands to the UART data input line. Each command is consisted by action (read or write), register type, register index, and data. Each result of command execution is returned to the CPU through the UART data output line. Address Learning CPU Interface Registers Each source address caught from the data bus, together with the ID of the ingress port, is passed to the Address Learning Engine of the ARL. The Address Learning Engine will first determine whether the frame is a valid frame. For a valid frame, it will first try to find the source address from the current address table. If that address doesn't exist, or if it does exist but the port ID associated with the MAC address is not the ingress port, the address will be learned into the address table. After an address is learned by the address learning engine, the CPU will be notified to read this newly learned address so that it can add it into the CPU's address table. The ARL provides a bunch of registers for the control CPU. Through the registers, the CPU can read all address entries of the address table, delete particular addresses from the table, add particular addresses into the table, secure an address from being changed, set filtering on some addresses, change the hashing algorithm etc. Through a proper interrupt request signal, the CPU can be notified whenever it needs to retrieve data for a newly-learned address or an aged-out address so that the CPU can build an exact same address table learned by the ARL. CPU Interface Engine Address Aging After each source address is learned into the address table, it has to be refreshed at least once within each address aging period. Refresh means it is caught again from the switch interface. If it has not occurred for a pre-set aging period, the address aging engine will remove the address from the address table. After an address is removed by the address aging engine, the CPU will be notified through interrupt request that it needs to read this aged out address so that it can remove this address from the CPU's address table. The command sent by the control CPU is executed by the CPU Interface Engine. For example, the CPU may send a command to learn the first newly-learned address. The CPU Interface Engine is responsible to find the newly-learned address from the address table, and passes it to CPU. The CPU may request to learn next newly-learned address. Then, it is again the responsibility of the CPU Interface Engine to search for next newly-learned address from the address table. Address Table The address table can hold up to 2,048 MAC addresses, together with the associated port ID, security flag, filtering flag, new flag, aging information etc. The address table resides in the embedded SRAM inside the ARL. 38 INTRODUCTORY All Ethernet frames received by ACD's switch controller have to be stored into memory buffer. As the frame data are written into memory, the status of the data shown on the data bus are displayed by ACD's switch controller through a state bus. The ARL's Switch Controller Interface contains the signals of the data bus and the state bus. By snooping the data bus and the state bus of ACD's switch controller, the ARL can detect the occurrence of any destination MAC address and source MAC address embedded inside each frame. ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Traffic Snooping Data Sheet: ACD82112 3. FUNCTIONAL DESCRIPTION The CPU can communicate with the ARL through the UART interface of the switch IC. The management CPU can send command to the ARL by writing into associated registers, and retrieve result from ARL by reading corresponding registers. The registers are described in the section of "Register Description." The CPU interface signals are described by table-1: Header where: * Table-1: CPU Interface I/O I O Description UART input data line. UART output data line. * * UARTDI is used by the control CPU to send command into the ARL. The baud rate will be automatically detected by the ARL. The result will be returned through the UARTDO line with the detected baud rate. The format of the command packet is shown as follows: Header where: * * * * Address Data * Data Checksum Header is further defined as: b1:b0 - read or write, 01 for read, 11 for write b4:b2 - device number, 000 to 111 (0 to 7) b7:b5 - device type, 010 for ARL Address - 8-bit value for address of the selected register Data - 32-bit value, only the LSB is used for read operation, all 0 for write operation Checksum - 8-bit value of XOR of all bytes The ARL will always check the CMD header to see if both the device type and the device number matches with its setting. If not, it ignores the command and will not generate any response to this command. Checksum Header is further defined as: b1:b0 - read or write, 01 for read, 11 for write b4:b2 - device number, 000 to 111 (0 to 7, same as the host switch controller) b7:b5 - device type, 010 for ARL Address - 8-bit value used to select the register to access Data - 32-bit value, only the LSB is used for write operation, all 0 for read operation Checksum - 8-bit value of XOR of all bytes ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Name UARTDI UARTDO Address Data Sheet: ACD82112 CPU Interface INTRODUCTORY UARTDO is used to return the result of command execution to the CPU. The format of the result packet is shown as follows: 4. INTERFACE DESCRIPTION 39 The registers accessible to the CPU are described by table-2: Table-2: Register Description Reg. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name DataReg0 DataReg1 DataReg2 DataReg3 DataReg4 DataReg5 DataReg6 DataReg7 AddrReg0 AddrReg1 CmdReg RsltReg CfgReg IntSrcReg IntMskReg 15 nLearnReg0 16 nLearnReg1 17 nLearnReg2 18 AgeTimeReg0 19 AgeTimeReg1 20 PosCfg Description Byte 0 of data Byte 1 of data Byte 2 of data Byte 3 of data Byte 4 of data Byte 5 of data Byte 6 of data Byte 7 of data LSB of address value MSB of address value Command register Result register Configuration register Interrupt source register Interrupt mask register Address learning disable register for port 0 - 7 Address learning disable register for port 8 - 15 Address learning disable register for port 16 - 23 LSB of aging period register The CmdReg is used to pass the type of command to the ACD80800. The command types are listed in table3. The details of each command is described in the chapter of "Command Description." Data Sheet: ACD82112 The AddrRegX are registers used to specify the address associated with the command. Table-3: Command List Command 0x10 0x11 0x20 0x21 0x30 0x31 0x40 0x41 0x50 0x51 0x60 0x61 0x80 0x81 Description Add the specified MAC address into the address table Set a lock for the specified MAC address Set a filtering flag for the specified MAC address Delete the specified MAC address from the address table Assign a port ID to the specified MAC address Read the first entry of the address table Read next entry of address book Read first valid entry Read next valid entry Read first new page Read next new page Read first aged page Read next aged page Read first locked page Read next locked page Read first filtered page Read next filtered page Read first page with specified PID Read next page with specified PID 0xFF System reset 0x09 0x0A 0x0B 0x0C 0x0D The RstReg is used to indicate the status of command execution. The result code is listed as follows: * * * 01 - command is being executed and is not done yet 10 - command is done with no error 1x - command is done, with error indicated by x, where x is a 4-bit error code: 0001 for cannot find the entry as specified MSB of aging period register Power On Strobe configuration register 0 40 INTRODUCTORY ACD80800 provides a bunch of registers for the CPU to access the address table inside it. Command is sent to ACD80800 by writing into the associated registers. Before the CPU can pass a command to ACD80800, it must check the result register (register 11) to see if the command has been done. When the Result register indicates the command has been done, the CPU may need to retrieve the result of previous command first. After that, the CPU has to write the associated parameter of the command into the Data registers. Then, the CPU can write the command type into the command register. When a new command is written into the command register, ACD80800 will change the status of the Result register to 0. The Result register will indicate the completion of the command at the end of the execution. Before the completion of the execution, any command written into the command register is ignored by ACD80800. The DataRegX are registers used to pass the parameter of the command to the ACD80800, and the result of the command to the CPU. ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. 5. REGISTER DESCRIPTION The IntSrcReg is used to indicate what can cause interrupt request to CPU. The source of interrupt is listed as: * * * * * * * * bit 0 - aged address exists bit 1 - new address exists bit 2 - reserved bit 3 - reserved bit 4 - bucket overflowed bit 5 - command is done bit 6 - system initialization is completed bit 7 - self test failure The IntMskReg is used to enable an interrupt source to generate an interrupt request. The bit definition is the same as IntSrcReg. A 1 in a bit enables the corresponding interrupt source to generate an interrupt request once it is set. The AgeTimeReg[1:0] are used to specify the period of address aging control. The aging period can be from 0 to 65535 units, with each unit counted as 2.684 second. Data Sheet: ACD82112 bit 0 - disable address aging bit 1 - disable address lookup bit 2 - disable DA cache bit 3 - disable SA cache bit 7:4 - hashing algorithm selection, default is 0000 The PosCfgReg is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin. The bits of PosCfgReg0 is listed as follows: * * bit 1* - NOCPU*, "0" = presence of control CPU, "1" = no control CPU; bit 0 - CPUGO, "0" = wait for System Start command from CPU before starting self initialization, "1" = CPU ready. Only effective when bit-1 (NOCPU) is set to 0; Note: When NOCPU is set as 0, ACD80800 will not start the initialization process until a System Start command is sent to the command register. INTRODUCTORY * * * * * The nLearnReg[2:0] are used to disable address learning activity from a particular port. If the bit corresponding to a port is set, ACD80800 will not try to learn new addresses from that port. ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. The CfgReg is used to configure the way the ACD80800 works. The bit definition of CfgReg is described as: 41 Command 0DH Command 09H Description: Assign the associated port number to the specified MAC address. Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the associated port number into DataReg6. Result: the MAC address will be stored into the address table if there is space available. The result is indicated by the Result register. Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the port number into DataReg6. Result: the port ID field of the entry containing the specified MAC address will be changed accordingly. The result is indicated by the Result register. Command 10H Command 0AH Description: Read the first entry of the address table. Description: Set the Lock bit for the specified MAC address. Parameter: None Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Result: the state machine will seek for an entry with matched MAC address, and set the Lock bit of the entry. The result is indicated by the Result register. Result: The result is indicated by the Result register. If the command is completed with no error, the content of the first entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag* bits are stored in DataReg7.The Read Pointer will be set to point to second entry of the address book. INTRODUCTORY Description: Add the specified MAC address into the address table. Data Sheet: ACD82112 6. COMMAND DESCRIPTION Command 0BH Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. b7 b6 b5 Rsvd Rsvd Filter where: Result: the state machine will seek for an entry with matched MAC address, and set the Filter bit of the entry. The result is indicated by the Result register. * Command 0CH * Description: Delete the specified MAC address from the address table. * Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. * * * * b4 Lock b3 New b2 Old b1 Age b0 Valid Filter - 1 indicates the frame heading to this address should be dropped. Lock - 1 indicates the entry should never be changed or aged out. New - 1 indicates the entry is a newly learned address. Old - 1 indicates the address has been aged out. Age - 1 indicates the address has not been visited for current age cycle. Valid - 1 indicates the entry is a valid one. Rsvd - Reserved bits. Result: the MAC address will be removed from the address table. The result is indicated by the Result register. 42 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Note - the Flag bits are defined as: Description: Set the Filter flag for the specified MAC address. Result: The result is indicated by the Result register. If the command is completed with no error, the content of the address book entry pointed by Read Pointer will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer will be increased by one. Command 20H Description: Read first valid entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first valid entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 21H Description: Read next valid entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next valid entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 30H Description: Read first new page. Parameter: None Command 31H Data Sheet: ACD82112 Parameter: None Description: Read next new entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next new entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 40H Description: Read first aged entry. INTRODUCTORY Description: Read next entry of address book. the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first aged entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 41H Description: Read next aged entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next aged entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Result: The result is indicated by the Result register. If the command is completed with no error, the content of first new entry of the address book will be stored into 43 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Command 11H Result: The result is indicated by the Result register. If the command is completed with no error, the content of first locked entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 51H Description: Read next locked entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next locked entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 60H Description: Read first filtered page. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first filtered entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 61H Command 80H Data Sheet: ACD82112 Parameter: None Description: Read first entry with specified port number. Parameter: Store port number into DataReg6. Result: The result is indicated by the Result register. If the command is completed with no error, the content of first entry of the address book with the said port number will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 81H Description: Read next valid entry. INTRODUCTORY Description: Read first locked entry. book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Parameter: Store port number into DataReg6. Result: The result is indicated by the Result register. If the command is completed with no error, the content of next entry from the Read Pointer of the address book with the said port number will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command FFH Description: System reset. Parameter: None Result: This command will reset the ARL system. All entries of the address book will be cleared. Description: Read next valid entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next filtered entry from the Read Pointer of the address 44 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only. Command 50H