ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8521 is a low skew, 1-to-9 Differential-to-HSTL Fanout Buffer. The ICS8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. * 9 HSTL outputs Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS8521 ideal for today's most advanced applications, such as IA64 and static RAMs. * Output skew: 50ps (maximum) * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 500MHz * Part-to-part skew: 250ps (maximum) * Propagation delay: 1.8ns (maximum) * VOH = 1.4V (maximum) * 3.3V core, 1.8V output operating supply voltages * 0C to 70C ambient operating temperature * Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VDDO nQ2 Q2 nQ1 Q1 nQ0 Q0 VDDO D CLK_EN Q CLK nCLK PCLK nPCLK CLK_SEL LE 0 1 32 31 30 29 28 27 26 25 Q0 nQ0 VDD CLK nCLK CLK_SEL PCLK nPCLK GND CLK_EN Q1 nQ1 Q2 nQ2 Q3 nQ3 1 2 3 4 5 6 7 8 ICS8521 24 23 22 21 20 19 18 17 VDDO Q3 nQ3 Q4 nQ4 Q5 nQ5 VDDO 9 1 0 1 1 1 2 1 3 1 4 1 5 16 VDDO Q6 nQ6 Q7 nQ7 Q8 nQ8 VDDO Q4 nQ4 Q5 nQ5 32-Lead LQFP 7mm x 7mm x 1.4mm Package Body Y Package Top View Q6 nQ6 Q7 nQ7 Q8 nQ8 8521BY www.idt.com 1 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDD Type Description Power Core supply pin. 2 CLK Input Pulldown 3 nCLK Input Pullup 4 CLK_SEL Input Pulldown 5 PCLK Input Pulldown Pullup 6 nPCLK Input 7 GND Power 8 CLK_EN Input Pullup Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS /LVTTL interface levels. 9, 16, 17, 24, 25, 32 10, 11 VDDO Power nQ8, Q8 Output Differential output pair. HSTL interface level. 12, 13 nQ7, Q7 Output Differential output pair. HSTL interface level. 14, 15 nQ6, Q6 Output Differential output pair. HSTL interface level. 18, 19 nQ5, Q5 Output Differential output pair. HSTL interface level. 20, 21 nQ4, Q4 Output Differential output pair. HSTL interface level. 22, 23 nQ3 Q3 Output Differential output pair. HSTL interface level. 26, 27 nQ2, Q2 Output Differential output pair. HSTL interface level. 28, 29 nQ1, Q1 Output Differential output pair. HSTL interface level. 30, 31 nQ0, Q0 Output Differential output pair. HSTL interface level. Output supply pins. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 K RPULLDOWN Input Pulldown Resistor 51 K 8521BY www.idt.com 2 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN CLK_SEL Outputs Selected Sourced Q0:Q8 nQ0:nQ8 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0:nQ8 Q0:Q8 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK or PCLK nCLK or nPCLK Q0:Q8 nQ0:nQ8 0 1 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information "Wiring the Differential Input to Accept Single Ended Levels". 8521BY www.idt.com 3 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter VDD Core Supply Voltage Test Conditions VDDO Output Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.6 1.8 2.0 V 60 80 mA Maximum Units TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical VIH CLK_EN, CLK_SEL 2 VDD + 0.3 V VIL CLK_EN, CLK_SEL -0.3 0.8 V IIH Input High Current IIL Input Low Current CLK_EN VIN = VDD = 3.465V 5 A CLK_SEL VIN = VDD = 3.465V 150 A CLK_EN VIN = 0V, VDD = 3.465V -150 A CLK_SEL VIN = 0V, VDD = 3.465V -5 A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units CLK VIN = VDD = 3.465V Test Conditions Minimum Typical 150 A nCLK VIN = VDD = 3.465V 5 A CLK VIN = 0V, VDD = 3.465V -5 A nCLK VIN = 0V, VDD = 3.465V -150 A VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8521BY www.idt.com 4 1.3 V VDD - 0.85 V REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol IIH IIL Parameter Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 150 A 5 A VDD = VIN = 3.465V PCLK nPCLK VDD = VIN = 3.465V PCLK VDD = 3.465V, VIN = 0V -5 A nPCLK VDD = 3.465V, VIN = 0V -150 A Peak-to-Peak Input Voltage 0.3 Common Mode Input Voltage; VCMR 1.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. 1 V VDD V VPP TABLE 4E. HSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX Test Conditions Output Crossover Voltage Minimum Maximum Units 1.0 1.4 V 0 0.4 V 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V 0.6 1.1 V Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50 to ground. VSWING Typical TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum 250MHz 1 Typical Maximum Units 500 MHz 1. 8 ns 50 ps fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 250 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 52 % odc Output Duty Cycle 48 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. Measured from VDD/2 to the output differential crossing point for single ended input levels. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8521BY www.idt.com 5 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V 5% 1.8V 0.2V VDD V DD Qx SCOPE VDDO nCLK, nPCLK V HSTL V Cross Points PP CMR CLK, PCLK nQx GND GND = 0V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy t sk(pp) t sk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK, nPCLK 80% CLK, PCLK 80% VOD Clock Outputs nQ0:nQ8 20% 20% tR tF Q0:Q8 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0:nQ8 Q0:Q8 Pulse Width t odc = PERIOD t PW t PERIOD odc & tPERIOD 8521BY www.idt.com 6 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8521BY www.idt.com 7 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. CLK/NCLK INPUT DRIVEN BY HSTL DRIVER FIGURE 3B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 FIGURE 3C. HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. 8521BY CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE www.idt.com 8 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here 3.3V 3.3V R1 50 CML 3.3V 3.3V 3.3V Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK nPCLK PCLK R1 100 Zo = 50 Ohm nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 4A. PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 4B. PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 FIGURE 4C. nPCLK HiPerClockS Input R5 100 - 200 R2 84 PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 4D. R6 100 - 200 R1 125 PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm R3 1K R4 1K PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 FIGURE 4E. 8521BY HiPerClockS PCLK/nPCLK R2 125 C2 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK R1 1K R2 120 PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER FIGURE 4F. www.idt.com 9 HiPerClockS PCL K/n PC LK R2 1K PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8521. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8521 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 80mA = 277.2mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 32.8mW = 295.2mW Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 295.2mW = 572.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.572W * 42.1C/W = 94.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance JA for 32-pin LQFP, Forced Convection JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8C/W 47.9C/W 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8521BY www.idt.com 10 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. VDDO Q1 VOUT RL 50 FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V L /R ) * (V OL_MAX L -V DDO_MAX ) OH_MAX -V DDO_MAX ) OL_MAX Pd_H = (1.0V/50) * (2V - 1.0V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 8521BY www.idt.com 11 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8C/W 47.9C/W 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8521 is: 944 8521BY www.idt.com 12 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC 0.75 L 0.45 0.60 0 -- 7 ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8521BY www.idt.com 13 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number 8521BY 8521BYT 8521BYLN Marking Package Shipping Packaging Temperature ICS8521BY ICS8521BY ICS8521BYLN tray 1000 tray 0C to 70C 0C to 70C 0C to 70C 8521BYLNT ICS8521BYLN 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead-Free/Annealed" LQFP 32 Lead "Lead-Free/Annealed" LQF on Tape and Reel 1000 0C to 70C While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8521BY www.idt.com 14 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table B D Updated Figure 1 - CLK_EN Timing Diagram. 5 T2 2 4 8 9 4 9 14 LVHSTL table - changed VOH maximum from 1.2V to 1.4V. Changed LVHSTL to HSTL throughout data sheet to conform with JEDEC terminology. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. T4B T7 8521BY Updated Figure 1 - CLK_EN Timing Diagram. 3 D E Description of Change 3 T4E B C Page T7 14 16 LVCMOS table - changed VIH from 3.765V max. to VDD + 0.3V max. Added Differential Input Interface section. Added LVPECL Input Interface section. Absolute Maximum Ratings - updated Output rating. Updated LVPECL Clock Input Interface section. Ordering Information - added "Lead-Free/Annealed" part number. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. www.idt.com 15 Date 10/16/01 11/1/01 01/02/03 7/16/03 7/7/04 7/25/10 REV. E JULY 25, 2010 ICS8521 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER We've Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 netcom@idt.com (c) 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8521BY www.idt.com 16 REV. E JULY 25, 2010