0.1 GHz to 6 GHz Silicon SP5T Switch ADRF5250 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VSS RFC ADRF5250 NEGATIVE VOLTAGE GENERATOR DIGITAL CONTROL V2 V1 RF5 50 BIAS VDD RF1 RF4 50 50 50 50 RF2 RF3 APPLICATIONS V3 15506-001 Nonreflective 50 design Low insertion loss: 1.5 dB at 4 GHz High isolation: 50 dB at 4 GHz High input linearity 0.1 dB compression (P0.1dB): 34 dBm typical Third-order intercept (IP3): 57 dBm typical High power handling at 85C 33 dBm through path 27 dBm terminated path ESD rating 3.5 kV HBM, Class 2 Single-supply or dual-supply operation Optional internal negative voltage generator (NVG) 1.8 V logic-compatible control 4 mm x 4 mm, 24-lead LFCSP Figure 1. Cellular/4G infrastructure Wireless infrastructure Mobile radios Test equipment GENERAL DESCRIPTION The ADRF5250 is a general-purpose, single-pole, five-throw (SP5T), nonreflective switch manufactured using a silicon process. The ADRF5250 is available in a 4 mm x 4 mm, 24-lead lead frame chip scale package (LFCSP) and provides high isolation and low insertion loss from 100 MHz to 6 GHz. Rev. 0 The ADRF5250 incorporates a negative voltage generator to operate with a single positive supply voltage from 3.3 V to 5 V applied to the VDD pin when the VSS pin is connected to ground. The negative voltage generator can be disabled when an external negative supply voltage of -3.3 V is applied to the VSS pin. The ADRF5250 provides a 1.8 V logic-compatible, 3-pin control interface. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5250 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................7 Applications ....................................................................................... 1 Typical Performance Characterics ..................................................8 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, And Isolation ...............................8 General Description ......................................................................... 1 Input Power Compression and Third-Order Intercept (IP3) ....9 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 11 Specifications..................................................................................... 3 Applications Information .............................................................. 12 Absolute Maximum Ratings ............................................................ 5 Evaluation Board ........................................................................ 12 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 14 Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 14 REVISION HISTORY 6/2017--Revision 0: Initial Version Rev. 0 | Page 2 of 15 Data Sheet ADRF5250 SPECIFICATIONS VDD = 5 V, VSS = 0 V, V1 = V2 = V3 = 0 V/VDD, TCASE = 25C, 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RFx (On) Symbol f ISOLATION Between RFC and RFx (Off ) RETURN LOSS RFC and RFx (On) RFx (Off ) SWITCHING Rise Time Fall Time On and Off Time Settling Time (RFx to RFx) 0.1 dB 0.05 dB INPUT LINEARITY 0.1 dB Compression Third-Order Intercept SUPPLY CURRENT Positive Negative DIGITAL CONTROL INPUTS Voltage Low High Current Low and High tRISE tFALL tON, tOFF Test Conditions/Comments Min 0.1 ISS VINL VINH IINL, IINH Max 6 Unit GHz 0.1 GHz to 2 GHz 2 GHz to 4 GHz 4 GHz to 6 GHz 1.3 1.5 1.8 dB dB dB 0.1 GHz to 2 GHz 2 GHz to 4 GHz 4 GHz to 6 GHz 55 50 46 dB dB dB 0.1 GHz to 2 GHz 2 GHz to 4 GHz 4 GHz to 6 GHz 0.1 GHz to 2 GHz 2 GHz to 4 GHz 4 GHz to 6 GHz 15 13 13 17 15 8 dB dB dB dB dB dB 10% to 90% of radio frequency (RF) output 10% to 90% of RF output 50% of digital control voltage (V1, V2, V3) to 90% of RF output 40 80 150 ns ns ns 50% of V1, V2, V3 to 0.1 dB of final RF output 50% of V1, V2, V3 to 0.05 dB of final RF output 400 500 ns ns 34 57 dB dBm 360 280 -60 A A A P0.1dB IP3 IDD Typ VDD, VSS pins NVG enabled (VSS = 0 V) NVG disabled (VSS = -3.3 V) NVG disabled (VSS = -3.3 V) V1, V2, V3 pins VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V VDD = 3.3 V to 5 V Rev. 0 | Page 3 of 15 0 0 1.3 1.6 0.8 1.2 3.3 5 <1 V V V V A ADRF5250 Parameter RECOMMENDED OPERATING CONDITIONS Supply Voltage Positive Negative Digital Control Voltage Maximum RF Input Power 1 TCASE = 105C Data Sheet Symbol VDD VSS V1, V2, V3 PIN 1 Min Max Unit 3.0 -3.45 0 5.25 -3.15 VDD V V V -40 30 24 24 33 27 27 +105 dBm dBm dBm dBm dBm dBm C Through path (VDD = 3.3 V to 5 V) Terminated path Hot switching Through path (VDD = 3.3 V to 5 V) Terminated path Hot switching TCASE = 85C Case Temperature Test Conditions/Comments TCASE Typ Exposure to levels between the recommended operating conditions and the absolute maximum rating conditions for extended period may affect device reliability. Rev. 0 | Page 4 of 15 Data Sheet ADRF5250 ABSOLUTE MAXIMUM RATINGS For recommended operating conditions, see Table 1. Table 2. Parameter Positive Supply Voltage (VDD) Negative Supply Voltage (VSS) Digital Control Input Voltage (V1, V2, V3) RF Input Power Through Path Terminated Path All Off State, RFC as Input Hot Switching RFC as Input RFx to RFx All Off to RFx RFx as Input RFx to RFx All Off to RFx Temperature Junction, TJ Storage Reflow (MSL3 Rating) Junction to Case Thermal Resistance, JC Through Path Terminated Path ESD Sensitivity Human Body Model (HBM) Field Induced Device Model (FICDM) Rating -0.3 V to +5.5 V -3.6 V to +0.3 V -0.3 V to VDD + 0.5 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. 35 dBm 34 dBm 24 dBm ESD CAUTION 32 dBm 24 dBm 34 dBm 34 dBm 135C -65C to +150C 260C 90C/W 100C/W 3.5 kV (Class 2) 1.25 kV (Class IV) Rev. 0 | Page 5 of 15 ADRF5250 Data Sheet 19 V3 21 GND 20 VSS 22 RFC 24 GND 23 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 18 V2 GND 1 RF5 2 17 V1 GND 3 ADRF5250 16 VDD GND 4 TOP VIEW (Not to Scale) 15 GND RF4 5 14 RF1 GND 6 NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PCB. 15506-002 GND 12 RF2 11 GND 9 GND 10 RF3 8 GND 7 13 GND Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 21, 23, 24 2 Mnemonic GND Description Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB). RF5 5 RF4 8 RF3 11 RF2 14 RF1 16 17 VDD V1 18 19 V2 V3 20 VSS 22 RFC RF Throw Port 5. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential is within 0 V dc. RF Throw Port 4. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential is within 0 V dc. RF Throw Port 3. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential is within 0 V dc. RF Throw Port 2. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential is within 0 V dc. RF Throw Port 1. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential is within 0 V dc. Positive Supply Voltage. Digital Input Voltage Applied to the Least Significant Bit (LSB) of Digital Interface for Controlling RF Path State. See Table 5. Digital Input Voltage Applied to the Second Bit of Digital Interface for Controlling RF Path State. See Table 5. Digital Input Voltage Applied to the Most Significant Bit (MSB) of Digital Interface for Controlling RF Path State. See Table 5. Optional Negative Supply Voltage. This pin can be connected to ground to operate with the internal negative voltage generator. The internal negative voltage generator is disabled when this pin is connected to an external 3.3 V supply. RF Common Port. This pin is dc-coupled and no dc blocking capacitor is necessary when the RF line potential is within 0 V dc. Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB. EPAD Rev. 0 | Page 6 of 15 Data Sheet ADRF5250 INTERFACE SCHEMATICS V1, V2, V3 VDD 15506-004 RFC, RF1 TO RF5 15506-003 VDD Figure 4. Digital Pin Interface Schematic Figure 3. RF Pin Interface Schematic Rev. 0 | Page 7 of 15 ADRF5250 Data Sheet TYPICAL PERFORMANCE CHARACTERICS INSERTION LOSS, RETURN LOSS, AND ISOLATION 0 0 RF1 ON RF2 ON RF3 ON RF4 ON RF5 ON -1.0 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -1.5 -2.0 -2.5 -3.0 1 2 3 4 5 6 7 8 FREQUENCY (GHz) -4.0 0 3 4 5 6 7 8 Figure 8. Insertion Loss on RF Paths over Temperature 0 0 RFC RF1 ON RF2 ON RF3 ON RF4 ON RF5 ON RF1 TO RF2 TO RF3 TO RF4 TO RF5 TO -10 WORST CASE ISOLATION (dB) -10 2 FREQUENCY (GHz) Figure 5. Insertion Loss on RF Paths at Room Temperature -5 1 15506-107 0 15506-005 -3.5 -4.0 RETURN LOSS (dB) TA = +105C TA = +85C TA = +25C TA = -40C -0.5 INSERTION LOSS (dB) INSERTION LOSS (dB) -0.5 -15 -20 -25 -30 -20 RFC (RF2 ON) RFC (RF1 ON) RFC (RF2 ON) RFC (RF5 ON) RFC (RF4 ON) -30 -40 -50 -60 -70 -80 1 2 3 4 5 6 7 8 FREQUENCY (GHz) Figure 6. Return Loss on Selected RFx Ports and RFC RF1 (RF2 ON) RF2 (RF1 ON) RF3 (RF2 ON) RF4 (RF5 ON) RF5 (RF4 ON) -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 FREQUENCY (GHz) 7 8 15506-008 RETURNLOSS (dB) -10 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 9. Worst Case Isolation on RF Paths 0 -5 -100 Figure 7. Return Loss on Terminated RFx Ports Rev. 0 | Page 8 of 15 7 8 15506-007 0 15506-006 -90 -35 Data Sheet ADRF5250 INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT (IP3) 40 RFC TO RFC TO RFC TO RFC TO RFC TO 38 INPUT P0.1 dB (dBm) 36 34 32 30 28 26 30 28 26 24 22 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 20 0.5 1.0 40 38 RF1 RF2 RF3 RF4 RF5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 TA = +105C TA = +85C TA = +25C TA = -40C 38 36 INPUT P0.1 dB (dBm) 36 2.0 FREQUENCY (GHz) 40 RFC TO RFC TO RFC TO RFC TO RFC TO 1.5 Figure 13. Input 0.1 dB Power Compression vs. Frequency over Temperature, VDD = 3.3 V, VSS = 0 V Figure 10. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency, VDD = 3.3 V, VSS = 0 V 34 32 30 28 26 34 32 30 28 26 24 24 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FREQUENCY (GHz) 20 0.5 15506-009 20 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FREQUENCY (GHz) 15506-011 22 22 Figure 14. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over Temperature, VDD = 5 V, VSS = 0 V Figure 11. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency, VDD = 5 V, VSS = 0 V 65 65 60 60 55 INPUT IP3 (dBm) 55 50 45 50 45 40 40 30 0.5 1.0 1.5 RF1 RF2 RF3 RF4 RF5 2.0 TA = +105C TA = +85C TA = +25C TA = -40C 35 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (GHz) 6.0 30 0.5 15506-013 RFC TO RFC TO RFC TO RFC TO RFC TO 35 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (GHz) Figure 15. Input IP3 vs. Frequency over Temperature, VDD = 5 V, VSS = 0 V Figure 12. Input IP3 vs. Frequency, VDD = 5 V, VSS = 0 V Rev. 0 | Page 9 of 15 6.0 15506-014 INPUT P0.1dB (dBm) 32 22 FREQUENCY (GHz) INPUT IP3 (dBm) 34 24 20 0.5 TA = +105C TA = +85C TA = +25C TA = -40C 38 15506-010 INPUT P0.1dB (dBm) 36 RF1 RF2 RF3 RF4 RF5 15506-012 40 Data Sheet 65 60 60 55 55 INPUT IP3 (dBm) 65 50 45 50 45 40 RFC TO RFC TO RFC TO RFC TO RFC TO 35 30 0.5 1.0 1.5 RF1 RF2 RF3 RF4 RF5 2.0 TA = +105C TA = +85C TA = +25C TA = -40C 35 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (GHz) 6.0 30 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (GHz) Figure 16. Input IP3 vs. Frequency, VDD = 3.3 V, VSS = 0 V Figure 17. Input IP3 vs. Frequency over Temperature, VDD = 3.3 V, VSS = 0 V Rev. 0 | Page 10 of 15 6.0 15506-016 40 15506-015 INPUT IP3 (dBm) ADRF5250 Data Sheet ADRF5250 THEORY OF OPERATION The ADRF5250 requires a positive supply voltage applied to the VDD pin and 0 V or -3.3 V supply voltage applied to the VSS pin. Bypass capacitors are recommended on the supply and digital control lines to minimize RF coupling. An incorporated negative supply generator is enabled or disabled depending on the applied VSS supply voltage. Table 4 describes the operation mode of that negative supply generator. Table 4. Negative Voltage Generator Operation Mode VSS 0V -3.3 V Test Conditions/Comments The incorporated negative voltage generator is enabled The incorporated negative voltage generator is disabled The ADRF5250 is internally matched to 50 at the RF common port (RFC) and the RF throw ports (RF1 to RF5); therefore, no external matching components are required. All of the RF ports are dc-coupled to 0 V, and no dc blocking is required at the RF ports when the RF line potential is equal to 0 V. The design is bidirectional; the RF input signal can be applied to the RFC port while the RF throw port (RF1 to RF5) is output, or vice versa. The ADRF5250 has a 3-bit, 1.8 V logic-compatible control interface that is controlled through the V1, V2, and V3 digital control voltage pins. A small bypassing capacitor is recommended on these digital signal lines to improve the RF signal isolation. The V1 and V3 test points correspond to the LSB and MSB of the digital control interface of the ADRF5250. The modes of the RF paths are determined as shown in Table 5. When an RF path is on, the RF signal is conducted equally well in both directions between its throw port (RFx) and common port (RFC). Otherwise, each RFx path is terminated to an internal 50 resistor that provides high loss between the insertion loss path and its throw ports. Table 5. Control Voltage Truth Table V3 Low Low Low Low High High High High V2 Low Low High High Low Low High High V1 Low High Low High Low High Low High Mode All Off RF1 on RF2 on RF3 on RF4 on RF5 on All off All off The ideal power-up sequence is as follows: 1. 2. 3. 4. Rev. 0 | Page 11 of 15 Power up GND. Power up VDD and VSS. The relative order is not important. Power up the digital control inputs. The relative order of the logic control inputs is not important. However, powering the digital control inputs before the VDD supply can inadvertently forward bias and damage the internal ESD protection structures. Apply an RF input signal. ADRF5250 Data Sheet APPLICATIONS INFORMATION EVALUATION BOARD Figure 20 shows the actual ADRF5250 evaluation board with component placement. Two power supply ports are connected to the VDD and VSS test points, TP3 and TP5, and the ground reference is connected to the GND test point, TP6. On the digital control and VDD supply traces, bypass capacitors are used. 15506-117 2200mil Figure 18 and Figure 19 show the top and cross sectional views of the evaluation board, which uses 4-layer construction with a copper thickness of 0.5 oz (0.7 mil) and dielectric materials between each copper layer. coplanar waveguide (CPWG) model with a width of 8 mil and ground spacing of 10 mil for a characteristic impedance of 50 . For optimal RF and thermal grounding, as many plated through vias as possible are arranged around the transmission lines and under the exposed pad of the package. 1400mil 15506-018 Figure 18. Evaluation Board Layout Top View 0.5oz Cu (0.7mil) Figure 20. ADRF5250-EVALZ Evaluation Board 10mil ROGERS 4350B TOTAL THICKNESS ~30mil W = 8mil 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) G = 10mil 0.5oz Cu (0.7mil) 8mil ROGERS 4450F 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) 15506-118 10mil ROGERS 4350B Figure 19. Evaluation Board Cross Sectional View All RF traces are routed on Layer 2; the V1, V3, and VSS dc traces are routed on Layer 3; the V2 and VDD dc traces are routed on the top layer; and the other remaining layers are grounded planes that provide a solid ground for RF transmission lines. The top and bottom dielectric material are Rogers 4350B, offering low loss performance. The middle dielectric material is Rogers 4450F and is used to achieve an overall board thickness of 30 mil. The RF transmission lines were designed using a Three control ports are connected to the V1, V2, and V3 test points, TP1, TP2, and TP4, respectively. On each control trace, a resistor position is available to improve the isolation between the RF and control signals. The RF ports are connected to the RFC, RF1, RF2, RF3, RF4, and RF5 connectors (J6, J8, J7, J5, J2, and J1), which are end launch jack SMA RF connectors. A through transmission line that connects unpopulated RF connectors (J3 and J4) is also available to measure the loss of the PCB. Figure 22 and Table 6 show the evaluation board schematic and bill of materials, respectively. The evaluation board shown in Figure 20 is available for order from the Analog Devices, Inc., website at www.analog.com. Rev. 0 | Page 12 of 15 Data Sheet ADRF5250 Table 6. Bill of Materials for the ADRF5250-EVALZ Evaluation Board 60 SECONDS TO 150 SECONDS RAMP UP 3C/SEC MAX Item J1, J2, J5 to J8 TP1 to TP6 C2 to C5 C6 to C9 C10 08-042239 260C -5C/+0C TEMPERATURE (C) 217C 150C TO 200C RAMP DOWN 6C/SEC MAX Description RF SMA connectors DC bias test pins 100 pF capacitors, 0402 package 0.01 F capacitor, 0402 package 10 F capacitor, tantalum package Evaluation PCB, Rogers 4350B circuit board material TIME (Seconds) 60 SECONDS TO 180 SECONDS 15506-120 20 SECONDS TO 40 SECONDS 480 SECONDS MAX Figure 21. Pb-Free Reflow Solder Profile R1 J6 RFC VSS TP5 0 V3 R2 0 GND C6 0.01F 0 GND C7 0.01F 0 GND C8 0.01F GND C2 100pF GND C3 100pF GND C4 100pF GND C5 100pF GND R3 V2 19 V3 20 VSS 21 RFC GND 23 22 GND 24 GND GND ADRF5250 RF4 GND RF1 TP1 18 17 VDD 16 15 14 13 + C9 0.1F GND TP3 C10 10F RF1 J8 12 8 V1 TP2 GND GND GND 6 VDD RF2 5 GND GND RF4 U1 7 TP6 GND GND RF3 J5 15506-017 J2 V1 11 4 V2 RF5 10 3 GND GND 2 RF3 RF5 9 1 J1 GND PAD PAD R4 TP4 RF2 J7 Figure 22. ADRF5250-EVALZ Evaluation Board Schematic Rev. 0 | Page 13 of 15 ADRF5250 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 4.10 4.00 SQ 3.90 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 1 18 0.50 BSC 2.80 2.70 SQ 2.60 EXPOSED PAD 13 TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 6 12 7 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PKG-005108 SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 04-27-2017-A PIN 1 INDICATOR 0.30 0.25 0.20 COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-6. Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.75 mm Package Height (CP-24-23) Dimensions shown in millimeters 1.85 1.75 1.65 0.35 0.30 0.25 4.40 4.30 4.20 3 BSC (NOTE 6) 1.35 1.25 1.15 (NOTE 8) 12.30 12.00 11.70 (NOTE 2) (NOTE 1) 2.05 2.00 1.95 4.10 4.00 3.90 5.60 5.50 5.40 O 1.50 MIN (NOTE 1) TOP VIEW A 8.00 DETAIL A DIRECTION OF FEED SECTION A-A NOTES: 1. MEASURED FROM THE CENTERLINE OF SPROCKET HOLE TO CENTERLINE OF THE POCKET HOLE 2. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE IS 0.20 3. THICKNESS IS APPLICABLE AS MEASURED AT EDGE OF TAPE 4. BLACK POLYSTYRENE M ATERIAL 5. ALLOWABLE CAMBER TO BE 1 mm PER 100 mm IN LENGHT, NON-CUMULATIVE OVER 250 mm 6. MEASUREMENT POINT TO BE 0.3 mm FROM BOTTOM POCKET 7. SURFACE RESISTIVITY FROM 105 TO 1011 /SQ 8. KO MEASUREMENT POINT SHOULD NOT BE REFERED ON POCKET RIDGE R 0.50 0.50 0.40 0.30 R 0.50 DETAIL A 06-02-2017-A (NOTE 3) 1.60 O 1.55 1.50 A Figure 24. LFCSP Tape and Reel Outline Dimensions Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF5250BCPZ ADRF5250BCPZ-R7 ADRF5250BCPZRL ADRF5250-EVALZ 1 Temperature Range -40C to +105C -40C to +105C -40C to +105C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP], 7" Tape and Reel 24-Lead Lead Frame Chip Scale Package [LFCSP], 13" Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 14 of 15 Package Option CP-24-23 CP-24-23 CP-24-23 Data Sheet ADRF5250 NOTES (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15506-0-6/17(0) Rev. 0 | Page 15 of 15