CY7C1231H-133AXC - Cypress Semiconductor Corp

2-Mbit (128K x 18) Flow-Through SRAM

with NoBL™ Architecture

CY7C1231H

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-00207 Rev. *B Revised April 26, 2006

Features

• Can support up to 133-MHz bus operations with zero

wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 128K x 18 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times

— 6.5 ns (133-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed write

• Asynchr onous Output Enable

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• Burst Capability—linear or interle aved burst order

• Low standby power

Functional Description[1]

The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1231H is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of th e clock. The clo ck input is qual ified b y

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay fr om the clock rise is 6.5 ns (133-M Hz

device).

Write operations are controlled by the two Byte Write Select

(BW[A:B]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

MODE

OE READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

D0 Q1

ADV/LD

CE ADV/LD

CLK

CEN

WRITE

DRIVERS

WRITE ADDRESS

A0, A1, A

ZZ SLEEP

CONTROL

Logic Block Diagram

CY7C1231H

Document #: 001-00207 Rev. *B Page 2 of 12

Selection Guide

133 MHz Unit

Maximum Access T i me 6.5 ns

Maximum Operating Current 225 mA

Maximum CMOS Standby Current 40 mA

Pin Configuration

100-pin TQFP Pinout

NC/288M

NC/144M

VSS

VDD

NC(36M)

NC/4M

VDDQ

VSS

DQPA

DQA

VSS

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VDD

VSS

DQB

VDDQ

VSS

DQB

DQPB

VSS

VDDQ

CE1

CE2

BWB

BWA

CE3

VDD

VSS

CLK

CEN

NC(18M)

100

ANC(9M)

ADV/LD

MODE

NC(72M)

CY7C1231H

BYTE A

BYTE B

CY7C1231H

Document #: 001-00207 Rev. *B Page 3 of 12

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of

the CLK. A[1:0] are fed to the two-bit burst counter.

BW[A:B] Input-

Synchronous Byte Write Input s, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the

rising edge of CLK.

WE Input-

Synchronous Write Enab le Inpu t, ac tive LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence .

ADV/LD Input-

Synchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address. When

HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address

can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW

in order to load a new address.

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK

is only recognized if CEN is active LOW .

CE1Input-

Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE2, and CE3 to select/deselect the device.

CE2Input-

Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE3 to select/deselect the device.

CE3Input-

Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE2 to select/deselect the device.

OE Input-

Asynchronous Output Enable, asynchro no us input, active LOW. Combin ed with the synchronous logic block

inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave

as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked

during the data portion of a write sequence, during the first clock when emerging from a deselected

state, when the device has been deselected.

CEN Input-

Synchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.

When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the

device, CEN can be used to extend the previous cycle when required.

ZZ Input-

Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has

an internal pull-down.

DQsI/O-

Synchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and

the internal control logic. When OE is asserted LOW , the pins can behave as outputs. When HIGH,

DQs and DQP[A:B] are placed in a tri-state condition. The outputs are automatically tri-stated during

the data portion of a write sequence, during the first clock when emerging from a deselected state,

and when the device is deselected, rega rdless of the state of OE.

DQP[A:B] I/O-

Synchronous Bidirectional Data Parity I/O Lines. Fu nctionally, these signals are identical to DQs. During write

sequences, DQP[A:B] is controlled by BWx correspondingly.

Mode Input

Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When

tied to VDD or left floating selects interleaved burst sequence.

VDD Power Supply Power supply inputs to the core of the device.

VDDQ I/O Power

Supply Power supply for the I/O circuitry.

VSS Ground Ground for the device.

NC –No Connects. Not Internally connected to the die. 4M, 9M, 18M, 36M, 72M, 144M, 288M, 576M, and

1G are address expansion pins and are not internally connected to the die.

CY7C1231H

Document #: 001-00207 Rev. *B Page 4 of 12

Functional Overview

The CY7C1231H is a synchronous flow-through burst SRAM

designed specifically to eliminate wait states during

Write-Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous op erations

are qualified with CEN. Maximum access delay from the clock

rise (tCDV) is 6.5 ns (133-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, dep ending on

the status of the Write Enable (WE). BW[A:B] can be used to

conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enab le (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and 4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory array

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the output buffers. The data is available within 6.5

ns (133-MHz device) provided OE is active LOW. After the first

clock of the read access, the ou tput buffers are controlled b y

OE and the internal con trol logic. OE must be driven LOW in

order for the device to drive out the requested data. On the

subsequent clock, another operation (Read/Write/Deselect)

can be initiated. When the SRAM is deselected at clock rise

by one of the chip enable signals, its output will be tri-stated

immediately.

Burst Read Accesses

The CY7C1231H has an on-chip burst counter that allows the

user the ability to supply a si ngle address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address in to the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap around when incremented sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of Chip Enable inputs or WE. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted active, and (3) the Write signal WE

is asserted LOW. The address presented to the addre ss bus

is loaded into the Address Register. The write signals are

latched into the Control Logic block. The data lines are

automatically tri-stated regardless of the state of the OE input

signal. This allows the external logic to present the data on

DQs and DQP[A:B].

On the next clock rise the data presented to DQs and DQP[A:B]

(or a subset for Byte Write operations, see Truth Table for

details) inputs is latched into the device and the write is

complete. Additional accesses (Read/Write/Deselect) can be

initiated on this cycle.

The data written during the Write operation is controlled by

BW[A:B] signals. The CY7C1231H provides Byte Write

capability that is described in the Truth Table. Asserting the

Write Enable input (WE) with the selected Byte Write Select

input will selective ly write to only the desired bytes. Bytes not

selected during a Byte Write operation will remain unalte red.

A synchronous self-timed write mechanism has been provided

to simplify the Write operations. Byte Write capability has been

included in order to greatly simplify Read/Modify/Write

sequences, which can be reduced to simple byte write opera-

tions.

Because the CY7C1231H is a common I/O device, data

should not be driven into the device while the outputs are

active. The Output Enable (OE) can be deasserted HIGH

before presenting data to the DQs and DQP[A:B] inputs. Doing

so will tri-state the output drivers. As a safety precaution, DQs

and DQP[A:B].are automatically tri-stated during the data

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1231H has an on-chip burst counter that allows the

user the ability to supply a singl e address and conduct up to

four Write operations without reasserting the address inpu ts.

ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are

ignored and the burst counter is incremented. The correct

BW[A:B] inputs must be driven in each cycle of the burst write,

in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected p rior to entering

the “sleep” mode. CE1, CE2, and CE3, must remain inactive for

the duration of tZZREC after the ZZ input returns LOW.

CY7C1231H

Document #: 001-00207 Rev. *B Page 5 of 12

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Interleaved Burst Sequence

First

Address Second

Address Third

Address Fourth

Address

A1, A0 A1, A0 A1, A0 A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Sleep mode standby current ZZ > VDD − 0.2V 40 mA

tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 ns

Truth Table[2, 3, 4, 5, 6, 7, 8]

Operation Address

Used CE1CE2 CE3ZZ ADV/LD WE BWXOE CEN CLK DQ

Deselect Cycle None H X X L L X X X L L->H Tri-State

Deselect Cycle None X X H L L X X X L L->H Tri-State

Deselect Cycle None X L X L L X X X L L->H Tri-State

Continue Deselect Cycle None X X X L H X X X L L->H Tri-State

READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)

READ Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)

NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H Tri-State

DUMMY READ (Continue Burst) Next X X X L H X X H L L->H Tri-State

WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)

WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)

NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Tri-State

WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Tri-State

IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H –

Sleep MODE None X X X H X X X X X X Tri-State

Truth Table for Read/Write [2, 3]

Function WE BWABWB

Read HXX

Write – No bytes written L H H

Write Byte A – (DQA and DQPA)LHH

Write Byte B – (DQB and DQPB)LHH

Write All Bytes L L L

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write

selects are asserted, see Truth Table for details.

3. Write is defined by BW[A:B], and WE. See Truth Table for Read/Write.

4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

5. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = Tri-state when

OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.

CY7C1231H

Document #: 001-00207 Rev. *B Page 6 of 12

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........–0.5V to +4.6V

Supply Voltage on VDDQ Relative to GND......–0.5V to +VDD

DC Voltage Applied to Outputs

in Tri-State................. ... ....................... –0.5V to VDDQ + 0.5V

DC Input Voltage .......................... .. .......–0.5V to VDD + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current............... ... ... ............................... > 200 mA

Operating Range

Range Ambient

Temperature (TA)V

DD VDDQ

Commercial 0°C to +70°C 3.3V –

5%/+10% 2.5V – 5% to

VDD

Industrial -40°C to +85°C

Electrical Characteristics Over the Operating Range [9,10]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage for 3.3V I/O 3.135 VDD V

for 2.5V I/O 2.375 2.625 V

VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA 2.4 V

for 2.5V I/O, IOH = –1.0 mA 2.0

VOL Output LOW Voltage for 3.3V I/O, IOL = 8. 0 mA 0.4 V

for 2.5V I/O, IOL = 1. 0 mA 0.4

VIH Input HIGH Voltage for 3.3V I/O 2.0 VDD + 0.3V V

for 2.5V I/O 1.7 VDD + 0.3V

VIL Input LOW Voltage[9] for 3.3V I/O –0.3 0.8 V

for 2.5V I/O –0.3 0.7

IXInput Leakage Current

except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5 µA

Input Current of MODE Input = VSS –30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS –5 µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA

IDD VDD Operating Supply

Current VDD = Max., IOUT = 0 mA,

f = fMAX= 1/tCYC 7.5-ns cycle, 133 MHz 225 mA

ISB1 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = fMAX,

inputs switching

7.5-ns cycle, 133 MHz 90 mA

ISB2 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,

f = 0, inputs static

7.5-ns cycle, 133 MHz 40 mA

ISB3 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V ,

f = fMAX, inputs switching

7.5-ns cycle, 133 MHz 75 mA

ISB4 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,

f = 0, inputs static

7.5-ns cycle, 133 MHz 45 mA

Notes:

9. Overshoot: VIH(AC) < VDD +1.5V (Pulse wid th less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).

10.TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During thi s ti me VIH < VDD and VDDQ < VDD.

CY7C1231H

Document #: 001-00207 Rev. *B Page 7 of 12

Capacitance[11]

Parameter Description Test Conditions 100 TQFP

Max. Unit

CIN Input Capacitance TA = 25°C , f = 1 MHz,

VDD = 3.3V

VDDQ = 2.5V

5pF

CCLOCK Clock Input Capacitance 5 pF

CI/O I/O Capacitance 5 pF

Thermal Resistance[11]

Parameters Description Test Conditions 100 TQFP

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient) T est conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

30.32 °C/W

ΘJC Thermal Resistance

(Junction to Case) 6.85 °C/W

AC Test Loads and Waveforms

Note:

11.Tested initially and after any design or process change tha t may affect these parameters.

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

3.3V I/O Test Load

OUTPUT

R = 1667Ω

R =1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

2.5V I/O Test Load

CY7C1231H

Document #: 001-00207 Rev. *B Page 8 of 12

Switching Characteristics Over the Operating Range [12, 13]

Parameter Description

-133

UnitMin. Max.

tPOWER VDD(Typical) to the first Access[14] 1ms

Clock

tCYC Clock Cycle Time 7.5 ns

tCH Clock HIGH 2.5 ns

tCL Clock LOW 2.5 ns

Output Times

tCDV Data Output Valid after CLK Rise 6.5 ns

tDOH Data Output Hold after CLK Rise 2.0 ns

tCLZ Clock to Low-Z[15, 16, 17] 0ns

tCHZ Clock to High-Z[15, 16, 17] 3.5 ns

tOEV OE LOW to Output Valid 3.5 ns

tOELZ OE LOW to Output Low-Z[15, 16, 17] 0ns

tOEHZ OE HIGH to Output High-Z[15, 16, 17] 3.5 ns

Set-up Times

tAS Address Set-up before CLK Rise 1.5 ns

tALS ADV/LD Set-up before CLK Rise 1.5 ns

tWES WE, BW[A:B] Set-up before CLK Rise 1.5 ns

tCENS CEN Set-up before CLK Rise 1.5 ns

tDS Data Input Set-up before CLK Rise 1.5 ns

tCES Chip Enable Set-up before CLK Rise 1.5 ns

Hold Times

tAH Address Hold after CLK Rise 0.5 ns

tALH ADV/LD Hold after CLK Rise 0.5 ns

tWEH WE, BW[A:B] Hold after CLK Rise 0.5 ns

tCENH CEN Hold after CLK Rise 0.5 ns

tDH Data Input Hold after CLK Rise 0.5 ns

tCEH Chip Enable Hold after CLK Rise 0.5 ns

Notes:

12.Timing reference level is 1. 5V when VDDQ = 3.3V and 1.25V when VDDQ = 2.5V.

13.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.

14.This part has a vo lt age reg ulator i nternal ly; t POWER is the time t hat the po wer needs to be supplied a bove VDD minimum initiall y bef ore a rea d or write op eration

can be initiated.

15.tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. T ransition is measured ± 200 mV from steady-state voltage.

16.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but refl ect paramet ers guarant eed over worst case user condition s. Device is designed

to achieve tri-state prior to Low-Z under the same system conditions.

17.This parameter is sampled and not 1 00% tested.

CY7C1231H

Document #: 001-00207 Rev. *B Page 9 of 12

Switching Waveforms

Read/Write Waveforms[18, 19, 20]

Notes:

18.For this waveform ZZ is tied LOW.

19.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

20.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst ope rations are optional.

WRITE

D(A1)

123456789

CLK

tCYC

tCL

tCH

tCEH

tCES

CEN

tCENH

tCENS

[A:B]

ADV/LD

tAH

tAS

ADDRESS A1 A2 A3 A4 A5 A6 A7

tDH

tDS

OMMAND

tCLZ

D(A1) D(A2) Q(A4)Q(A3)

D(A2+1)

tDOH tCHZ

tCDV

WRITE

D(A2) BURST

WRITE

D(A2+1)

READ

Q(A3) READ

Q(A4) BURST

READ

Q(A4+1)

WRITE

D(A5) READ

Q(A6) WRITE

D(A7) DESELECT

tOEV

tOELZ

tOEHZ

DON’T CARE UNDEFINED

D(A5)

tDOH

Q(A4+1)

D(A7)Q(A6)

CY7C1231H

Document #: 001-00207 Rev. *B Page 10 of 12

NOP, STALL and Des elect Cyc les[18, 19, 21]

ZZ Mode Timing[22, 23]

Notes:

21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

22.Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.

23.I/Os are in tri-state when exiting ZZ sleep mode.

Switching Waveforms (continued)

READ

Q(A3)

45678910

A3 A4 A5

D(A4)

123

CLK

CEN

BW[A:B]

ADV/LD

ADDRESS

OMMAND WRITE

D(A4) STALLWRITE

D(A1) READ

Q(A2) STALL NOP READ

Q(A5) DESELECT CONTINUE

DESELECT

DON’T CARE UNDEFINED

tCHZ

A1 A2

Q(A2)D(A1) Q(A3) tDOHQ(A5)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

CY7C1231H

Document #: 001-00207 Rev. *B Page 11 of 12

© Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to change without notice. Cypress S em icon duct or Corpo ration assu mes no resp onsib ility for th e u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device

Technology, In c. All product and company names mentioned in this document are the trademarks of th eir respective holders.

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered”.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

133 CY7C1231H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1231H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

Package Diagram

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL A

DETAIL

100

31 50

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

CY7C1231H

Document #: 001-00207 Rev. *B Page 12 of 12

Document History Page

Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Archite cture

Document Number: 001-00207

REV. ECN NO. Issue Date Orig. of

Change Description of Cha ng e

** 347377 See ECN PCI New Data Sheet

*A 428408 See ECN NXR Converted from Preliminary to Final.

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Removed 100 MHz Speed-bin

Changed Three-State to Tri-State.

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table.

Modified test condition from VDDQ < VDD to VDDQ < VDD

Replaced Package Name column with Packag e Diagram in the Ordering

Information table.

Updated the Ordering Information Table.

Replaced Package Diagram of 51-85050 from *A to *B

*B 459347 See ECN NXR Included 2.5V I/O option

Updated the Ordering Information table.