2010 Microchip Technology Inc. DS41190G
PIC12F629/675
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
DS41190G-page 2 2010 Microchip Technology Inc.
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Printed on recycled paper.
ISBN: 978-1-60932-160-4
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc. DS41190G-page 3
PIC12F629/675
High-Performance RISC CPU:
Only 35 Instructions to Learn
- All single-cycle instructions except branches
Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
Interrupt Capability
8-Level Deep Hardware Stack
Direct, Indirect, and Relative Addressing modes
Special Microcontroller Features:
Internal and External Oscillator Options
- Precision Internal 4 MHz oscillator factory
calibrated to ±1%
- External Oscillator support for crystals and
resonators
-5s wake-up from Sleep, 3.0V, typical
Power-Saving Sleep mode
Wide Operating Voltage Range – 2.0V to 5.5V
Industrial and Extended Temperature Range
Low-Power Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Brown-out Detect (BOD)
Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
Multiplexed MCLR/Input Pin
Interrupt-on-Pin Change
Individual Programmable Weak Pull-ups
Programmable Code Protection
High Endurance Flash/EEPROM Cell
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM Retention: > 40 years
Low-Power Features:
Standby Current:
- 1 nA @ 2.0V, typical
Operating Current:
-8.5A @ 32 kHz, 2.0V, typical
-100A @ 1 MHz, 2.0V, typical
Watchdog Timer Current
- 300 nA @ 2.0V, typical
Timer1 Oscillator Current:
-4A @ 32 kHz, 2.0V, typical
Peripheral Features:
6 I/O Pins with Individual Direction Control
High Current Sink/Source for Direct LED Drive
Analog Comparator module with:
- One analog comparator
- Programmable on-chip comparator voltage
reference (CVREF) module
- Programmable input multiplexing from device
inputs
- Comparator output is externally accessible
Analog-to-Digital Converter module (PIC12F675):
- 10-bit resolution
- Programmable 4-channel input
- Voltage reference input
Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator, if INTOSC mode
selected
In-Circuit Serial ProgrammingTM (ICSPTM) via
two pins
* 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
Device
Program
Memory Data Memory
I/O 10-bit A/D
(ch) Comparators Timers
8/16-bit
Flash
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC12F629 1024 64 128 6 1 1/1
PIC12F675 1024 64 128 6 4 1 1/1
8-Pin Flash-Based 8-Bit CMOS Microcontroller
PIC12F629/675
DS41190G-page 4 2010 Microchip Technology Inc.
Pin Diagrams
VSSVDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT
1
2
3
45
6
7
8
PIC12F675
VSS
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
1
2
3
45
6
7
8
PIC12F629
8-pin PDIP, SOIC, DFN-S, DFN
2010 Microchip Technology Inc. DS41190G-page 5
PIC12F629/675
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 7
2.0 Memory Organization.................................................................................................................................................................. 9
3.0 GPIO Port ................................................................................................................................................................................. 21
4.0 Timer0 Module .......................................................................................................................................................................... 29
5.0 Timer1 Module with Gate Control ............................................................................................................................................. 32
6.0 Comparator Module .................................................................................................................................................................. 37
7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) ................................................................................................... 43
8.0 Data EEPROM Memory ............................................................................................................................................................ 49
9.0 Special Features of the CPU .................................................................................................................................................... 53
10.0 Instruction Set Summary ........................................................................................................................................................... 71
11.0 Development Support ............................................................................................................................................................... 81
12.0 Electrical Specifications ............................................................................................................................................................ 85
13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 107
14.0 Packaging Information ............................................................................................................................................................ 117
Appendix A: Data Sheet Revision History ......................................................................................................................................... 127
Appendix B: Device Differences ....................................................................................................................................................... 127
Appendix C: Device Migrations ......................................................................................................................................................... 128
Appendix D: Migrating from other PIC® Devices .............................................................................................................................. 128
Index ................................................................................................................................................................................................. 129
On-Line Support ................................................................................................................................................................................ 133
Systems Information and Upgrade Hot Line ..................................................................................................................................... 133
Reader Response ............................................................................................................................................................................. 134
Product Identification System ........................................................................................................................................................... 135
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PIC12F629/675
DS41190G-page 6 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS41190G-page 7
PIC12F629/675
1.0 DEVICE OVERVIEW
This document contains device specific information for
the PIC12F629/675. Additional information may be
found in the PIC® Mid-Range Reference Manual
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this Data
Sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
The PIC12F629 and PIC12F675 devices are covered
by this Data Sheet. They are identical, except the
PIC12F675 has a 10-bit A/D converter. They come in
8-pin PDIP, SOIC, MLF-S and DFN packages.
Figure 1-1 shows a block diagram of the PIC12F629/
675 devices. Table 1-1 shows the pinout description.
FIGURE 1-1: PIC12F629/675 BLOCK DIAGRAM
Flash
Program
Memory
1K x 14
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
8-Level Stack
(13-bit)
RAM
File
Registers
64 x 8
Direct Addr 7
Addr(1)
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
8
8
Brown-out
Detect
8
3
Timing
Generation
GP5/T1CKI/OSC1/CLKIN
Internal
4 MHz
RAM
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP2/AN2/T0CKI/INT/COUT
GP1/AN1/CIN-/VREF
GP0/AN0/CIN+
Oscillator
Note 1: Higher order bits are from STATUS register.
Analog
Timer0 Timer1
DATA
EEPROM
128 bytes
EEDATA
EEADDR
Comparator
Analog to Digital Converter
(PIC12F675 only)
AN0 AN1 AN2 AN3
CIN- CIN+ COUT
T0CKI
T1CKI
VREF
and reference
T1G
8
PIC12F629/675
DS41190G-page 8 2010 Microchip Technology Inc.
TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION
Name Function Input
Type
Output
Type Description
GP0/AN0/CIN+/ICSPDAT GP0 TTL CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN0 AN A/D Channel 0 input
CIN+ AN Comparator input
ICSPDAT TTL CMOS Serial programming I/O
GP1/AN1/CIN-/VREF/
ICSPCLK
GP1 TTL CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN1 AN A/D Channel 1 input
CIN- AN Comparator input
VREF AN External voltage reference
ICSPCLK ST Serial programming clock
GP2/AN2/T0CKI/INT/COUT GP2 ST CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN2 AN A/D Channel 2 input
T0CKI ST TMR0 clock input
INT ST External interrupt
COUT CMOS Comparator output
GP3/MCLR/VPP GP3 TTL Input port w/ interrupt-on-change
MCLR ST Master Clear
VPP HV Programming voltage
GP4/AN3/T1G/OSC2/
CLKOUT
GP4 TTL CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN3 AN A/D Channel 3 input
T1G ST TMR1 gate
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
T1CKI ST TMR1 clock
OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/RC oscillator connection
VSS VSS Power Ground reference
VDD VDD Power Positive supply
Legend: Shade = PIC12F675 only
TTL = TTL input buffer, ST = Schmitt Trigger input buffer
2010 Microchip Technology Inc. DS41190G-page 9
PIC12F629/675
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F629/675 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h-03FFh)
for the PIC12F629/675 devices is physically imple-
mented. Accessing a location above these boundaries
will cause a wrap-around within the first 1K x 14 space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 2-1).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
DSTEMP/675
2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose
Registers and the Special Function Registers. The
Special Function Registers are located in the first 32
locations of each bank. Register locations 20h-5Fh are
General Purpose Registers, implemented as static
RAM and are mapped across both banks. All other
RAM is unimplemented and returns ‘0’ when read. RP0
(STATUS<5>) is the bank select bit.
•RP0 = 0 Bank 0 is selected
•RP0 = 1 Bank 1 is selected
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F629/675 devices. Each register is accessed,
either directly or indirectly, through the File Select
Register FSR (see Section 2.4 “Indirect Addressing,
INDF and FSR Registers”).
PC<12:0>
13
000h
0004
0005
03FFh
0400h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Note: The IRP and RP1 bits STATUS<7:6> are
reserved and should always be maintained
as ‘0’s.
PIC12F629/675
DS41190G-page 10 2010 Microchip Technology Inc.
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
FIGURE 2-2: DATA MEMORY MAP OF
THE PIC12F629/675
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Bank 0
Unimplemented data memory locations, read as ‘0’.
1: Not a physical register.
2: PIC12F675 only.
CMCON VRCON
General
Purpose
Registers accesses
20h-5Fh
64 Bytes
EEDATA
EEADR
EECON2(1)
5Fh
60h
File
Address
File
Address
WPU
IOC
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCCAL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
Bank 1
DFh
E0h
ADRESH(2)
ADCON0(2)
EECON1
ADRESL(2)
ANSEL(2)
2010 Microchip Technology Inc. DS41190G-page 11
PIC12F629/675
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOD Page
Bank 0
00h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 20,61
01h TMR0 Timer0 Module’s Register xxxx xxxx 29
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19
03h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC
0001 1xxx 14
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 20
05h GPIO GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx 21
06h Unimplemented
07h Unimplemented
08h Unimplemented
09h Unimplemented
0Ah PCLATH Write Buffer for Upper 5 bits of Program Counter ---0 0000 19
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 15
0Ch PIR1 EEIF ADIF —CMIF—TMR1IF00-- 0--0 17
0Dh Unimplemented
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit Timer1 xxxx xxxx 32
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit Timer1 xxxx xxxx 32
10h T1CON TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 35
11h Unimplemented
12h Unimplemented
13h Unimplemented
14h Unimplemented
15h Unimplemented
16h Unimplemented
17h Unimplemented
18h Unimplemented
19h CMCON COUT CINV CIS CM2 CM1 CM0 -0-0 0000 38
1Ah Unimplemented
1Bh Unimplemented
1Ch Unimplemented
1Dh Unimplemented
1Eh ADRESH(3) Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result xxxx xxxx 44
1Fh ADCON0(3) ADFM VCFG CHS1 CHS0 GO/DONE ADON 00-- 0000 45,61
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
PIC12F629/675
DS41190G-page 12 2010 Microchip Technology Inc.
Bank 1
80h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 20,61
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14,31
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19
83h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC0001 1xxx 14
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 20
85h TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 21
86h Unimplemented
87h Unimplemented
88h Unimplemented
89h Unimplemented
8Ah PCLATH —— Write Buffer for Upper 5 bits of Program Counter ---0 0000 19
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 15
8Ch PIE1 EEIE ADIE —CMIE—TMR1IE00-- 0--0 16
8Dh Unimplemented
8Eh PCON ——————PORBOD ---- --0x 18
8Fh Unimplemented
90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 1000 00-- 18
91h Unimplemented
92h Unimplemented
93h Unimplemented
94h Unimplemented
95h WPU WPU5 WPU4 WPU2 WPU1 WPU0 --11 -111 21
96h IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 23
97h Unimplemented
98h Unimplemented
99h VRCON VREN VRR VR3 VR2 VR1 VR0 0-0- 0000 42
9Ah EEDATA Data EEPROM Data Register 0000 0000 49
9Bh EEADR Data EEPROM Address Register -000 0000 49
9Ch EECON1 ——— WRERR WREN WR RD ---- x000 50
9Dh EECON2(1) EEPROM Control Register 2 ---- ---- 50
9Eh ADRESL(3) Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result xxxx xxxx 44
9Fh ANSEL(3) ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 46,61
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOD Page
2010 Microchip Technology Inc. DS41190G-page 13
PIC12F629/675
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains:
the arithmetic status of the ALU
the Reset status
the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Status bits, see the “Instruction Set Summary”.
REGISTER 2-1: STATUS: STATUS REGISTER (ADDRESS: 03h OR 83h)
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC12F629/675 and should
be maintained as clear. Use of these bits
is not recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: This bit is reserved and should be maintained as ‘0
bit 6 RP1: This bit is reserved and should be maintained as ‘0
bit 5 RP0: Register Bank Select bit (used for direct addressing)
0 = Bank 0 (00h - 7Fh)
1 = Bank 1 (80h - FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT Time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
For borrow, the polarity is reversed.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
PIC12F629/675
DS41190G-page 14 2010 Microchip Technology Inc.
2.2.2.2 OPTION Register
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
TMR0/WDT prescaler
External GP2/INT interrupt
•TMR0
Weak pull-ups on GPIO
REGISTER 2-2: OPTION_REG: OPTION REGISTER (ADDRESS: 81h)
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ (OPTION<3>). See
Section 4.4 “Prescaler”.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
2010 Microchip Technology Inc. DS41190G-page 15
PIC12F629/675
2.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO port change and
external GP2/INT pin interrupts.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
bit 3 GPIE: Port Change Interrupt Enable bit(1)
1 = Enables the GPIO port change interrupt
0 = Disables the GPIO port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
bit 0 GPIF: Port Change Interrupt Flag bit
1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)
0 = None of the GP5:GP0 pins have changed state
Note 1: IOC register must also be enabled to enable an interrupt-on-change.
2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
PIC12F629/675
DS41190G-page 16 2010 Microchip Technology Inc.
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
EEIE ADIE CMIE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only)
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4 Unimplemented: Read as ‘0
bit 3 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 2-1 Unimplemented: Read as ‘0
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
2010 Microchip Technology Inc. DS41190G-page 17
PIC12F629/675
2.2.2.5 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
EEIF ADIF —CMIF —TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only)
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ‘0
bit 3 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 2-1 Unimplemented: Read as ‘0
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
PIC12F629/675
DS41190G-page 18 2010 Microchip Technology Inc.
2.2.2.6 PCON Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
Power-on Reset (POR)
Brown-out Detect (BOD)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6: PCON: POWER CONTROL REGISTER (ADDRESS: 8Eh)
2.2.2.7 OSCCAL Register
The Oscillator Calibration register (OSCCAL) is used to
calibrate the internal 4 MHz oscillator. It contains 6 bits
to adjust the frequency up or down to achieve 4 MHz.
The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7: OSCCAL: OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x
—PORBOD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOD: Brown-out Detect Status bit
1 = No Brown-out Detect occurred
0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits
111111 = Maximum frequency
100000 = Center frequency
000000 = Minimum frequency
bit 1-0 Unimplemented: Read as ‘0
2010 Microchip Technology Inc. DS41190G-page 19
PIC12F629/675
2.3 PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 2-3 shows the
two situations for the loading of the PC. The upper
example in Figure 2-3 shows how the PC is loaded on
a write to PCL (PCLATH<4:0> PCH). The lower
example in Figure 2-3 shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH<4:3>
PCH).
FIGURE 2-3: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the PC (ADDWF PCL). When performing a table read
using a computed GOTO method, care should be
exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the
Application Note, “Implementing a Table Read”
(AN556).
2.3.2 STACK
The PIC12F629/675 family has an 8-level deep x 13-bit
wide hardware stack (see Figure 2-1). The stack space
is not part of either program or data space and the
Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is
executed, or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate Stack
Overflow or Stack Underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
PIC12F629/675
DS41190G-page 20 2010 Microchip Technology Inc.
2.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-2.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESSING
FIGURE 2-2: DIRECT/INDIRECT ADDRESSING PIC12F629/675
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
For memory map detail see Figure 2-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
Data
Memory
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1(1) RP0 6 0
From Opcode IRP(1) FSR Register
70
Bank Select Location Select
00 01 10 11
180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Not Used
2010 Microchip Technology Inc. DS41190G-page 21
PIC12F629/675
3.0 GPIO PORT
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
3.1 GPIO and the TRISIO Registers
GPIO is an 6-bit wide, bidirectional port. The
corresponding data direction register is TRISIO.
Setting a TRISIO bit (= 1) will make the corresponding
GPIO pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISIO
bit (= 0) will make the corresponding GPIO pin an
output (i.e., put the contents of the output latch on the
selected pin). The exception is GP3, which is input-only
and its TRISIO bit will always read as ‘1’. Example 3-1
shows how to initialize GPIO.
Reading the GPIO register reads the status of the pins,
whereas writing to it will write to the PORT latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the
PORT data latch. GP3 reads ‘0’ when MCLREN = 1.
The TRISIO register controls the direction of the
GP pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
register are maintained set when using them as analog
inputs. I/O pins configured as analog inputs always
read ‘0’.
EXAMPLE 3-1: INITIALIZING GPIO
3.2 Additional Pin Functions
Every GPIO pin on the PIC12F629/675 has an
interrupt-on-change option and every GPIO pin, except
GP3, has a weak pull-up option. The next two sections
describe these functions.
3.2.1 WEAK PULL-UP
Each of the GPIO pins, except GP3, has an individually
configurable weak internal pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 3-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit
(OPTION<7>).
REGISTER 3-1: GPIO: GPIO REGISTER (ADDRESS: 05h)
Note: Additional information on I/O ports may be
found in the PIC® Mid-Range Reference
Manual, (DS33023).
Note: The ANSEL (9Fh) and CMCON (19h)
registers (9Fh) must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’. The ANSEL register is defined for
the PIC12F675.
BCF STATUS,RP0 ;Bank 0
CLRF GPIO ;Init GPIO
MOVLW 07h ;Set GP<2:0> to
MOVWF CMCON ;digital IO
BSF STATUS,RP0 ;Bank 1
CLRF ANSEL ;Digital I/O
MOVLW 0Ch ;Set GP<3:2> as inputs
MOVWF TRISIO ;and set GP<5:4,1:0>
;as outputs
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 GPIO<5:0>: General Purpose I/O pin
1 = Port pin is >VIH
0 = Port pin is <VIL
PIC12F629/675
DS41190G-page 22 2010 Microchip Technology Inc.
REGISTER 3-2: TRISIO: GPIO TRI-STATE REGISTER (ADDRESS: 85h)
REGISTER 3-3: WPU: WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 TRISIO<5:0>: General Purpose I/O Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
Note: TRISIO<3> always reads ‘1’.
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
WPU5 WPU4 WPU2 WPU1 WPU0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-4 WPU<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3 Unimplemented: Read as ‘0
bit 2-0 WPU<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).
2010 Microchip Technology Inc. DS41190G-page 23
PIC12F629/675
3.2.2 INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of GPIO. This will end the
mismatch condition.
b) Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
REGISTER 3-4: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 IOC<5:0>: Interrupt-on-Change GPIO Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.