ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 1/14
PSRAM 2-Mbit (128K x 16)
Pseudo Static RAM
Features
• Wide voltage range: 2.7V–3.6V
• Access Time: 55 ns, 70 ns
• Ultra-low active power
— Typical active current: 1mA @ f = 1 MHz
— Typical active current: 14 mA @ f = fmax (For 55-ns)
—Typical active current: 8 mA @ f = fmax (For 70-ns)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The M24L216128SA is a high-performance CMOS Pseudo
Static RAM organized as 128K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the chip is deselected ( CE
HIGH), or when the outputs are disabled ( OE HIGH), or
when both Byte High Enable and Byte Low Enable are
disabled ( BHE , BLE HIGH), or during a write operation
(CE LOW and WE LOW).
Writing to the device is accomplished by asserting Chip
Enable ( CE LOW) and Write Enable ( WE ) input LOW. If
Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A16). If Byte High Enable ( BHE ) is
LOW, then data from I/O pins (I/O8 through I/O15) is written
into the location specified on the address pins (A0 through
A16).
Reading from the device is accomplished by asserting Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable ( WE ) HIGH. If Byte Low Enable
(BLE ) is LOW, then data from the memory location specified
by the address pins will appear on I/O0 to I/O7. If Byte High
Enable( BHE ) is LOW, then data from memory will appear on
I/O8 to I/O15. Refer to the truth table for a complete description
of read and write modes.
Logic Block Diagram
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 2/14
Pin Configuration[2, 3, 4]
48-ball VFBGA
Top View
44-pin TSOPII
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
V
CC
V
SS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
V
SS
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 3/14
Product Portfolio Product
Power Dissipation
Operating ICC(mA)
VCC Range (V)
f = 1MHz f = fmax
Standby ISB2(µA) Product
Min. Typ. Max.
Speed(ns)
Typ.[5] Max. Typ.[5] Max. Typ. [5] Max.
55 14 22
M24L216128SA 2.7 3.0 3.6
70
1 5
8 15
9 40
Notes:
2.Ball D3, H1, G2 and ball H6 for the FBGA package can be used to upgrade to a 4-Mbit, 8-Mbit, 16-Mbit and a 32-Mbit density,
respectively.
3.NC “no connect”—not connected internally to the die.
4.DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application.
5.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.),
TA = 25°C.
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 4/14
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to Ground Potential ..................−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[3, 4, 5] .......................................−0.4V to 3.7V
DC Input Voltage[3, 4, 5] ....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ...............................20 mA
Static Discharge Voltage ........................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range Ambient
Temperature(TA) VCC
Extended −25°C to +85°C 2.7V to 3.6V
Industrial −40°C to +85°C 2.7V to 3.6V
Electrical Characteristics (Over the Operating Range) -55 -70
Parameter Description Test Conditions Min. Typ
.[5] Max. Min. Typ.
[5] Max. Unit
VCC Supply Voltage 2.7 3.0 3.6 2.7 3.0 3.6 V
VOH Output HIGH
Voltage IOH = −0.1 mA VCC = 2.70V VCC-
0.4
VCC-
0.4 V
VOL Output LOW
Voltage IOL = 0.1 mA VCC = 2.70V 0.4 0.4 V
VIH Input HIGH
Voltage VCC = 2.7V to 3.6V 0.8*
VCC VCC+
0.4V
0.8*
VCC VCC+
0.4V V
VIL Input LOW Voltage -0.4 0.4 -0.4 0.4 V
IIX Input Leakage
Current GND ≤VIN ≤ V
CC -1 +1 -1 +1
µA
IOZ Output Leakage
Current GND ≤ V
OUT ≤ V
CC, Output Disabled -1 +1 -1 +1
µA
f = fMAX = 1/tRC 14 22 8 15 mA
ICC VCC Operating
Supply Current f = 1 MHz
VCC = VCCmax
IOUT = 0mA
CMOS levels 1 5 1 5 mA
ISB1
Automatic CE
Power-Down
Current
—CMOS Inputs
CE ≥VCC − 0.2V
VIN ≥VCC − 0.2V, VIN ≤ 0.2V, f = fMAX
(Address and Data Only), f = 0 ( OE ,
WE ,BHE and BLE ), VCC=3.6V
40 250 40 250 µA
ISB2
Automatic CE
Power-Down
Current
—CMOS Inputs
CE ≥VCC−0.2V
VIN ≥ V
CC − 0.2V or VIN ≤ 0.2V, f = 0,
VCC =3.6V
9 40 9 40 µA
Capacitance[9]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance 8 pF
COUT Output Capacitance
TA = 25°C, f = 1 MHz
VCC = VCC(typ) 8 pF
Thermal Resistance[9]
Parameter Description Test Conditions BGA Unit
ΘJA Thermal Resistance(Junction to Ambient) Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51.
55 °C/W
ΘJC Thermal Resistance (Junction to Case) 17 °C/W
Notes: 6.VIL(MIN) = –0.5V for pulse durations less than 20 ns.
7.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
8.Overshoot and undershoot specifications are characterized and are not 100% tested.
9.Tested initially and after any design or process changes that may affect these parameters.
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 5/14
AC Test Loads and Waveforms
Parameters 3.0V VCC Unit
R1 22000 Ω
R2 22000 Ω
RTH 11000 Ω
VTH 1.50 V
Switching Characteristics Over the Operating Range[10]
-55 [14] -70
Parameter Description
Min. Max. Min. Max.
Unit
Read Cycle
tRC Read Cycle Time 55[14] 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 10 ns
tACE CE LOW to Data Valid 55 70
ns
tDOE OE LOW to Data Valid 25 35
ns
tLZOE OE LOW to LOW Z[11, 13] 5 5
ns
tHZOE OE HIGH to High Z[11, 13] 25 25
ns
tLZCE CE LOW to Low Z[11, 13] 2 5
ns
tHZCE CE HIGH to High Z[11, 13] 25 25
ns
tDBE BLE /BHE LOW to Data Valid 55 70
ns
tLZBE BLE /BHE LOW to Low Z[11, 13] 5 5
ns
tHZBE BLE /BHE HIGH to HIGH Z[11, 13] 10 25
ns
tSK[14] Address Skew 0 10 ns
Write Cycle[12]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60
ns
tAW Address Set-Up to Write End 45 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 40 45
ns
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test
Loads and Waveforms” section.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.12.The internal Write
time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing
should be referenced to the edge of the signal that terminates the write.
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 6/14
Switching Characteristics Over the Operating Range (continued)[10]
-55 [14] -70 Unit
Parameter Description Min. Max. Min. Max.
tBW BLE/BHE LOW to Write End 50 60 ns
tSD Data Set-Up to Write End 25 45 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High-Z[11, 13] 25 25
ns
tLZWE WE HIGH to Low-Z[11, 13] 5 5 ns
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[15, 16, 17]
Read Cycle 2 (OE Controlled)[16, 17]
Notes:
15. Device is continuously selected. OE , CE = VIL.
16. WE is HIGH for Read Cycle.
17. For the 55-ns Cycle, the addresses must not toggle once the read is started on the device. For the 70-ns Cycle, the
addresses must be stable within 10 ns after the start of the read cycle.
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 7/14
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[12, 13, 18, 19, 20]
Write Cycle 2 (CE Controlled)[12, 13, 18, 19, 20]
Notes:
18.Data I/O is high impedance if OE ≥ V
IH.
19.If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state.
20.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 8/14
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[19, 20]
Write Cycle 4 (BHE /BLE Controlled, O
E
LOW)[19, 20]
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 9/14
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during
15μs shown as in Avoidable timing 1 or toggle CE to high (≧tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
Avoidable Timing 1
Avoidable Timing 2
CE
≧15μs
WE
Address
＜ tRC
CE
≧15μs
WE
Address
t≧RC
CE
≧15μs
WE
Address
＜ tRC
t≧RC
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 10/14
Truth Table[21]
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
X X X H H High Z Deselect/Power-Down Standby (ISB)
L H L L L Data Out (I/O0–I/O15) Read Active (ICC)
L H L H L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15) Read Active (ICC)
L H L L H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15) Read Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L L X L L Data In (I/O0–I/O15) Write
Active (ICC)
L L X H L
Data In (I/O0–I/O7);
High Z (I/O8–I/O15) Write Active (ICC)
L L X L H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15) Write Active (ICC)
Note:
21.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Ordering information
Speed(ns) Ordering Code Package Type Operating Range
55 M24L216128SA-55BEG 48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free) Extended
70 M24L216128SA-70BEG 48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free) Extended
55 M24L216128SA-55TEG 44-pin TSOPII (Pb-free) Extended
70 M24L216128SA-70TEG 44-pin TSOPII (Pb-free) Extended
55 M24L216128SA-55BIG 48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free) Industrial
70 M24L216128SA-70BIG 48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free) Industrial
55 M24L216128SA-55TIG 44-pin TSOPII (Pb-free) Industrial
70 M24L216128SA-70TIG 44-pin TSOPII (Pb-free) Industrial
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 11/14
Package Diagram
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 12/14
44-LEAD TSOP(II) PRAM(400mil)
Symbol Dimension in mm Dimension in inch
Min Norm Max Min Norm Max
A
1.20
0.047
A1 0.05
0.15 0.002
0.006
A2 0.95 1.00 1.05 0.037 0.039 0.042
B 0.30
0.45 0.012
0.018
B1 0.30 0.35 0.40 0.012 0.014 0.016
C 0.12
0.21 0.005
0.008
C1 0.10
0.16 0.004
0.006
D 18.28 18.41 18.54 0.720 0.725 0.730
ZD 0.805 REF 0.0317 REF
E 11.56 11.76 11.96 0.455 0.463 0.471
E1 10.03 10.16 10.29 0.395 0.400 0.4
L 0.40 0.59 0.69 0.016 0.023 0.027
L1 0.80 REF 0.031 REF
e 0.80 BSC 0.0315 BSC
θ °0 °8 °0 °8
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 13/14
Revision History
Revision Date Description
1.0 2007.05.11 Original
1.1 2008.02.29 1. Add 44-pin TSOPII package
2. Add Avoid timing
1.2 2008.07.04
1. Move Revision History to the last
2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V
3. Add Industrial grade
ESMT
M24L216128SA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008
Revision : 1.2 14/14
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
