SN65HVD62 www.ti.com SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 AISG On-Off Keying Coax Modem Transceiver Check for Samples: SN65HVD62 FEATURES DESCRIPTION * * * These transceivers modulate and demodulate signals between the logic (baseband) and a frequency suitable for long coaxial media. 1 * * * * * * * Supply Ranging From 3V to 5.5V Independent Logic Supply of 1.6V to 5.5V Wide Input Dynamic Range of -15dBm to +5dBm for Receiver Power Delivered by the Driver to the Coax can be Adjusted From 0dBm to +6dBm AISG Compliant Output Emission Profile Low-power Standby Mode Direction Control Output for RS-485 Bus Arbitration Supports up to 115 kbps Signaling Integrated Active Bandpass Filter with Center Frequency at 2.176MHz 3mm x 3mm 16-Pin QFN Package APPLICATIONS * * * AISG - Interface for Antenna Line Devices Tower Mounted Amplifiers (TMA) General Modem Interfaces The HVD62 is an integrated AISG transceiver designed to be compliant with Antenna Interface Standards Group v2.0 specification. The HVD62 receiver integrates an active bandpass filter to enable demodulation of signals even in the presence of spurious frequency components. The filter has a 2.176 MHz center frequency. The transmitter supports adjustable output power levels varying from +0dBm to +6dBm delivered to the 50 coax cable. The HVD62 transmitter is compliant with the spectrum emission requirement provided by the AISG standard. A direction control output is provided which facilitates bus arbitration for an RS-485 interface. These devices integrate an oscillator input for a crystal, and also accept standard clock inputs to the oscillator. Vcc 13 VL 3 1 9 XTAL1 14 XTAL2 15 TXIN DIRSET1 DIRSET2 DIR RXOUT FILTER OOK MOD XTAL Buffer OUTPUT STAGE PREAMP 12 SYNCOUT RES TXOUT 2.176 2 7 6 Control Logic 5 FILTER OOK DEMOD 4 11 Buffer RXIN 2.176 Buffer COMP RECEIVER THRESHOLD 16 GND 8 GND 10 BIAS 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2013, Texas Instruments Incorporated SN65HVD62 SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. RES BIAS RXIN TXOUT PIN CONFIGURATION VCC GND XTAL1 DIRSET1 Exposed text Pad GND DIR VL TXIN RXOUT DIRSET2 SYNCOUT XTAL2 PIN FUNCTIONS PIN HVD62 PIN DESCRIPTION NAME 1 SYNCOUT Open drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1,2. (8.704 MHz for HVD62) 2 TXIN Digital data bit stream to driver. 3 VL Logic supply voltage for the device. 4 RXOUT Digital data bit stream from receiver. 5 DIR 6 DIRSET2 7 DIRSET1 DIR: Direction control output signal for bus arbitration. DIRSET1 and DIRSET2: Bits to set the duration of DIR DIRSET[2,1]:[L,L]=9.6kbps [L,H]=38.4kbps [H,L]=115kbps [H,H]=Standby Mode 8 GND Ground 9 RES Input voltage to adjust driver output power. Set by external resistors from BIAS pin to GND. 10 BIAS Bias voltage output for setting driver output power by external resistors. 11 RXIN Modulated input signal to the receiver. 12 TXOUT Modulated output signal from the driver. 13 VCC Analog supply voltage for the device. 14 XTAL1 15 XTAL2 Crystal oscillator's IO pins. Connect a 4 x fC crystal between these pins. Or connect XTAL1 to an 8.704 MHz clock and connect XTAL2 to GND. 16 GND Ground EP Exposed pad. Recommended to be connected to ground plane for best thermal conduction. - Table 1. DRIVER FUNCTION TABLE (1) TXIN H L [DIRSET1, DIRSET2] [L,L], [L,H] or [H,L] X (1) 2 [H,H] TXOUT < 1 mVPP at 2.176 MHz VOPP at 2.176 MHz < 1 mVPP at 2.176 MHz COMMENT Driver not active Driver active Standby mode H = High, L = Low, X = Indeterminate Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 Table 2. RECEIVER and DIR FUNCTION TABLE (1) RXIN RXOUT DIR COMMENT (see Figure 22) H L No outgoing or incoming signal < VIT at 2.176 MHz for less than tDIR Timeout H H Incoming '1' bit, DIR stays HIGH for DIR Timeout > VIT at 2.176 MHz for longer than tnoise filter L H Incoming '0' bit, DIR output is HIGH H L Outgoing message, DIR stays LOW for DIR Timeout IDLE mode (not transmitting or receiving) < VIT at 2.176 MHz for longer than DIR timeout RECEIVE mode (not already transmitting) TRANSMIT mode (not already receiving) X (1) H = High, L = Low ABSOLUTE MAXIMUM RATINGS (1) VALUES UNITS MIN MAX Supply voltage, VCC and VL -0.5 6 V Voltage range at coax pins -0.5 6 V Voltage range at logic pins -0.3 VL + 0.3 V 2 kV 20 mA Electrostatic Discharge, Human Body Model (EIA/JESD 22-A114) Logic Output Current -20 TXOUT output current Internally limited SYNCOUT output current Internally limited Junction Temperature, TJ 170 Continuous total power dissipation (1) C See the Thermal Table Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION SN65HVD62 THERMAL METRIC (1) QFN UNITS (16) PINS JA Junction-to-ambient thermal resistance 49.4 JCtop Junction-to-case (top) thermal resistance 64.2 JB Junction-to-board thermal resistance 22.9 JT Junction-to-top characterization parameter 1.7 JB Junction-to-board characterization parameter 22.9 JCbot Junction-to-case (bottom) thermal resistance TSTG Storage temperature (1) C/W 25.0 -65 to 150 C For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 3 SN65HVD62 SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VCC Analog supply voltage VL Logic supply voltage VI(pp) Input signal amplitude at RXIN VIH High-level input voltage VIL Low-level input voltage 1/tUI Data signaling rate FOSC Oscillator frequency TA Operating free-air temperature -40 85 C TJ Junction Temperature -40 125 C TXIN, DIRSET1, DIRSET2 3 5.5 1.6 5.5 V 1.12 Vpp 70%VL VL 70%VCC VCC TXIN, DIRSET1, DIRSET2 0 30%VL XTAL1, XTAL2 0 30%VCC XTAL1, XTAL2 9.6 HVD62 -30 ppm 8.704 V V V 115 kbps 30 ppm MHz Load impedance between TXOUT to RXIN 50 Load impedance between RXIN and GND at fC (channel) 50 R1 Bias resistor between BIAS and RES 4.1 k R2 Bias resistor between RES and GND 10 k RSYNC Pull-up resistor between SYNCOUT and VCC 1 k VRES Voltage at RES pin CC Coupling capacitance between RXIN and Coax (channel) CBIAS Capacitance between BIAS and GND RLOAD 4 0.7 Submit Documentation Feedback 1.5 V 220 nF 1 F Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 28 33 25 31 27 33 12 17 UNIT POWER SUPPLY 100 TXIN = L (Active) 101 TXIN = H (Quiescent) ICC Supply current (VCC) 103 IL Logic supply current TXIN = H, RXIN = DC input 104 VRXIN/ VCC Receiver power supply rejection ratio VTXIN = VL 102 TXIN = 115 kbps, 50% duty cycle 99 DIRSET1 = L DIRSET2 = H (Standby) DIRSET1 = DIRSET2=H 50 45 60 mA A dB LOGIC PINS 112 VOH High-level logic output voltage (RXOUT, DIR) IOH = -4 mA for VL > 2.4V, IOH = -2 mA for VL < 2.4V 113 VOL Low-level logic output voltage (RXOUT, DIR) IOL = 4 mA for VL > 2.4V, IOL = 2 mA for VL < 2.4V 114 IIH/IIL Logic input current (DIRSET1/2) IIH/IIL Logic input current (TXIN) 90%VL V 10%VL V -1 10 A -2 1 A COAX DRIVER 130 132 130A 132A 134 134A VOPP Peak-to-peak output voltage at device pin TXOUT (See Figure 1) VRES = 1.5 V (Maximum setting) VOPP Peak-to-peak voltage at coax out (See Figure 1) VRES = 1.5 V VOZ Off-state output voltage 136 41 fo Output frequency (HVD62) f Output frequency variation 143 144 145 2.5 1.17 5 VRES = 0.7 V At coax out Coupled to coaxial cable with characteristic impedance 50 Ohms, as shown in Figure 1. With a recommended 470 pF capacitor between RXIN and GND. Measurements above 150 MHz are determined by setup. 1.3 6 -0.6 At TXOUT Output emissions 142 2.24 VRES = 0.7 V (Minimum setting) 0.3 VPP dBm 1 mVpp -60 dBm Conforms to AISG spectrum emissions mask, 3GPP TS 25.461, see Figure 3 2.176 -100 MHz 100 ppm At 100 kHz 0.03 At 10 MHz 3.5 Short-circuit output current TXOUT is also protected by a thermal shutdown circuit during short-circuit faults 300 450 mA VIT Input threshold fIN = 2.176 MHz ZIN Input impedance Zo Output impedance | IOS | COAX RECEIVER 152 152A 154 79 112 158 mVPP -18 -15 -12 dBm f = fO 11 21 Passband VRXIN = 1.12VP_P 1.1 4.17 MHz Receiver rejection range 2.176MHz carrier amplitude of 112.4 mVPP, Frequency band of spurious components with 800 mVPP allowed. 1.1 4.17 MHz Receiver noise filter time (slow bit rate) DIRSET for 9.6kbps 4 Receiver noise filter time (fast bit rate) DIRSET for > 9.6 kbps 2 Input leakage current XTAL1, XTAL2, 0V < VIN < VCC Output low voltage SYNCOUT, with 1 k resistor from SYNCOUT to VCC k RECEIVER FILTER 160 161 162 163 fPB fREJ tnoise filter s XTAL AND SYNC 171 172 II VOL -15 15 A 0.4 V Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 5 SN65HVD62 SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tpAQ, tpQA Coax driver propagation delay See Figure 1 202 tr, tf Coax receiver output rise/fall time CL = 15 pF, RL = 1 k, See Figure 1 203 tPHL, tPLH Receiver propagation delay See Figure 2 204 Duty Cycle Coax receiver output duty cycle 201 214 206 207 Direction control active duration 209 tDIR Skew Direction control skew (DIR to RXOUT) 210 tDIS Standby disable delay 211 tEN Standby enable delay TYP 5.5 MAX s 20 ns 11 s 40% 60% VRXIN(ON) = 200 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle 40% 60% 1667 DIRSET2 = GND, DIRSET1 = VL 417 DIRSET2 = VL, DIRSET1 = VL 137 270 300 mVPP at 2.176 MHz on RXIN Submit Documentation Feedback UNIT 5 VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle DIRSET2 = DIRSET1 = GND or OPEN tDIR 208 6 MIN s ns 2 2 ms Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 PARAMETER MEASUREMENT INFORMATION Signal generator rate is 115 kbps, 50% duty cycle, rise and fall times less than 6 nsec, nominal output levels 0V and 3V. Coupling capacitor Cc is 220 nF. Driver Amplitude Adjust RAMP XTAL2 2.176 MHz Crystal RES TXOUT TXIN 50 W XTAL2 Signal generator Coax Out 50 W Cc RXIN VL 0.5 VL TXIN tpQA tpAQ Vpk 0.5 Vpk TXOUT Figure 1. Measurement of Modem Driver Output Voltage With 50 Loads Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 7 SN65HVD62 SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) TXOUT 50 2.176 MHz Signal Coax In Received Data Out Cc RXIN Direction Control Vpk 0.5 VL RXIN VL 0.5 VL RXOUT tPHL tPLH VL 0.5 VL DIR tDIRSKEW Figure 2. Measurement of Modem Receiver Propagation Delays 8 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 Emissions spectrum with 50% duty cycle OOK and VRES=1.5V conforms to TS 25.461 10 2.276, 5 2.076, 5 0 2.376, -5 Emissions (dBm) with OOK and VRES=1.5V 1.976, -5 -10 -20 2.676, -25 1.676, -25 -30 10, -36 1, -36 20, -36 -40 -50 -60 30, -67 -70 0.1 1 10 100 Frequency (MHz) Figure 3. AISG Emissions Template TYPICAL CHARACTERISTICS 10 60 AISG Mask 50% Duty Cycle CF = 470pF 70 10 TRANSMITTER OUTPUT (dBm) TRANSMITTER OUTPUT (dBm) 0 20 AISG Mask 30 40 50 50% Duty Cycle CF = 470pF 80 90 100 60 110 70 80 120 0 10M 20M FREQUENCY (Hz) 30M 30M 130M 230M FREQUENCY (Hz) 330M C00 Figure 4. Low Frequency Emissions Spectrum with 9.6 kbps Signaling Rate C00 Figure 5. High Frequency Emissions Spectrum with 9.6 kbps Signaling Rate Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 9 SN65HVD62 SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 10 60 AISG Mask 50% Duty Cycle cF = 470 pF 0 70 TRANSMITTER OUTPUT (dBm) TRANSMITTER OUTPUT (dBm) 10 20 AISG Mask 30 40 50 50% Duty Cycle CF = 470pF 80 90 100 60 110 70 80 120 0 10M 20M FREQUENCY (Hz) 30M 30M 130M 230M FREQUENCY (Hz) 330M C00 C00 Figure 6. Low Frequency Emissions Spectrum with 38.4 kbps Signaling Rate Figure 7. High Frequency Emissions Spectrum with 38.4 kbps Signaling Rate 10 60 AISG Mask 50% Duty cycle cF = 470 pF 70 10 TRANSMITTER OUTPUT (dBm) TRANSMITTER OUTPUT (dBm) 0 20 AISG Mask 30 40 50 50% Duty Cycle CF = 470pF 80 90 100 60 110 70 120 80 0 10M 20M FREQUENCY (Hz) 30M 30M 230M 330M FREQUENCY (Hz) C00 C00 Figure 8. Low Frequency Emissions Spectrum with 115.2 kbps Signaling Rate 10 130M Figure 9. High Frequency Emissions Spectrum with 115.2 kbps Signaling Rate Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 6 35 5 30 4 TRANSMITTER OUTPUT (dBm) TRANSMITTER OUTPUT IMPEDANCE (Y) TYPICAL CHARACTERISTICS (continued) 40 25 20 15 10 5 3 2 1 0 1 0 2 0.1M 1M 10M FREQUENCY (Hz) 0.7 0.9 1.1 VRES (V) 1.3 1.5 C00 C00 Figure 10. Transmitter Output Impedance Figure 11. Transmit Power Adjustment 13 27 26.5 12.8 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) TXIN = VL 12.9 TXIN = VL 26 25.5 25 12.7 12.6 12.5 12.4 12.3 12.2 24.5 12.1 24 12 3 3.5 4 4.5 5 5.5 3 SUPPLY VOLTAGE (V) 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) C00 Figure 12. Supply Current versus Supply Voltage while Transmitting C00 Figure 13. Supply Current versus Supply Voltage in Standby Mode Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 11 SN65HVD62 SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 7 13.2 6 13 TRANSMITTER OUTPUT (dBm) QUIESCENT CURRENT (mA) 13.1 12.9 12.8 12.7 12.6 5 4 3 2 12.5 1 12.4 -40 -10 20 50 80 110 TEMPERATURE (OC) 0 3 C00 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) C00 Figure 14. Supply Current versus Temperature in Standby Mode Figure 15. Transmitter Output Power versus Supply Voltage 30k 7 25k RECEIVER INPUT IMPEDANCE (Y) TRANSMITTER OUTPUT (dBm) 6 5 4 3 2 20k 15k 10k 5k 1 0 0 -40 -10 20 50 80 100 110 TEMPERATURE (OC) 10k 100k 1M 5M FREQUENCY (Hz) C00 Figure 16. Transmitter Output Power versus Temperature 12 1k C00 Figure 17. Receiver Input Impedance versus Frequency Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 TYPICAL CHARACTERISTICS (continued) 0.16 360 DIR RECEIVER OUTPUT DELAY (nS) RECEIVER IINPUT THRESHOLD (V) 0.15 0.14 0.13 RTXOUT=STABLE LOW 0.12 0.11 RXOUT=STABLE HIGH 0.1 355 350 345 0.09 0.08 340 -40 -10 20 50 80 110 -40 -10 TEMPERATURE (OC) 20 50 80 110 TEMPERATURE (OC) C00 C00 Figure 18. Receiver Input Threshold versus Temperature Figure 19. DIR Output Delay versus Temperature 60 RECEIVER OUTPUT DUTYCYCLE (%) RECEIVER OUTPUT DUTYCYCLE (%) 60 56 52 48 44 40 50 40 30 20 10 0 -10 -7 -4 -1 2 5 -10 RECEIVER INPUT (dBm) -7 -4 -1 2 5 RECEIVER INPUT (dBm) C00 Figure 20. Receiver Duty Cycle with 9.6 kbps Signaling Rate C00 Figure 21. Receiver Duty Cycle with 115.2 kbps Signaling Rate Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 13 SN65HVD62 SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 www.ti.com APPLICATION INFORMATION Driver Amplitude Adjust The SN65HVD62 can provide up to 2.5 V peak-to-peak of output signal at the TXOUT pin to compensate for potential loss within the external filter, cable, connections, and termination. External resistors are used to set the amplitude of the modulated driver output signal. Resistors connected across RES and BIAS set the output amplitude. The maximum peak-to-peak voltage at TXOUT is 2.5 V, corresponding to +6 dBm on the coaxial cable. The TXOUT voltage level can be adjusted by choice of resistors to set the voltage at the RES pin. according to the following equation: VTXOUT (VP-P) = (2.5 VP-P x VRES (V))/1.5 V VRES (V) = 1.5 V x R2/(R1 + R2) VTXOUT (VP-P) = 2.5 VP-P x R2/(R1 + R2). (1) The voltage at the RES pin should be between 0.7 V and 1.5 V. Connect RES directly to the BIAS (R1 = 0 ) for maximum output level of 2.5 V peak-to-peak. This gives a minimum voltage level at TXOUT of 1.2 V peak-topeak, corresponding to about 0 dBm at the coaxial cable. A 1 F capacitor should be connected between the BIAS pin and GND. To obtain a nominal power level of +3 dBm at the feeder cable as the AISG standard requires, use R1 = 4.1k and R2 = 10k that provide 1.78 VP-P at TXOUT. Direction Control In many applications the mast-top modem which receives data from the base will then distribute the received data through an RS-485 network to several mast-top devices. When the mast-top modem receives the first logic 0 bit (active modulated signal) it will take control of the mast-top RS-485 network by asserting the Direction Control signal. The duration of the Direction Control assertion should be optimized to pass a complete message of length B bits at the known signaling rate (1/tBIT) before relinquishing control of the mast-top RS-485 network. For example, if the messages are 10 bits in length (B=10) and the signaling rate is 9600 bits per second (tBIT = 0.104 msec) then a positive pulse of duration 1.7 msec is sufficient (with margin to allow for network propagation delays) to enable the mast-top RS-485 drivers to distribute each received message. Coax In Data Out Direction DIRECTION Control Time Constant The time constant for the Direction Control function can be set by the Control Mode pins, DIRSET1/DIRSET2. These pins should be set to correspond to the desired data rate. With no external connections to the Control Mode pins, the internal time constant is set to the maximum value, corresponding to the minimum data rate. Conversion Between dBm and Peak-to-peak Voltage dBm = 20 x LOG10 [Volts-pp / SQRT(0.008 x Zo)] = 20 x LOG10 [Volts-pp / 0.63] for Zo = 50 Volts-pp = SQRT(0.008 x Zo) x 10(dBm/20) = 0.63 x 10(dBm/20) for Zo = 50 (2) (3) The following table shows conversions between dBm and peak-to-peak voltage with 50 load, for various levels of interest including reference levels from the 3GPP TS 25.461 Technical Specification. SIGNAL ON COAX (Iuant Layer 1) dBm Vpp (V) Maximum Driver ON Signal 5 1.12 Nominal Driver ON Signal 3 0.89 Minimum Driver ON Signal 14 1 0.71 AISG Maximum Receiver Threshold -12 0.16 Nominal Receiver Threshold -15 0.11 Minimum Receiver Threshold -18 0.08 Maximum Driver OFF Signal -40 0.006 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 SN65HVD62 www.ti.com SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 States of Operation If DIRSET1 and DIRSET2 are in a logic High state, the device will be in STANDBY mode. While in STANDBY mode, the Receiver functions normally, detecting carrier frequency activity on the RXIN pin and setting the RXOUT state as discussed below. But the Transmitter circuits are not active in STANDBY, thus the TXOUT pin is idle regardless of the logic state of TXIN. The supply current in STANDBY mode is significantly reduced, allowing power savings when the node is not transmitting. When not in STANDBY mode, the default power-on state is IDLE. When in IDLE mode, RXOUT is High, and TXOUT is quiet. The device transitions to RECEIVE mode when a valid modulated signal is detected on the RXIN line <OR> the device transitions to TRANSMIT mode when TXIN goes Low. The device stays in either RECEIVE or TRANSMIT mode until DIR Timeout (nominal 16 bit times) after the last activity on RXOUT or TXIN. When in RECEIVE mode: * RXOUT responds to all valid modulated signals on RXIN, whether from the local transmitter, a remote transmitter, or long noise burst. * TXOUT responds to TXIN, generating 2.176 MHz signals on TXOUT when TXIN is Low, and TXOUT is quiet when TXIN is High. (In normal operation, TXIN is expected to remain High when the device is in RECEIVE mode). * The device stays in RECEIVE mode until 16 bit times after the last rising edge on RXOUT, caused by valid modulated signal on the RXIN line. When in TRANSMIT mode: * RXOUT stays High, regardless of the input signal on RXIN. * TXOUT responds to TXIN, generating 2.176 MHz signals on TXOUT when TXIN is Low, and TXOUT is quiet when TXIN is High. * The device stays in TRANSMIT mode until 16 bit times after TXIN goes High. Transmit 0 RXIN 9 TXOUT=Active DIR = L Receive 0 RXOUT = L DIR = H TXIN ; IDLE TXIN 9 RXOUT = H TXOUT=Idle DIR = L TXIN ; Transmit 1 RXIN 9 RXIN ; Receive 1 DIR Timeout TXOUT=Idle DIR = L DIR Timeout RXOUT = H DIR = H Figure 22. State Transition Diagram Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 15 SN65HVD62 SLLSE94B - SEPTEMBER 2011 - REVISED JANUARY 2013 www.ti.com REVISION HISTORY Changes from Original (September 2011) to Revision A Page * Changed Pin 4 label (lower right) in the PIN CONFIGURATION diagram from TXIN to RXOUT ........................................ 2 * Changed the PIN FUNCTIONS table by merging the DESCRIPTION cells for pins 5, 6, and 7 and deleted the word DIRSET from the beginning of the second line in that description field. .............................................................................. 2 * Added 3 FUNCTIONAL TABLES (DRIVER, RECEIVER, AND DIR) under the PIN FUNCTIONS ...................................... 2 * Added rows 162 and 163 to the ELEC CHARACTERISTICS table, under RECEIVER FILTER section ............................ 5 * Added rows 210 and 211 to the SWITCH CHARACTERISTICS table ................................................................................ 6 * Added Figure 22 State Transition Diagram ........................................................................................................................ 15 Changes from Revision A (January 2012) to Revision B Page * Changed Feature From: "Power Delivered by the Driver to the Coax can be Adjusted +3dBm to +6dBm" To: "Power Delivered by the Driver to the Coax can be Adjusted 0dBm to +6dBm" .............................................................................. 1 * Added Storage temperature to the Thermal Table ............................................................................................................... 3 * Change the MIN value of VRES in the ROC table From: 0.84 To: 0.7 V ............................................................................... 4 * Change the TYP value of CC in the ROC table From: 270 To: 220 nF ................................................................................ 4 * Changed the ELECTRICAL CHARACTERISTICS ............................................................................................................... 5 * Changed the SWITCHING CHARACTERISTICS ................................................................................................................. 6 * Changed the PARAMETER MEASUREMENT INFORMATION ........................................................................................... 7 * Added the TYPICAL CHARACTERISTICS section .............................................................................................................. 9 * Changed the APPLICATION INFORMATION section ........................................................................................................ 14 16 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: SN65HVD62 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) SN65HVD62RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 HVD62 SN65HVD62RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 HVD62 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65HVD62RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 SN65HVD62RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD62RGTR QFN RGT 16 3000 367.0 367.0 35.0 SN65HVD62RGTT QFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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