XTAL
Buffer
OUTPUT
STAGE
Buffer
OOK
DEMOD
RES
XTAL1
TXIN
RXOUT
TXOUT
VL
GND
Buffer
OOK
MOD PREAMP
FILTER
Control
Logic
COMP
2.176
FILTER
2.176
SYNCOUT
RXIN
DIR
DIRSET1
RECEIVER
THRESHOLD
14
15
2
7
6
5
4
16
11
3
12
9
1
13
810
BIAS
GND
Vcc
XTAL2
DIRSET2
SN65HVD62
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SLLSE94B –SEPTEMBER 2011–REVISED JANUARY 2013
AISG On-Off Keying Coax Modem Transceiver
Check for Samples: SN65HVD62
1FEATURES DESCRIPTION
These transceivers modulate and demodulate signals
• Supply Ranging From 3V to 5.5V between the logic (baseband) and a frequency
• Independent Logic Supply of 1.6V to 5.5V suitable for long coaxial media.
• Wide Input Dynamic Range of –15dBm to The HVD62 is an integrated AISG transceiver
+5dBm for Receiver designed to be compliant with Antenna Interface
• Power Delivered by the Driver to the Coax can Standards Group v2.0 specification.
be Adjusted From 0dBm to +6dBm The HVD62 receiver integrates an active bandpass
• AISG Compliant Output Emission Profile filter to enable demodulation of signals even in the
• Low-power Standby Mode presence of spurious frequency components. The
filter has a 2.176 MHz center frequency.
• Direction Control Output for RS-485 Bus
Arbitration The transmitter supports adjustable output power
levels varying from +0dBm to +6dBm delivered to the
• Supports up to 115 kbps Signaling 50 Ωcoax cable. The HVD62 transmitter is compliant
• Integrated Active Bandpass Filter with Center with the spectrum emission requirement provided by
Frequency at 2.176MHz the AISG standard.
• 3mm × 3mm 16-Pin QFN Package A direction control output is provided which facilitates
bus arbitration for an RS-485 interface. These
APPLICATIONS devices integrate an oscillator input for a crystal, and
• AISG – Interface for Antenna Line Devices also accept standard clock inputs to the oscillator.
• Tower Mounted Amplifiers (TMA)
• General Modem Interfaces
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
text
Exposed
Pad
DIR
DIRSET2
DIRSET1
GNDVCC
XTAL1
XTAL2
GND
TXOUT
RXIN
BIAS
RES
SYNCOUT
TXIN
VL
RXOUT
SN65HVD62
SLLSE94B –SEPTEMBER 2011–REVISED JANUARY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN CONFIGURATION
PIN FUNCTIONS
HVD62 PIN
PIN DESCRIPTION
NAME
1 SYNCOUT Open drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1,2. (8.704 MHz for HVD62)
2 TXIN Digital data bit stream to driver.
3 VL Logic supply voltage for the device.
4 RXOUT Digital data bit stream from receiver.
5 DIR DIR: Direction control output signal for bus arbitration.
DIRSET1 and DIRSET2: Bits to set the duration of DIR
6 DIRSET2 DIRSET[2,1]:[L,L]=9.6kbps [L,H]=38.4kbps [H,L]=115kbps [H,H]=Standby Mode
7 DIRSET1
8 GND Ground
9 RES Input voltage to adjust driver output power. Set by external resistors from BIAS pin to GND.
10 BIAS Bias voltage output for setting driver output power by external resistors.
11 RXIN Modulated input signal to the receiver.
12 TXOUT Modulated output signal from the driver.
13 VCC Analog supply voltage for the device.
14 XTAL1 Crystal oscillator’s IO pins. Connect a 4 x fCcrystal between these pins. Or connect XTAL1 to an 8.704 MHz
clock and connect XTAL2 to GND.
15 XTAL2
16 GND Ground
- EP Exposed pad. Recommended to be connected to ground plane for best thermal conduction.
Table 1. DRIVER FUNCTION TABLE(1)
TXIN [DIRSET1, DIRSET2] TXOUT COMMENT
H < 1 mVPP at 2.176 MHz Driver not active
[L,L], [L,H] or [H,L]
L VOPP at 2.176 MHz Driver active
X [H,H] < 1 mVPP at 2.176 MHz Standby mode
(1) H = High, L = Low, X = Indeterminate
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Table 2. RECEIVER and DIR FUNCTION TABLE(1)
RXIN RXOUT DIR COMMENT (see Figure 22)
IDLE mode (not transmitting or receiving)
< VIT at 2.176 MHz for longer than DIR H L No outgoing or incoming signal
timeout
RECEIVE mode (not already transmitting)
< VIT at 2.176 MHz for less than tDIR Timeout H H Incoming '1' bit, DIR stays HIGH for DIR Timeout
> VIT at 2.176 MHz for longer than tnoise filter L H Incoming '0' bit, DIR output is HIGH
TRANSMIT mode (not already receiving)
X H L Outgoing message, DIR stays LOW for DIR Timeout
(1) H = High, L = Low
ABSOLUTE MAXIMUM RATINGS(1)
VALUES UNITS
MIN MAX
Supply voltage, VCC and VL–0.5 6 V
Voltage range at coax pins –0.5 6 V
Voltage range at logic pins –0.3 VL+ 0.3 V
Electrostatic Discharge, Human Body Model (EIA/JESD 22-A114) ±2 kV
Logic Output Current –20 20 mA
TXOUT output current Internally limited
SYNCOUT output current Internally limited
Junction Temperature, TJ170 °C
Continuous total power dissipation See the Thermal Table
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION SN65HVD62
THERMAL METRIC(1) QFN UNITS
(16) PINS
θJA Junction-to-ambient thermal resistance 49.4
θJCtop Junction-to-case (top) thermal resistance 64.2
θJB Junction-to-board thermal resistance 22.9 °C/W
ψJT Junction-to-top characterization parameter 1.7
ψJB Junction-to-board characterization parameter 22.9
θJCbot Junction-to-case (bottom) thermal resistance 25.0
TSTG Storage temperature -65 to 150 °C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VCC Analog supply voltage 3 5.5 V
VLLogic supply voltage 1.6 5.5 V
VI(pp) Input signal amplitude at RXIN 1.12 Vpp
TXIN, DIRSET1, DIRSET2 70%VLVL
VIH High-level input voltage V
XTAL1, XTAL2 70%VCC VCC
TXIN, DIRSET1, DIRSET2 0 30%VL
VIL Low-level input voltage V
XTAL1, XTAL2 0 30%VCC
1/tUI Data signaling rate 9.6 115 kbps
FOSC Oscillator frequency HVD62 –30 ppm 8.704 30 ppm MHz
TAOperating free-air temperature –40 85 °C
TJJunction Temperature –40 125 °C
Load impedance between TXOUT to RXIN 50
RLOAD Ω
Load impedance between RXIN and GND at fC(channel) 50
R1 Bias resistor between BIAS and RES 4.1 kΩ
R2 Bias resistor between RES and GND 10 kΩ
RSYNC Pull-up resistor between SYNCOUT and VCC 1 kΩ
VRES Voltage at RES pin 0.7 1.5 V
CCCoupling capacitance between RXIN and Coax (channel) 220 nF
CBIAS Capacitance between BIAS and GND 1 µF
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
100 TXIN = L (Active) 28 33
101 TXIN = H (Quiescent) DIRSET1 = L 25 31
DIRSET2 = H
ICC Supply current (VCC) mA
TXIN = 115 kbps,
102 27 33
50% duty cycle
99 (Standby) DIRSET1 = DIRSET2=H 12 17
103 ILLogic supply current TXIN = H, RXIN = DC input 50 µA
ΔVRXIN/
104 Receiver power supply rejection ratio VTXIN = VL45 60 dB
ΔVCC
LOGIC PINS
High-level logic output voltage IOH = –4 mA for VL> 2.4V,
112 VOH 90%VLV
(RXOUT, DIR) IOH = –2 mA for VL< 2.4V
Low-level logic output voltage IOL = 4 mA for VL> 2.4V,
113 VOL 10%VLV
(RXOUT, DIR) IOL = 2 mA for VL< 2.4V
114 IIH/IIL Logic input current (DIRSET1/2) -1 10 µA
IIH/IIL Logic input current (TXIN) -2 1 µA
COAX DRIVER
130 VRES = 1.5 V (Maximum setting) 2.24 2.5
Peak-to-peak output voltage at device pin
VOPP VPP
TXOUT (See Figure 1)
132 VRES = 0.7 V (Minimum setting) 1.17 1.3
130A VRES = 1.5 V 5 6
Peak-to-peak voltage at coax out (See
VOPP dBm
Figure 1)
132A VRES = 0.7 V -0.6 0.3
134 At TXOUT 1 mVpp
VOZ Off-state output voltage
134A At coax out -60 dBm
Coupled to coaxial cable with characteristic Conforms to AISG
impedance 50 Ohms, as shown in Figure 1. With a spectrum emissions mask,
136 Output emissions recommended 470 pF capacitor between RXIN 3GPP TS 25.461, see
and GND. Measurements above 150 MHz are Figure 3
determined by setup.
41 fo Output frequency (HVD62) 2.176 MHz
142 ∆f Output frequency variation –100 100 ppm
143 At 100 kHz 0.03 Ω
Zo Output impedance
144 At 10 MHz 3.5 Ω
TXOUT is also protected by a thermal shutdown
145 | IOS | Short-circuit output current 300 450 mA
circuit during short-circuit faults
COAX RECEIVER
152 79 112 158 mVPP
VIT Input threshold fIN = 2.176 MHz
152A –18 –15 –12 dBm
154 ZIN Input impedance f = fO11 21 kΩ
RECEIVER FILTER
160 fPB Passband VRXIN = 1.12VP_P 1.1 4.17 MHz
2.176MHz carrier amplitude of 112.4 mVPP,
161 fREJ Receiver rejection range Frequency band of spurious components with 800 1.1 4.17 MHz
mVPP allowed.
162 Receiver noise filter time (slow bit rate) DIRSET for 9.6kbps 4
tnoise filter µs
163 Receiver noise filter time (fast bit rate) DIRSET for > 9.6 kbps 2
XTAL AND SYNC
171 IIInput leakage current XTAL1, XTAL2, 0V < VIN < VCC –15 15 µA
SYNCOUT, with 1 kΩresistor from SYNCOUT to
172 VOL Output low voltage 0.4 V
VCC
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
201 tpAQ, tpQA Coax driver propagation delay See Figure 1 5 µs
Coax receiver output rise/fall
202 tr, tfCL= 15 pF, RL= 1 kΩ, See Figure 1 20 ns
time
203 tPHL, tPLH Receiver propagation delay See Figure 2 5.5 11 µs
VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5
204 Duty Cycle Coax receiver output duty cycle 40% 60%
mVpp, 50% duty cycle
VRXIN(ON) = 200 mVpp, VRXIN(OFF) < 5
214 40% 60%
mVpp, 50% duty cycle
206 DIRSET2 = DIRSET1 = GND or OPEN 1667
207 tDIR Direction control active duration DIRSET2 = GND, DIRSET1 = VL 417 µs
208 DIRSET2 = VL, DIRSET1 = VL 137
Direction control skew
209 tDIR Skew 270 ns
(DIR to RXOUT)
210 tDIS Standby disable delay 2
300 mVPP at 2.176 MHz on RXIN ms
211 tEN Standby enable delay 2
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Driver Amplitude
Adjust
TXIN
Coax
Out
2.176 MHz
Crystal
Signal
generator
Cc
TXOUT
RXIN
RES
XTAL2
XTAL2
RAMP
50 W
50 W
VL
0.5 VL
Vpk
0.5 Vpk
tpAQ
tpQA
TXIN
TXOUT
SN65HVD62
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SLLSE94B –SEPTEMBER 2011–REVISED JANUARY 2013
PARAMETER MEASUREMENT INFORMATION
Signal generator rate is 115 kbps, 50% duty cycle, rise and fall times less than 6 nsec, nominal output levels 0V
and 3V. Coupling capacitor Cc is 220 nF.
Figure 1. Measurement of Modem Driver Output Voltage With 50 ΩLoads
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Received
Data Out
Coax
In
Direction
Control
2.176 MHz
Signal
50
Cc
TXOUT
RXIN
RXIN
RXOUT
DIR
0.5 VL
Vpk
VL
0.5 VL
tPHL tPLH
VL
0.5 VL
tDIRSKEW
SN65HVD62
SLLSE94B –SEPTEMBER 2011–REVISED JANUARY 2013
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 2. Measurement of Modem Receiver Propagation Delays
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0
10M
20M
30M
±80
±70
±60
±50
±40
±30
±20
±10
10
TRANSMITTER OUTPUT (dBm)
FREQUENCY (Hz)
C00
50% Duty Cycle
CF = 470pF
AISG Mask
30M
130M
230M
330M
±120
±110
±100
±90
±80
±70
±60
TRANSMITTER OUTPUT (dBm)
FREQUENCY (Hz)
C00
AISG Mask
50% Duty Cycle
CF = 470pF
1, -36
1.676, -25
1.976, -5
2.076, 5 2.276, 5
2.376, -5
2.676, -25
10, -36 20, -36
30, -67
-70
-60
-50
-40
-30
-20
-10
0
10
0.1 1 10 100
Emissions (dBm) with OOK and VRES=1.5V
Frequency (MHz)
Emissions spectrum with 50% duty cycle OOK and VRES=1.5V
conforms to TS 25.461
SN65HVD62
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SLLSE94B –SEPTEMBER 2011–REVISED JANUARY 2013
Figure 3. AISG Emissions Template
TYPICAL CHARACTERISTICS
Figure 4. Low Frequency Emissions Spectrum with 9.6 kbps Figure 5. High Frequency Emissions Spectrum with 9.6
Signaling Rate kbps Signaling Rate
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0
10M
20M
30M
±80
±70
±60
±50
±40
±30
±20
±10
10
TRANSMITTER OUTPUT (dBm)
FREQUENCY (Hz)
C00
50% Duty cycle
cF = 470 pF
AISG Mask
30M
130M
230M
330M
±120
±110
±100
±90
±80
±70
±60
TRANSMITTER OUTPUT (dBm)
FREQUENCY (Hz)
C00
AISG Mask
50% Duty Cycle
CF = 470pF
0
10M
20M
30M
±80
±70
±60
±50
±40
±30
±20
±10
10
TRANSMITTER OUTPUT (dBm)
FREQUENCY (Hz)
C00
50% Duty Cycle
cF = 470 pF
AISG Mask
30M
130M
230M
330M
±120
±110
±100
±90
±80
±70
±60
TRANSMITTER OUTPUT (dBm)
FREQUENCY (Hz)
C00
AISG Mask
50% Duty Cycle
CF = 470pF
SN65HVD62
SLLSE94B –SEPTEMBER 2011–REVISED JANUARY 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 6. Low Frequency Emissions Spectrum with 38.4 Figure 7. High Frequency Emissions Spectrum with 38.4
kbps Signaling Rate kbps Signaling Rate
Figure 8. Low Frequency Emissions Spectrum with 115.2 Figure 9. High Frequency Emissions Spectrum with 115.2
kbps Signaling Rate kbps Signaling Rate
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24
24.5
25
25.5
26
26.5
27
3 3.5 4 4.5 5 5.5
QUIESCENT CURRENT (mA)
SUPPLY VOLTAGE (V)
C00
TXIN = VL
12
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
13
3 3.5 4 4.5 5 5.5
QUIESCENT CURRENT (mA)
SUPPLY VOLTAGE (V)
C00
TXIN = VL
0.1M
1M
10M
10
15
20
25
30
35
40
TRANSMITTER OUTPUT IMPEDANCE (Ÿ)
FREQUENCY (Hz)
C00
0.7
0.9
1.1
1.3
1.5
±2
±1
TRANSMITTER OUTPUT (dBm)
VRES (V)
C00
SN65HVD62
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SLLSE94B –SEPTEMBER 2011–REVISED JANUARY 2013
TYPICAL CHARACTERISTICS (continued)
Figure 10. Transmitter Output Impedance Figure 11. Transmit Power Adjustment
Figure 12. Supply Current versus Supply Voltage while Figure 13. Supply Current versus Supply Voltage in
Transmitting Standby Mode
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0
1
2
3
4
5
6
7
-40 -10 20 50 80 110
TRANSMITTER OUTPUT (dBm)
TEMPERATURE (OC)
C00
5M
0
5k
10k
15k
20k
25k
30k
100 1k 10k 100k 1M
RECEIVER INPUT IMPEDANCE (Ÿ)
FREQUENCY (Hz)
C00
0
1
2
3
4
5
6
7
3 3.5 4 4.5 5 5.5
TRANSMITTER OUTPUT (dBm)
SUPPLY VOLTAGE (V)
C00
12.4
12.5
12.6
12.7
12.8
12.9
13
13.1
13.2
-40 -10 20 50 80 110
QUIESCENT CURRENT (mA)
TEMPERATURE (OC)
C00
SN65HVD62
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www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 14. Supply Current versus Temperature in Standby Figure 15. Transmitter Output Power versus Supply Voltage
Mode
Figure 16. Transmitter Output Power versus Temperature Figure 17. Receiver Input Impedance versus Frequency
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40
44
48
52
56
60
-10 -7 -4 -1 2 5
RECEIVER OUTPUT DUTYCYCLE (%)
RECEIVER INPUT (dBm)
C00
0
10
20
30
40
50
60
-10 -7 -4 -1 2 5
RECEIVER OUTPUT DUTYCYCLE (%)
RECEIVER INPUT (dBm)
C00
0.08
0.09
0.1
0.11
0.12
0.13
0.14
0.15
0.16
-40 -10 20 50 80 110
RECEIVER IINPUT THRESHOLD (V)
TEMPERATURE (OC)
C00
RXOUT=STABLE HIGH
RTXOUT=STABLE LOW
340
345
350
355
360
-40 -10 20 50 80 110
DIR RECEIVER OUTPUT DELAY (nS)
TEMPERATURE (OC)
C00
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TYPICAL CHARACTERISTICS (continued)
Figure 18. Receiver Input Threshold versus Temperature Figure 19. DIR Output Delay versus Temperature
Figure 20. Receiver Duty Cycle with 9.6 kbps Signaling Rate Figure 21. Receiver Duty Cycle with 115.2 kbps Signaling
Rate
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Coax In
Data Out
Direction
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APPLICATION INFORMATION
Driver Amplitude Adjust
The SN65HVD62 can provide up to 2.5 V peak-to-peak of output signal at the TXOUT pin to compensate for
potential loss within the external filter, cable, connections, and termination. External resistors are used to set the
amplitude of the modulated driver output signal. Resistors connected across RES and BIAS set the output
amplitude. The maximum peak-to-peak voltage at TXOUT is 2.5 V, corresponding to +6 dBm on the coaxial
cable. The TXOUT voltage level can be adjusted by choice of resistors to set the voltage at the RES pin.
according to the following equation:
VTXOUT (VP-P) = (2.5 VP-P x VRES (V))/1.5 V VRES (V) = 1.5 V x R2/(R1 + R2) VTXOUT (VP-P) = 2.5 VP-P x R2/(R1 + R2). (1)
The voltage at the RES pin should be between 0.7 V and 1.5 V. Connect RES directly to the BIAS (R1 = 0 Ω) for
maximum output level of 2.5 V peak-to-peak. This gives a minimum voltage level at TXOUT of 1.2 V peak-to-
peak, corresponding to about 0 dBm at the coaxial cable. A 1 μF capacitor should be connected between the
BIAS pin and GND. To obtain a nominal power level of +3 dBm at the feeder cable as the AISG standard
requires, use R1 = 4.1k Ωand R2 = 10k Ωthat provide 1.78 VP-P at TXOUT.
Direction Control
In many applications the mast-top modem which receives data from the base will then distribute the received
data through an RS-485 network to several mast-top devices. When the mast-top modem receives the first logic
0 bit (active modulated signal) it will take control of the mast-top RS-485 network by asserting the Direction
Control signal. The duration of the Direction Control assertion should be optimized to pass a complete message
of length B bits at the known signaling rate (1/tBIT) before relinquishing control of the mast-top RS-485 network.
For example, if the messages are 10 bits in length (B=10) and the signaling rate is 9600 bits per second (tBIT =
0.104 msec) then a positive pulse of duration 1.7 msec is sufficient (with margin to allow for network propagation
delays) to enable the mast-top RS-485 drivers to distribute each received message.
DIRECTION Control Time Constant
The time constant for the Direction Control function can be set by the Control Mode pins, DIRSET1/DIRSET2.
These pins should be set to correspond to the desired data rate. With no external connections to the Control
Mode pins, the internal time constant is set to the maximum value, corresponding to the minimum data rate.
Conversion Between dBm and Peak-to-peak Voltage
dBm = 20 × LOG10 [Volts-pp / SQRT(0.008 × Zo)] = 20 × LOG10 [Volts-pp / 0.63] for Zo= 50 Ω(2)
Volts-pp = SQRT(0.008 × Zo) × 10(dBm/20) = 0.63 × 10(dBm/20) for Zo= 50 Ω(3)
The following table shows conversions between dBm and peak-to-peak voltage with 50 Ωload, for various levels
of interest including reference levels from the 3GPP TS 25.461 Technical Specification.
SIGNAL ON COAX (Iuant Layer 1) dBm Vpp (V)
Maximum Driver ON Signal 5 1.12
Nominal Driver ON Signal 3 0.89
Minimum Driver ON Signal 1 0.71
AISG Maximum Receiver Threshold –12 0.16
Nominal Receiver Threshold –15 0.11
Minimum Receiver Threshold –18 0.08
Maximum Driver OFF Signal –40 0.006
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IDLE
RXOUT = H
TXOUT=Idle
DIR = L
Transmit 0
TXOUT=Active
DIR = L
Receive 0
RXOUT = L
DIR = H
Receive 1
RXOUT = H
DIR = H
TXIN ;
TXIN 9
RXIN 9
DIR Timeout
RXIN ;
Transmit 1
TXOUT=Idle
DIR = L
TXIN ;
DIR Timeout
RXIN 9
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States of Operation
If DIRSET1 and DIRSET2 are in a logic High state, the device will be in STANDBY mode. While in STANDBY
mode, the Receiver functions normally, detecting carrier frequency activity on the RXIN pin and setting the
RXOUT state as discussed below. But the Transmitter circuits are not active in STANDBY, thus the TXOUT pin
is idle regardless of the logic state of TXIN. The supply current in STANDBY mode is significantly reduced,
allowing power savings when the node is not transmitting.
When not in STANDBY mode, the default power-on state is IDLE. When in IDLE mode, RXOUT is High, and
TXOUT is quiet. The device transitions to RECEIVE mode when a valid modulated signal is detected on the
RXIN line <OR> the device transitions to TRANSMIT mode when TXIN goes Low. The device stays in either
RECEIVE or TRANSMIT mode until DIR Timeout (nominal 16 bit times) after the last activity on RXOUT or TXIN.
When in RECEIVE mode:
• RXOUT responds to all valid modulated signals on RXIN, whether from the local transmitter, a remote
transmitter, or long noise burst.
• TXOUT responds to TXIN, generating 2.176 MHz signals on TXOUT when TXIN is Low, and TXOUT is quiet
when TXIN is High. (In normal operation, TXIN is expected to remain High when the device is in RECEIVE
mode).
• The device stays in RECEIVE mode until 16 bit times after the last rising edge on RXOUT, caused by valid
modulated signal on the RXIN line.
When in TRANSMIT mode:
• RXOUT stays High, regardless of the input signal on RXIN.
• TXOUT responds to TXIN, generating 2.176 MHz signals on TXOUT when TXIN is Low, and TXOUT is quiet
when TXIN is High.
• The device stays in TRANSMIT mode until 16 bit times after TXIN goes High.
Figure 22. State Transition Diagram
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: SN65HVD62
SN65HVD62
SLLSE94B –SEPTEMBER 2011–REVISED JANUARY 2013
www.ti.com
REVISION HISTORY
Changes from Original (September 2011) to Revision A Page
• Changed Pin 4 label (lower right) in the PIN CONFIGURATION diagram from TXIN to RXOUT ........................................ 2
• Changed the PIN FUNCTIONS table by merging the DESCRIPTION cells for pins 5, 6, and 7 and deleted the word
DIRSET from the beginning of the second line in that description field. .............................................................................. 2
• Added 3 FUNCTIONAL TABLES (DRIVER, RECEIVER, AND DIR) under the PIN FUNCTIONS ...................................... 2
• Added rows 162 and 163 to the ELEC CHARACTERISTICS table, under RECEIVER FILTER section ............................ 5
• Added rows 210 and 211 to the SWITCH CHARACTERISTICS table ................................................................................ 6
• Added Figure 22 State Transition Diagram ........................................................................................................................ 15
Changes from Revision A (January 2012) to Revision B Page
• Changed Feature From: "Power Delivered by the Driver to the Coax can be Adjusted +3dBm to +6dBm" To: "Power
Delivered by the Driver to the Coax can be Adjusted 0dBm to +6dBm" .............................................................................. 1
• Added Storage temperature to the Thermal Table ............................................................................................................... 3
• Change the MIN value of VRES in the ROC table From: 0.84 To: 0.7 V ............................................................................... 4
• Change the TYP value of CCin the ROC table From: 270 To: 220 nF ................................................................................ 4
• Changed the ELECTRICAL CHARACTERISTICS ............................................................................................................... 5
• Changed the SWITCHING CHARACTERISTICS ................................................................................................................. 6
• Changed the PARAMETER MEASUREMENT INFORMATION ........................................................................................... 7
• Added the TYPICAL CHARACTERISTICS section .............................................................................................................. 9
• Changed the APPLICATION INFORMATION section ........................................................................................................ 14
16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: SN65HVD62
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
SN65HVD62RGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 HVD62
SN65HVD62RGTT ACTIVE QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 HVD62
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD62RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
SN65HVD62RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Feb-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD62RGTR QFN RGT 16 3000 367.0 367.0 35.0
SN65HVD62RGTT QFN RGT 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Feb-2013
Pack Materials-Page 2
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