19-1072; Rev 2; 5/98 MIAAILM 4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 General Description The MAX1248/MAX1249 10-bit data-acquisition sys- tems combine a 4-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. They operate from a single +2.7V to +5.25V supply, and their analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPI QSPI and MICROWIRE devices without external logic. A serial strobe output allows direct connection to TMS320-family digital signal processors. The MAX1248/MAX1249 use either the internal clock or an external serial-interface clock to perform successive- approximation analog-to-digital conversions. The MAX1248 has an internal 2.5V reference, while the MAX1249 requires an external reference. Both parts have a reference-buffer amplifier with a +1.5% voltage adjustment range. These devices provide a hard-wired SHDN pin and a software-selectable power-down, and can be pro- grammed to automatically shut down at the end of a conversion. Accessing the serial interface automatically powers up the MAX1248/MAX1249, and the quick turn-on time allows them to be shut down between all conversions. This technique can cut supply current to under 60UA at reduced sampling rates. The MAX1248/MAX1249 are available in a 16-pin DIP and a very small QSOP that occupies the same board area as an 8-pin SO. For 8-channel versions of these devices, see the MAX148/MAX149 data sheet. Applications Data Acquisition Battery-Powered Instruments System Supervision Portable Data Logging Medical Instruments Pen Digitizers Pin Configuration appears at end of data sheet. SP! and QSP! are trademarks of Motorola, inc. MICROWIRE is a trademark of National Semiconductor Corp. MAXIM Features 4-Channel Single-Ended or 2-Channel Differential Inputs # Single +2.7V to +5.25V Operation Internal 2.5V Reference (MAX1248) @ Low Power: 1.2mA (133ksps, +3V supply) 54yA (1ksps, +3V supply) 1pA (power-down mode) # SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire Serial Interface @ Software-Configurable Unipolar or Bipolar Inputs # 16-Pin QSOP Package (same area as 8-pin SO) Ordering Information INL PART TEMP. RANGE PIN-PACKAGE (LSB) MAX1248ACPE 0Cto+70C =: 16 Plastic DIP +1/2 MAX1248BCPE O0C to+70C = 16 Plastic DIP +1 MAX1248ACEE OCto+70C 16 QSOP +1/2 MAX1248BCEE O0Cto+70C 16 QSOP +1 Ordering Information continued at end of data sheet. + Contact factory for availability of alternate surface-mount packages. Typical Operating Circuit 1 CHO V #_ Vop DD C3 oVTO DGND 0.1pF +2.5V MAXIM ANALOG INPUTS MAX1248 penn CPU \ Jos COM t$ -<# V0 SCLK SCK (SK) VREF ct Lt DIN MOS! (SO) ATF TO DOUT | MISO (SI) - ssTRB [EL REFADJ Veg SHON J 02 + O.0iuF | Maxim Integrated Products 1 For free samples & the latest literature: http:/www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 ABSOLUTE MAXIMUM RATINGS Vpp to AGND, DGND occ ete eeeneneneeneee -0.3V to +6V QSOP (derate 8.30MW/C above +70C) vo... cece 667mW AGND to DGND... eee eee eeneenenee -0.3V to +0.3V CERDIP (derate 10.00mW/C above +70C) ..... 800mW CHO-CH3, COM to AGND, DGND...... .. -0.3V to (Vpp + 0.3V) Operating Temperature Ranges VREF to AGND..... cece w 0.3V to (Vpp + 0.3V) MAX1248_C_E/MAX1249 C_E. eee 0C to +70C Digital Inputs to DGND wo... cee eneeneeeeee -0.3V to +6V MAX1248_ E E/MAX1249 E E Digital Outputs to DGND uu... ee -0.3V to (Vpp + 0.3V) MAX1248 MJE/MAX1249 MJE....eeeeeeee -65C to +125C Digital Output Sink CUrTent ..... cece ener eeeneereel 25mA Storage Temperature Range... -60C to +150C Continuous Power Dissipation (Ta, = +70C) Lead Temperature (soldering, 10SC) wo... eee eee +300C Plastic DIP (derate 10.53mW/C above +70C) ......... 842mWw Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vpp = +2.7V to +5.25V; COM = OV; fgcik = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX12484.7pF capacitor at VREF pin; MAX1249external reference, VREF = 2.500V applied to VREF pin; Ta = Tyin to Tax unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP = MAX | UNITS DC ACCURACY (Note 1) Resolution 10 Bits . MAX124 A +0.5 Relative Accuracy (Note 2) INL MAX124 B +10 LSB Differential Nonlinearity DNL No missing codes over temperature +1 LSB Offset Error MAX'24_A +1 LSB MAX124 B +2 Gain Error (Note 3) MAXt24_A +1 LSB MAX124 B +2 Gain Temperature Coefficient +0.25 ppm/C Mating Offset +0.05 LSB DYNAMIC SPECIFICATIONS (10kHz sine-wave input, OV to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode) Signal-to-Noise + Distortion Ratio | SINAD 66 dB Total Harmonic Distortion THD Up to the 5th harmonic -70 dB Spurious-Free Dynamic Range SFDR 70 dB Channel-to-Channel Crosstalk 65kHz, 2.500Vp-p (Note 4) -75 dB Small-Signal Bandwidth -3dB rolloff 2.25 MHz Full-Power Bandwidth 1.0 MHz CONVERSION RATE Internal clock, SHDN = FLOAT 5.5 7.5 Conversion Time (Note 5) tCONV Internal clock, SHDN = Vpp 35 65 ys External clock = 2MHz, 12 clocks/conversion 6 Track/Hold Acquisition Time taca 1.5 ys Aperture Delay 30 ns Aperture Jitter <50 ps Internal Clock Frequency SHDN = FLOAT 18 MHz SHDN = Vpp 0.225 0.1 2.0 External Clock Frequency Data transfer only 0 30 MHz 2 MAXUM4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 ELECTRICAL CHARACTERISTICS (continued) (Vop = +2.7V to +5.25V; COM = OV; fgciq = 2-0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX12484.7LF capacitor at VREF pin; MAX1249external reference, VREF = 2.500V applied to VREF pin; Ta = Twin to Tuax unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS ANALOG/COM INPUTS Input Voltage Range, Single- Unipolar, COM = OV 0 to VREF Vv Ended and Differential (Note 6) Bipolar, COM = VREF/2 +VREF /2 Multiplexer Leakage Current On/off leakage current, VcH_= OV or Vpp +0.01 +1 pA Input Capacitance 16 pF INTERNAL REFERENCE (MAX1248 only, reference buffer enabled) VREF Output Voltage Ta = +25C (Note 7) 2.470 2.500 2.530 Vv VREF Short-Circuit Current 30 mA VREF Temperature Coefficient MAX1248 +30 ppm/C Load Regulation (Note 8) OmA to 0.2mA output load 0.35 mV a: Internal compensation mode 0 Capacitive Bypass at VREF External compensation mode 47 HF Capacitive Bypass at REFADJ 0.01 HF REFADJ Adjustment Range 41.5 % EXTERNAL REFERENCE AT VREF (Buffer disabled) VREF Input Voltage Range Vbp + (Note 9) 1.0 somv | VREF Input Current VREF = 2.500V 100 150 pA VREF Input Resistance 18 25 kQ Shutdown VREF Input Current 0.01 10 pA REFADJ Buffer-Disable Threshold yop Vv EXTERNAL REFERENCE AT REFADJ a: Internal compensation mode 0 Capacitive Bypass at VREF External compensation mode 47 HF . MAX1248 2.06 Reference-Buffer Gain MAX1249 300 VV MAX1248 +50 REFADJ Input Current MAX1249 +10 pA DIGITAL INPUTS (DIN, SCLK, CS, SHDN) DIN, SCLK, CS Input High Voltage | Vin = = ~ V DIN, SCLK, CS Input Low Voltage VIL 0.8 Vv DIN, SCLK, CS Input Hysteresis VHYST 0.2 Vv DIN, SCLK, CS Input Leakage IIN VIN = OV or VoD +0.01 +1 pA DIN, SCLK, CS Input Capacitance CIN (Note 10) 15 pF SHDN Input High Voltage VSH Vop - 0.4 V SHDN Input Mid Voltage Vsm 1.1 Vop - 1.1 V SHDN Input Low Voltage VsL 0.4 V SHDN Input Current Is SHDN = OV or Vop +4.0 pA MAXIM 3 6VCLXVW/8I7CLXVWN4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 ELECTRICAL CHARACTERISTICS (continued) (Vop = +2.7V to +5.25V; COM = OV; fgci = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX12484.7)F capacitor at VREF pin; MAX1249external reference; VREF = 2.500V applied to VREF pin, Ta = Twin to Tax, unless otherwise noted.) MAX1248/MAX 1249 PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS SHDN Voltage, Floating VFLT SHDN = FLOAT Vpp/2 Vv SHDN Maximum Allowed SHDN = FLOAT +100 nA Leakage, Mid Input ~ ~ DIGITAL OUTPUTS (DOUT, SSTRB) ISINK = 5mA 0.4 Output Voltage Low VoL Vv IsINK = 16mA 0.8 Output Voltage High VOH ISOURCE = 0.5mA Vpp - 0.5 Vv Three-State Leakage Current IL CS =Vpp +0.01 +10 pA Three-State Output Capacitance Cout | CS = Vpp (Note 10) 15 pF POWER REQUIREMENTS Positive Supply Voltage Vppb 2.70 5.25 Vv Operating mode, VDD = 5.25V 1.6 3.0 : mA full-scale input (Note 11) Vpp = 3.6V 1.2 2.0 | Positive Supply Current pp Vop = 5.25V 3.5 15 Full power-down VbD = 3.6V 1.2 10 pA IDD Fast power-down (MAX1248) 30 70 as VbD = 2.7V to 5.25V, full-scale input, Supply Rejection (Note 12) PSR extarnal reference = 2.500V P +0.3 mV 4 MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 TIMING CHARACTERISTICS (Vpp = +2.7V to +5.25V, Ta = Twin to Tyax, unless otherwise noted.) 6VCLXVW/8I7CLXVWN PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS Acquisition Time tACQ 1.5 ys DIN to SCLK Setup tbs 100 ns DIN to SCLK Hold tDH 0 ns . . MAX124__ C/E 20 200 SCLK Fall to Output Data Valid tbo Figure 1 ns MAX124__M 20 240 CS Fall to Output Enable tov Figure 1 240 ns CS Rise to Output Disable tTR Figure 2 240 ns CS to SCLK Rise Setup tcss 100 ns CS to SCLK Rise Hold tCSH 0 ns SCLK Pulse Width High tCH 200 ns SCLK Pulse Width Low tcL 200 ns SCLK Fall to SSTRB tssTRB | Figure 1 240 ns CS Fall to SSTRB Output Enable tsbv External clock mode only, Figure 1 240 ns CS Rise to SSTRB Output Disable tsTR External clock mode only, Figure 2 240 ns SSTRB Rise to SCLK Rise tsck Internal clock mode only (Note 10) 0 ns Note 1: Tested at Vpp = 2.7V; COM = OV; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX1248internal reference, offset nulled; MAX1249 external reference (VREF = +2.500V), offset nulled. Note 4: Ground on channel; sine wave applied to all off channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to Vpp. Note 7 Sample tested to 0.1% AQL. Note 8: External load should not change during conversion for specified accuracy. Note 9: ADC performance is limited by the converters noise floor, typically 300pVp-p. Note 10 Guaranteed by design. Not subject to production testing. Note 11: The MAX1 249 typically draws 400A less than the values shown. Note 12: Measured as |Vrg(2.7V) - VFg(5.25V)|. MAXIM 5MAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Typical Operating Characteristics (Vpp = 3.0V, VREF = 2.500V, fscLk = 2.0MHz, CLoAD = 20pF, Ta = +25C, unless otherwise noted.) SUPPLY CURRENT (mA) INL (LSB) SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE 2.00 | : 40 8 2.5025 3 == z FULL POWER-DOWN | g CODE = 10101010 Bo : : 175 + Clow =50pF Ht" = 35 - = i Coa = 20pF & 30 2 150 | \ AF is F MAX1248 as Fa a 25 = L L "| > 2 I 1.25 I z 20 2.5000 Fro 5 f Maxine LK | CLoap = S0pF 2 tb +00 SS Z 15 3 oO ] Coan = 20pF 5 10 0.75 A w E 05 0.50 0 2.4975 225 275 325 375 425 475 5.25 225 275 325 375 425 475 525 225 275 325 375 425 475 5.25 SUPPLY VOLTAGE (V) Vo (V) SUPPLY VOLTAGE (V) SHUTDOWN CURRENT INTERNAL REFERENCE VOLTAGE SUPPLY CURRENT vs. TEMPERATURE vs. TEMPERATURE vs. TEMPERATURE 13 . 20 . 2.501 . 5 g Vpp = 5.25V g peer TL Maxi 248 ; ; 2900 , 12 = 16 L * < 3s | @ 2.499 = & _ La 3 @ 1.1 12 fr 2.498 3 7 1.0 z 08 thi 2.497 E Z MAX1249 5 3 2.496 oo PT I tf F 2.495 RLoap = >< og LOBES 010101000 0 404 60 -20 2 60 100 140 60-20 2 60 100 140 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) INTERGRAL NONLINEARITY INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. CODE 0.30 . 0.30 2 0,100 g 2 g g 3 =2.7V 3 0.075 i 0.25 0.25 0,050 0,20 0.20 = a 0% a 0.15 = 0.15 = 0 mere z z 010 -0,025 0.10 MAX1248 WAX 288 cose 0,05 ne MAX1249 MAX1249 -0.075 00 0 -0.100 225 275 325 375 425 475 5.25 -60 -40 -20 0 20 40 60 80 100 120 140 0 256 512 768 1024 SUPPLY VOLTAGE (V) TEMPERATURE (C) CODE MAXI4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Pin Description PIN NAME FUNCTION 1 Vppb Positive Supply Voltage 2-5 CHO-CH3 Sampling Analog Inputs Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to 6 COM +0.5LSB. Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1 249 down; otherwise, the 7 SHDN devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compen- sation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode. Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In 8 VREF internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to Vpp. 9 REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to Vpp. 10 AGND Analog Ground 11 DGND Digital Ground 12 DOUT Serial Data Output. Data is clocked out at SCLKs falling edge. High impedance when CS is high. Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the 13 SSTRB A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external clock mode). 14 DIN Serial Data Input. Data is clocked in at SCLks rising edge. 15 cS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. 16 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60%.) Vpp Vpp 6k 6k DOUT DOUT DOUT DOUT 6k | CLoap | CLoap 6k L CLoap L CLoap L 50pF L S0pF [ 50pF L 50pF = DGND = = DGND = DGD = = DGND a) High-Zto Voy and Vor to Vou b) High-Z to VoL and Voy to VoL a) Voy to High-Z b) Voy to High-Z Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time MAXIM v 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Detailed Description The MAX1248/MAX1249 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 10-bit digital output. A flexible serial interface provides easy interface to microproces- sors (uPs). Figure 3 is a block diagram of the MAX1248/MAX1 249. Pseudo-Differential Input The sampling architecture of the ADCs analog com- parator is illustrated in the equivalent input circuit (Figure 4). In single-ended mode, IN+ is internally switched to CHO-CH3, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from two pairs: CHO/CH1 and CH2/CH3. Configure the channels with Tables 2 and 3. Please note that the codes for CHO-CH3 in the MAX1248/MAX1249 correspond to the codes for CH2-CH5 in the eight-channel (MAX148/MAX1 49) versions. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain sta- ble within +0.5LSB (+0.1LSB for best results) with respect to AGND during a conversion. To accomplish this, connect a 0.1pF capacitor from IN- (the selected analog input) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval soans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acqui- sition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplex- er switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is sim- ply COM. This unbalances node ZERO at the compara- tors input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to OV within the limits of 10-bit resolution. This action is equivalent to transferring a charge of 16pF x [(Vin+) - (VIN-)] from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital represen- tation of the analog input signal. Track/Hold The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the converter samples the + input. If the converter is set up for dif- ferential inputs, IN- connects to the - input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHoOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, CS pel SCLK p18 | INPUT INT DIN 14 > SHIFT CLOCK _ REGISTER ["| conTROL SHDN pe LOGIC 2 LL _9. CHO <_ OUTPUT ia, DOUT CHt p38 = REGISTER| 4 ssTRB CH2 m+ Neat um CLOCK - MUX |_| Ll 5 SAR CHB ADC OUT com -6| = Yop 2 | oq, A206" 14 DGND REFERENCE 9 (MAX1248) maaan +2 AGND PEFADS osoov| MAxi248 vrer 8 +e. MAX1249 * A= 2.00 (MAX1249) CAPACITIVE DAC VREF --- COMPARATOR MU CHO o CHI o cCH2 o AT THE SAMPLING INSTANT, CH3 O THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED COM IN- CHANNEL. SINGLE- ENDED MODE: IN+ =CHO-CH3, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CHO/CH1 AND CH2/CH3. SWITCH Figure 3. Block Diagram 8 Figure 4. Equivalent Input Circuit MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Table 1. Control-Byte Format BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT O (MSB) (LSB) START SEL2 SEL1 SELO UNI/BIP SGL/DIF PD1 PDO BIT NAME DESCRIPTION 7(MSB) START The first logic 1 bit after CS goes low defines the beginning of the control byte. 6 SEL2 These three bits select which of the four channels are used for the conversion (Tables 2 and 3). 5 SEL1 4 SELO 3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from OV to VREF can be converted; in bipolar mode, the signal can range from -VREF / 2 to + VREF / 2. 2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single- ended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3). 1 PD1 Selects clock and power-down modes. 0(LSB) PDO PD1 PDO Mode 0 0 Full power-down 0 1 Fast power-down (MAX1248 only) 1 0 Internal clock mode 1 1 External clock mode the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, taca, is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by: taca = 7.6 x (Rs + RIN) x 16pF where Rin = 9kQ, Rg = the source impedance of the input signal, and taca is never less than 1.5us. Note that source impedances below 3kQ do not significantly affect the ADCs AC performance. Higher source impedances can be used if a 0.01pF capacitor is connected to the individual analog inputs. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADCs signal bandwidth. Input Bandwidth The ADCs input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic sig- nals with bandwidths exceeding the ADCs sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. MAXIM Analog Input Protection Internal protection diodes, which clamp the analog input to Vop and AGND, allow the channel input pins to swing from AGND - 0.3V to Vpp + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed Vpp by more than 50mV or be lower than AGND by 50mvV. If the analog input exceeds 50mV beyond the sup- plies, do not forward bias the protection diodes of off channels over 4mA. How to Start a Conversion A conversion is started by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1248/MAX1249s internal shift reg- ister. After CS falls, the first arriving logic 1 bit defines the control bytes MSB. Until this first start bit arrives, any number of logic 0 bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX1248/MAX1249 are compatible with SPI/QSP| and MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control reg- isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the sim- 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1) SEL2 SEL1 SELO CHO CH1 CH2 CH3 COM 0 0 1 + - 1 0 1 + - 0 1 0 + - 1 1 0 + - Table 3. Channel Selection in Differential Mode (SGL/DIF = 0) SEL2 SEL1 0 1 0 1 plest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 10-bit conversion result). See Figure 19 for MAX1248/ MAX1249 QSPI connections. Simple Software Interface Make sure the CPU's serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte RBS. 6) Pull CS high. Figure 5 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion padded with one leading zero, two sub-bits, and three trailing zeros. The total conversion time is a function of the 10 SELO CHO CH1 serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120us. Digital Output In unipolar input mode, the output is straight binary (Figure 16). For bipolar inputs, the output is twos com- plement (Figure 17). Data is clocked out at the falling edge of SCLK in MSB-first format. Clock Modes The MAX1248/MAX1249 may use either an external serial clock or the internal clock to perform the succes- sive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1248/MAX1249. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PDO of the control byte program the clock mode. Figures 6-9 show the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital con- version steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approxi- mation bit decisions are made and appear at DOUT on each of the next 10 SCLK falling edges (Figure 5). SSTRB and DOUT go into a high-impedance state when MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 SS - {t taca >} SCLK 1 4 8 12 16 20 24 DIN | 4 {sev2 seus [sero | YAY | Sau] PDI [Foo | ssTr8 START - _ + RBt._~ si RB2 ~<q RB3 __= DOUT nfs] 82 | 87 | 26 | es es] es] se | et | BS] st | s0 |zeHos ACQUISITION AD STATE IDLE rbe1.5:s>fe. CONVERSION) la IDLE (folk = 2MHz) Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fscLK < 2MHz) I I I 1 | ; Itcss _ I pt tcsH | Ke tev | | | | | I | | | | I I SCLK ) \ } \ y Noose / \ y \ I I |Past | | I pttoa I I I I | Vey ove * tbo-+ ttre Figure 6. Detailed Serial-Interface Timing CS goes high; after the next CS falling edge, SSTRB will the serial-clock frequency is less than 100kHz, or if output a logic low. Figure 7 shows the SSTRB timing in serial-clock interruptions could cause the conversion external clock mode. interval to exceed 120us. The conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if MAXIM " 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 SSTRB SCLK too CLOCKED | N Figure 7. External Clock Mode SSTRB Detailed Timing S| SCLK +] lol fa] fa] fal fel |7} Is UNI/ | SGL/ DIN | 4 {sev2 sex [sero | BIP | DIE | PD1 | Poo | START (fseLk = 2MHz) (SHDN = FLOAT) SSTRB fat tconv > FILLED WITH Bg Bo DOUT th Insel 8 Le7 |S) [igs] st | so [zeros [ ACQUISITION CONVERSION A/D STATE IDLE 1.5ps 7.5yus MAX IDLE Figure 8. Internal Clock Mode Timing Internal Clock In internal clock mode, the MAX1248/MAX1249 gener- ate their own conversion clocks internally. This frees the UP from the burden of running the SAR conversion clock and allows the conversion results to be read back at the processor's convenience, at any clock rate from OMHz to 2MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum of 7.5us (SHDN = FLOAT), during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the 12 MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figure 8). CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX1248/MAX1249 and three-states DOUT, but it does not adversely affect an internal clock mode con- version already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 9 shows the SSTRB timing in internal clock mode. In this mode, data can be shifted in and out of the MAX1248/MAX1249 at clock rates exceeding 2.0MHz if the minimum acquisition time, taca, is kept above 1.5us. MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 __ Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conver- sion starts on the falling edge of SCLK, after the eighth bit of the control byte (the PDO bit) is clocked into DIN. The start bit is defined as: The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VoD is applied. OR The first high bit clocked into DIN after bit 3 of a con- version in progress is clocked onto the DOUT pin. If CS is toggled before the current conversion is com- plete, the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated, and a new one is started. The fastest the MAX1248/MAX1249 can run with CS held low between conversions is 15 clocks per conver- sion. Figure 10a shows the serial-interface timing nec- essary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Most microcontrollers require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion is typically the fastest that a microcontroller can drive the MAX1248/MAX1249. Figure 10b shows the serial-inter- face timing necessary to perform a conversion every 16 SCLK cycles in external clock mode. Applications Information Power-On Reset When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1248/MAX1249 in internal clock mode, ready to convert with SSTRB = high. After the power supplies have stabilized, the internal reset time is 10us, and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN is interpreted as a start bit. Until a con- version takes place, DOUT shifts out zeros (also see Table 4). Reference-Buffer Compensation In addition to its shutdown function, SHDN selects inter- nal or external compensation. The compensation affects both power-up time and maximum conversion speed. The 100kHz minimum clock rate is limited by droop on the sample-and-hold, and is independent of the compensation used. I I \ SSTRB eee I I I I I I I I I | SCLK eee PDO CLOCK IN DOUT eee NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. Figure 9. Internal Clock Mode SSTRB Detailed Timing MAXIM 13 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 DIN XXXX $s CONTROL BYTE 0 $s CONTROL BYTE 1 S | CONTROL BYTE 2 pout SSTRB._ [| | B9 B8 B7 Be BS B4 B3 B2 B1 BO St SO | CONVERSION RESULT 0 [B89 BS B7 B6 BS B4 B3 B2 Bt BO Si SO | CONVERSION RESULT 1 Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing Ss | KXXXX SCLK XXX eee DIN XXXX S| CONTROL BYTE 0 $s CONTROL BYTE 1 eee pouT poor | Bo B8 B7 B6 BS B4 B3 B2 Bi BO Si So | CONVERSION RESULT 0 B9 B8 B7 B6 eee CONVERSION RESULT 1 KXXXX Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing Float SHDN to select external compensation. The Typical Operating Circuit uses a 4.7uF capacitor at VREF. A value of 4.7UF or greater ensures reference- buffer stability and allows converter operation at the 2MHz full clock speed. External compensation increas- es power-up time (see Choosing Power-Down Mode and Table 4). Pull SHDN high to select internal compensation. Internal compensation requires no external capacitor at VREF and allows for the shortest power-up times. The maximum clock rate is 2MHz in internal clock mode and 400kHz in external clock mode. Choosing Power-Down Mode You can save power by placing the converter in a low- current shutdown state between conversions. Select full power-down or fast power-down mode via bits 1 and 0 of the DIN control byte with SHDN high or floating (Tables 1 and 5). In both software power-down modes, the serial interface remains operational, but the ADC does not convert. Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 1 and 0 of the control byte. 14 Full power-down mode turns off all chip functions that draw quiescent current, reducing supply current typically to 2HA. Fast power-down mode turns off all circuitry except the bandgap reference. With fast power-down mode, the supply current is 30NA. Power-up time can be shortened to 5us in internal compensation mode. Table 4 shows how the choice of reference-buffer com- pensation and power-down mode affects both power-up delay and maximum sample rate. In external compensa- tion mode, power-up time is 20ms with a 4.7UF compen- sation capacitor when the capacitor is initially fully discharged. From fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than 1/2LSB while shut down. In power- down, leakage currents at VREF cause droop on the ref- erence bypass capacitor. Figures 11a and 11b show the various power-down sequences in both external and internal clock modes. MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Table 4. Typical Power-Up Delay Times REFERENCE-BUFFER VREF POWER-UP MAXIMUM eee COMPENSATION CAPACITOR POGOe DELAY SAMPLING RATE MODE (uF) (us) (ksps) Enabled Internal _ Fast 5 26 Enabled Internal _ Full 300 26 Enabled External 4.7 Fast See Figure 13c 133 Enabled External 4.7 Full See Figure 13c 133 Disabled _ _ Fast 2 133 Disabled _ _ Full 2 133 \ I CLOCK a i EXTERNAL MODE | EXTERNAL prt SHDN 1 | SETS EXTERNAL SETS SOFTWARE SETS EXTERNAL I 1 CLOCK MODE POWER-DOWN CLOCKMODE I I I AY AN I DIN |x| xtx}x] x] 11 s}x]x|x|x]x]o}o sl x{x]x]xbx] 1] DOUT 10+2 DATA BITS 10+2 DATA BITS ! VALID; INVALID rt DATA1 DATA | I I I I I I ! ! | HARDWARE ! MODE POWERED UP Bp POWERED UP omeg_POWER- ppstegg SOFTWARE | DOWN! powERED UP POWER-DOWN Figure 11a. Timing Diagram Power-Down Modes, External Clock CLOCK $$ MODE ; INTERNAL >! SETS INTERNAL SETS \ CLOCK MODE POWER-DOWN a aN | DIN SIXT XTXIX[X] 1/0 $]X|X1X]X1X]0] 0 s DOUT DATA VALID DATA VALID ! I SSTRB CONVERSION CONVERSION I I I MODE POWERED UP ot POWER-DOWN ot _ I 1 POWERED UP Figure 11b. Timing Diagram Power-Down Modes, Internal Clock MAXIM 15 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Table 5. Software Power-Down and Clock Mode PD1 PDO DEVICE 0 Full Power-Down 1 Fast Power-Down 1 0 Internal Clock 1 1 External Clock Table 6. Hardware Power-Down and Internal Clock Frequency 10,000 T 7 7 VREF = Vpp = 3.0V RLOAD = 1000 | CODE = 1010101000 100 WV acuanas J LEZ 1 CHANNEL Ipp (WA) 04 Ot 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz) SHDN DEVICE REFERENCE- INTERNAL STATE | MODE BUFFER CLOCK COMPENSATION | FREQUENCY 1 Enabled Internal 225kHz Floating Enabled External 1.8MHz 0 Power- N/A NA Down Software Power-Down Software power-down is activated using bits PD1 and PDO of the control byte. As shown in Table 5, PD1 and PDO also specify the clock mode. When software shutdown is asserted, the ADC operates in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quiescent-current state. In internal clock mode, the interface remains active, and conversion results may be clocked out after the MAX1248/MAX1249 enter a software power-down. The first logical 1 on DIN is interpreted as a start bit and powers up the MAX1248/MAX1249. Following the start bit, the data inout word or control byte also deter- mines clock mode and power-down states. For exam- ple, if the DIN word contains PD1 = 1, then the chip remains powered up. If PDO = PD1 = 0, a power-down resumes after one conversion. Hardware Power-Down Pulling SHDN low places the converter in hardware power-down (Table 6). Unlike software power-down mode, the conversion is not completed; it stops coinci- dentally with SHDN being brought low. SHDN also con- trols the clock frequency in internal clock mode. Letting SHDN float sets the internal clock frequency to 1.8MHz. When returning to normal operation with SHDN floating, there is a tRc delay of approximately 2MQ x CL, where CL is the capacitive loading on the SHDN pin. Pulling SHDN high sets the internal clock frequency to 225kHz. Figure 12. Average Supply Current vs. Conversion Rate with External Reference This feature eases the settling-time requirement for the reference voltage. With an external reference, the MAX1248/MAX1249 can be considered fully powered up within 2us of actively pulling SHDN high. Power-Down Sequencing The MAX1248/MAX1249 auto power-down modes can save considerable power when operating at less than maximum sample rates. Figures 12, 13a, and 13b show the average supply current as a function of the sampling rate. The following discussion illustrates the various power-down sequences. Lowest Power at up to 500 Conversions/Channel/Second The following examples illustrate two different power- down sequences. Other combinations of clock rates, compensation modes, and power-down modes may give lowest power consumption in other applications. Figure 13a depicts the MAX1248 power consumption for one or eight channel conversions, utilizing full power-down mode and internal-reference compensa- tion. A 0.01pF bypass capacitor at REFADJ forms an RC filter with the internal 20kQ reference resistor with a 0.2ms time constant. To achieve full 10-bit accuracy, 8 time constants or 1.6ms are required after power-up. Waiting 1.6ms in FASTPD mode instead of in full power- up can reduce the power consumption by a factor of 10 or more. This is achieved by using the sequence shown in Figure 14. MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 100 RLoap = CODE = 1010101000 AVERAGE SUPPLY CURRENT (1A) So 1 CHANNEL 001 04 1 10 100 1k CONVERSION RATE (Hz) 10,000 1000 BRIT aa i 1 CHANNEL eS a AVERAGE SUPPLY CURRENT (11A) 3 8 01 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hq Figure 13a. MAX1248 Supply Current vs. Conversion Rate, FULLPD Lowest Power at Higher Throughputs Figure 13b shows the power consumption with external-reference compensation in fast power-down, with one and four channels converted. The external 4.7UF compensation requires a 75us wait after power-up with one dummy conversion. This circuit combines fast multi-channel conversion with lowest power consumption possible. Full power-down mode may provide increased power savings in applications where the MAX1248/MAX1 249 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. Internal and External References The MAX1248 can be used with an internal or external reference voltage, whereas an external reference is required for the MAX1249. An external reference can be connected directly at VREF or at the REFADJ pin. An internal buffer is designed to provide 2.5V at VREF for both the MAX1248 and the MAX1249. The MAX1248's internally trimmed 1.21V reference is buffered with a gain of 2.06. The MAX1249s REFADJ pin is also buffered with a gain of 2.06 to scale an external 1.25V reference at REFADJ to 2.5V at VREF. Internal Reference (MAX1248) The MAX1248s full-scale range with the internal refer- ence is 2.5V with unipolar inputs and +1.25V with bipo- lar inputs. The internal-reference voltage is adjustable to +1.5% with the circuit of Figure 15. MAXIM Figure 13b. MAX1248 Supply Current vs. Conversion Rate, FASTPD 3.0 25 2.0 POWER: UP DELAY (ms) Y 0 0.01 0.1 1 10 TIME IN SHUTDOWN (sec) Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown 17 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 COMPLETE CONVERSION SEQUENCE bt 1.6ms WAIT (ZEROS) ( (ZEROS) CHI CH7 ow ETT} \% TUE ACLS ATL eet 4 TT FULLPD FASTPD NOPD FULLPD FASTPD 1.21V | REFADJ ov > 50V t =RC =20kQ x Crean VREF ov 1BUFFEN ~ 75US Figure 14. MAX1248 FULLPD/FASTPD Power-Up Sequence External Reference With both the MAX1248 and MAX1249, an external ref- erence can be placed at either the input (REFADJ) or the output (VREF) of the internal reference-buffer ampli- fier. The REFADJ input impedance is typically 20kQ for the MAX1248 and higher than 100kQ for the MAX1249, where the internal reference is omitted. At VREF, the DC input resistance is a minimum of 18kQ. During con- version, an external reference at VREF must deliver up to 350A DC load current and have an output impedance of 10Q or less. If the reference has higher output impedance or is noisy, bypass it close to the VREF pin with a 4.7pF capacitor. Using the REFADJ input makes buffering the external reference unnecessary. To use the direct VREF input, disable the internal buffer by tying REFADJ to Vpp. In power-down, the input bias current to REFADJ can be as much as 25uA with REFADJ tied to Vpp. Pull REFADJ to AGND to minimize the input bias current in power-down. Transfer Function Table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. The external reference must have a temperature coeffi- cient of 20ppm/C or less to achieve accuracy to within 1LSB over the commercial temperature range of 0C to +70C. Figure 16 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 17 shows the bipolar input/output transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = 2.44mV (2.500V / 1024) for unipolar operation and 1LSB = 2.44mV [(2.500V / 2 - -2.500V / 2) / 1024] for bipolar operation. 18 $3.3V 24k MAXIAA MAX1248 510k 9 100k Ne REFADJ = 0.01pF T Figure 15. MAX1248 Reference-Adjust Circuit OUTPUT CODE FULL-SCALE 12.411 TRANSITION 11... 110 11... 104 ; I l c I l y I ; ' FS = VREF + COM I / I , | ZS=COM 4 | 1LSB = WREF 1024 00...011 ! 00... 010 ! 00... 001 ! oo...o09 LLy 4+ 4--------- oe 0 1 2 8 A FS (COM INPUT VOLTAGE (LSBs) FS - 3/2LSB Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF + COM, Zero Scale (ZS) = COM MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Table 7. Full Scale and Zero Scale UNIPOLAR MODE BIPOLAR MODE Full Scale Zero Seale Positive Zero Negative Full Scale Scale Full Scale VREF / 2 -VREF / 2 VREF + COM COM COM + COM + COM OUTPUT CODE VREF 011...111 FS = +COM 011...110-7 7_coM \ SUPPLIES I Tg _ -VPEF -FS = +COM I +3V +3V GND 000...010 2 \ 000...001 + 4,9 3_ WREF ; 000...000 K---- Wed da - I Ht... ; \ F-10008 __ 111...110 + ; 1 111...101 + 1 ! Je ! ; + ; 1 Vpp AGND COM DGND +3V. DGND 100...001 \ 1 . I 100... 000 I MAXLAN DIGITAL | ( I ( | MAX1248 CIRCUITRY I yy + ) MAX1249 - FS COM +FS - 1LSB INPUT VOLTAGE (LSB) OPTIONAL *COM > VREF/2 Figure 17. Bipolar Transfer Function, Zero Scale (ZS) = COM, Full Scale (FS) = VREF/2+ COM Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 18 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to the star ground. No other digital system ground should be connected to this ground. For lowest noise operation, the ground return to the star grounds power supply should be low impedance and as short as pos- sible. MAXIM Figure 18. Power-Supply Grounding Connection High-frequency noise in the Vpp power supply may affect the ADCs high-speed comparator. Bypass the supply to the star ground with 0.1pF and 1pF capaci- tors close to pin 1 of the MAX1248/MAX1249. Minimize capacitor lead lengths for best supply-noise rejection. If the +3V power supply is very noisy, a 10 resistor can be connected as a lowpass filter (Figure 18). High-Speed Digital Interfacing with QSPI The MAX1248/MAX1249 can interface with QSPI using the circuit in Figure 19 (fscLk = 2.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the four channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own micro-sequencer. The MAX1248/MAX1249 are QSPI compatible up to their maximum external clock frequency of 2MHz. 19 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 BV 4V te u _ a Lt 1] Voo scik [16] = SCK 0.1 pF " 2| CHO pg axiaa CS 45] PCSO MC683XX = ANALOG {3| CHI MAXIDAg DIN 4} MOSI inputs.) a] cre ssTre [13] {5] crs pour |12] Miso re COM DGND [11 = |7] SHDN AGND |10 42.5V "Te VREF REFADJ | 9 } =] ow O.1F r CLOCK CONNECTIONS NOT SHOWN 1 Figure 19. MAX1248/MAX1249 QSPI Connections External Reference TMS320LC3x Interface Figure 20 shows an application circuit to interface the MAX1248/MAX1249 to the TMS320 in external clock mode. The timing diagram for this interface circuit is |= shown in Figure 21. F os Use the following steps to initiate a conversion in the CLKX pw! SCLK MAX1248/MAX1249 and to read the results: TMS3201.C3x MAXIM 1) The TMS320 should be configured with CLKX CLKR {a MAX1249 (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high DX em! DIN input clock. CLKX and CLKR on the TMS320 are tied together with the MAX1248/MAX1249s SCLK DR lag DOUT input. 2) The MAX1248/MAX1249s CS pin is driven low by FSR bt SSTRB the TMS320s XF_ I/O port, to enable data to be clocked into the MAX1248/MAX1249s DIN. 3) An 8-bit word (1XXXXX11) should be written to the MAX1248/MAX1 249 to initiate a conversion and , place the device into external clock mode. Refer to Figure 20. MAX1248/MAX1249-to-TMS320 Serial Interface Table 1 to select the Proper XXXXxX bit values for 5) The TMS320 reads in one data bit on each of the your specific application. next 16 rising edges of SCLK. These data bits rep- 4) The MAX1248/MAX1249s SSTRB output is moni- resent the 10 + 2-bit conversion result followed by tored via the TMS320's FSR input. A falling edge on four trailing bits, which should be ignored. the SSTRB output indicates that the conversion is in 6) Pull CS high to disable the MAX1248/MAX1249 until 20 progress and data is ready to be received from the MAX1248/MAX1249. the next conversion is initiated. MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 aa fo DIN | stant { SEL2 Y seu Y seto \ unvaiP| savor} PD1 | PDO \ W HIGH SSTRB | \ [IMPEDANCE Sa HIGH DOUT [ us | BB a | Si I So \ [IMPEDANCE Figure 21. TMS320 Serial-interface Timing Diagram Ordering Information (continued) INL INL PART* TEMP. RANGE = PIN-PACKAGE (LSB) PART* TEMP. RANGE PIN-PACKAGE (LSB) MAX1248AEPE -40C to +85C =: 16 Plastic DIP) ss + 1/2 MAX1249ACEE OC to +70C }~=6 16 QSOP +1/2 MAX1248BEPE -40C to+85C 16PlasticDIP +1 MAX1249BCEE OC to +70C =16 QSOP +1 MAX1248AEEE -40C to +85C }3=s- 16 QSOP +1/2 MAX1249AEPE -40C to +85C ~- 16 Plastic DIP +1/2 MAX1248BEEE -40Cto+85C 16 QSOP +1 MAX1249BEPE -40C to +85C ~- 16 Plastic DIP +1 MAX1248AMJE = -55C to+125C =16 CERDIP* 1/2 MAX1249AEEE -40C to +85C }3=- 16 QSOP +1/2 MAX1248BMJE = -55C to+125C =16 CERDIP* +1 MAX1249BEEE -40C to +85C }= 16 QSOP +1 MAX1249ACPE OC to+70C =6.16 Plastic DIP =s + 1/2 MAX1249AMJE -55C to +125C =16 CERDIP* +1/2 MAX1249BCPE OC to+70C = =6.16 Plastic DIP) ss +1 MAX1249BMJE -55C to +125C =16 CERDIP* +1 + Contact factory for availability of alternate surface-mount packages. * Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B. 21 MAXIM 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 Pin Configuration Chip Information TRANSISTOR COUNT: 2554 22 QSOP.EPS TOP VIEW . Vop Ly] 6] SCLK cro [2 | 15] CS cuts | py acan [4] oN CH2 | 4 MAX1248 13 La] MAX1249 3] sss crs [5 | [2] pour com [6 | 1] Deno SHON [7 | [10] AGNO veer [ | [9 | REFADJ DIP/QSOP Package Information _ | - 4 INCHES MILLIMETERS | Ev2 e ' ! Ce t 4 \ a ww NOTES: 1. D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .006 PER SIDE. 3. HEAT SLUG DIMENSIONS X AND Y APPLY ONLY TO 16 AND 28 LEAD POWER-QSOP PACKAGES. 4. CONTROLLING DIMENSIONS: INCHES. e h x SEE Y 087 O s O VARIATIONS: MA AXAIL/VI PROPRIETARY INF DRMATION TITLE: PACKAGE OUTLINE, QSOP, 150, 025 LEAD PITCH APPROVAL DOCUMENT CONTROL NOL Rev 21-0055 B A MAXIMA4+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAXIM a om ra onl JI Jy JT sor [tenon cludes [O75 S{0.055 [0.080 OO O22 LO045 [eS O.008 HS MOTEL 1 De DO NOT INCLUDE MOLD FLASH e, MOLD FLATH a PPOTPUS TON? NOT TO Exceed 15mm sce" + 3. CONTPOLLING DIMEN: TOM MILLIMETEP. 4. MEETC JEDEC Mindi-x* Al JHOWN IN ABOVE TABLE 5 SIMILIAP TO JEDEC MO-NSe84B oo NM = NUMBEP OF PINS ; x J] === [4ns | --- [ites |e if --- [0 : Vf --- |ae4o] --- y | --- [ose tf --- [leo 1 NOTES L CONTPOLLING DIMENSION: INCH 2 MEET. 1225 CATE OUTLINE COMPIGUPATION #1 &= CHOWN IN ABOVE TABLE 3M = MUMBEP OF PINS Package Information (continued) 23 6VCLXVW/8I7CLXVWNMAX1248/MAX 1249 4+2./V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 1998 Maxim Integrated Products Printed USA MAXIMA is a registered trademark of Maxim Integrated Products.