PPC603EFACT/D REV. 7 Fact Sheet MOTOROLA POWERPC 603eTM MICROPROCESSOR The Motorola PowerPC 603e microprocessor (MPC603e) is a low-power implementation of the PowerPC Reduced Instruction Set Computer (RISC) architecture. The PowerPC 603e microprocessor offers workstationlevel performance packed into a low-power, low-cost design ideal for desktop computers, notebooks and battery-powered systems, as well as printer and imaging equipment, telecommunications systems, networking and communications infrastructure, industrial controls, and home entertainment and educational devices. Industrial-grade, extended temperature PowerPC 603e microprocessors are available for harsh operating environments. The PowerPC 603e microprocessor is software- and bus-compatible with the PowerPC 740TM, PowerPC 750TM, and MPC7400 microprocessor families. Motorola PowerPC 603e Microprocessor Superscalar Microprocessor The PowerPC 603e microprocessor is a superscalar design capable of issuing three instructions per clock cycle into five independent execution units, including: Integer unit Load/Store unit Floating-point unit System register unit Branch processing unit The ability to execute multiple instructions in parallel, to pipeline instructions, and the use of simple instructions with rapid execution times yields maximum efficiency and throughput for PowerPC 603e systems. Product Highlights The PowerPC 603e microprocessor features a low-power 2.5-volt or 3.3-volt design with three power-saving modes--doze, nap and sleep. These user-programmable modes progressively reduce the power drawn by the processor. The PowerPC 603e microprocessor also uses dynamic power management to selectively activate functional units as they are needed by the executing instructions. Unused functional units enter a low-power state automatically without affecting performance, software execution, or external hardware. PowerPC 603e Microprocessor Block Diagram System Register Unit Integer Unit Branch Processing Unit Load/Store Unit Instruction Unit Floating Point Unit MMU MMU Data Cache Inst. Cache Bus Interface Unit 32b Address 32b/64b Data System Bus Cache and MMU Support The PowerPC 603e microprocessor has separate 16-Kbyte, physically-addressed instruction and data caches. Both caches are four-way set-associative. The PowerPC 603e microprocessor also contains separate memory management units (MMUs) for instructions and data. The MMUs support 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory. Access privileges and memory protection are controlled on block or page granularities. Large, 64entry translation lookaside buffers (TLBs) provide efficient physical address translation and support for demand virtual-memory management on both page- and variable-sized blocks. Flexible Bus Interface The PowerPC 603e microprocessor has a selectable 32- or 64-bit data bus and a 32-bit address bus. Support is included for burst, split and pipelined transactions. The interface provides snooping for data cache coherency. The PowerPC 603e microprocessor maintains MEI coherency protocol in hardware, allowing access to system memory for additional caching bus masters, such as DMA devices. Contact Information Motorola offers user's manuals, application notes and sample code for all of its processors. In addition, local support for these products is also provided. This information can be found at: http://motorola.com/PowerPC/ PowerPC 603e CPU Summary Bus Interface L1 Cache For all other inquiries about Motorola products, please contact the Motorola Customer Response Center at: 200-300 MHz 200*, 266 and 300 MHz x1.5, x2, x2.5, x3, x3.5, x4 x2, x2.5, x3, x3.5, x4, x4.5, x5, x5.5, x6 64-and 32-bit modes 64-and 32-bit modes 3 (2 + Branch) 3 (2 + Branch) 16-Kbyte instruction 16-Kbyte data 16-Kbyte instruction 16-Kbyte data 4.2W/5.3W @ 133 MHz 4.0W/6.0W @ 300 MHz Instructions per Clock Typical/Maximum Power Dissipation MPC603e 100-133 MHz 100 and 133 MHz CPU Speeds - Internal CPU Bus Dividers MPC603e 98 mm2 42 mm2 Package 240 CQFP, 255 CBGA 255 CBGA - all: 255 PBGA @200 Process 0.5 4LM CMOS 0.29 5LM CMOS Die Size Phone: 800-521-6274 or http://motorola.com/semiconductors 2.6 million 2.6 million 3.3V 3.3V i/o, 2.5V internal SPECint95 (estimated) 3.9 @ 133 MHz 7.4 @ 300 MHz SPECfp95 (estimated) 3.1 @133 MHz 6.1 @ 300 MHz 188 MIPS @ 133 MHz 423 MIPS @ 300 MHz Transistors Voltage Other Performance Integer, Floating-Point, Branch, Integer, Floating-Point, Branch, Execution Units Load/Store, System Register Load/Store, System Register *see hardware specifications for operation at lower frequencies PowerPC 1xx, 6xx and 7xx Part Number Key MPC 603 R RX 300 L C Revision Frequency 2-3 digits Package FE CQFP Application Modifier RX CBGA w/o lid Bus Ratio PX PBGA w/o lid C 2:1 (106 only) ZT PBGA w/lid D 5:2 (106 only) L Full spec all modes Part/Module Modifier -orA Alpha (original) Application Relief B DGO process E 603 Enhanced Performance R 105 P Enhanced & Lower Voltage T ext. temp. (-40 to 105) R 603e in HiP3 process 100, 600, or 700 Series Device Number (106, 107, 603, 740, 745, 750, 755) Product Code PPC Sample XPC XC qualified MPC Qualified (c) 2000 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola and the are registered trademarks of Motorola, Inc. PowerPC, the PowerPC logo, PowerPC 603e, PowerPC 740, and PowerPC 750 are trademarks of International Business Machines Corporation and used under license therefrom. This document contains information on a new product under development. Specifications and information herein are subject to change without notice. 1ATX31875-7 Printed in USA 05/00 Hibbert LITRISC