Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
FEBRUARY 2007 REV. 1.0.2
GENERAL DESCRIPTION
The XR16C2550 (2550) is a dual universal
asynchronous receiver and transmitter (UART). The
XR16C2550 is an improved version of the PC16550
UART with higher operating speed and faster access
times. The 2550 provides enhanced UART functions
with 16 byte FIFO’s, a modem control interface, and
data rates up to 4 Mbps. Onboard status registers
provide the user with error indications and
operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Independent
programmable baud rate generators are provided to
select transmit and receive clock rates from 50 bps to
4 Mbps. The Baud Rate Generator can be configured
for either crystal or external clock input. An internal
loopback capability allows onboard diagnostics. The
2550 is available in a 44-pin PLCC and 48-pin TQFP
packages. The 2550 is fabricated in an advanced
CMOS process capable of operating from 2.97 volt to
5.5 volt power supply.
APPLICATIONS
•Portable Appliances
•Telecommunication Network Routers
•Ethernet Network Rout ers
•Cellular Data Devices
•Factory Automation and Process Controls
FEATURES
•2.97 Volt to 5.5 Volt Operation
•5 Volt Tolerant Inputs
•Pin-to-pin compatible to Exar’s ST16C2450,
XR16L2550 and XR16L2750
•Pin-to-pin comp at ible to TI’s TL16C752B on the 48-
TQFP package
•Pin alike XR16C2850 48-TQFP package but
without CLK8/16, CLKSEL and HDCNTL inputs
•2 independent UART channels
■Up to 4 Mbps with external clock of 64 MHz
■Up to 1.5 Mbps data rate with a 24 MHz crystal
frequency
■16 byte T ransmit FIFO to reduce the ba ndwidth
requirement of the external CPU
■16 byte Receive FIFO with error t ags to r edu ce
the bandwidth requireme nt of the external CPU
■4 selectable Receive FIFO interrupt trigger
levels
■Modem control signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
■Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
•Crystal oscillator or external clock input
•48-TQFP and 44-PLCC packages
FIGURE 1. XR16C2550 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
8- bit Data
Bus
Interface
UART Channel A
16 Byte TX FIFO
16 Byte RX FIFO
BRG TX & RX
UART
Regs
2.97V to 5.5V
GND
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB #,
OP2B#
UART Channel B
( same as Channel A )
A2:A0
D7:D0
CSA#
CSB#
INTA
INTB
IOW#
IOR#
Reset
TXRDYA#
TXRDYB#
RXRDYA#
RDRXYB#
*All inputs are 5V tolerant
XR16C2550
2
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
FIGURE 2. PIN OUT ASSIGNMENT
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING
TEMPERATURE RANGE DEVICE STATUS
XR16C2550IJ 44-Lead PLCC -40°C to +85°C Active
XR16C2550IM 48-Lead TQFP -40°C to +85°C Active
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
NC
XTAL1
XTAL2
IOW#
CDB#
GND
RXRDYB#
IOR#
DSRB#
RIB#
RTSB#
CTSB#
NC
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
NC
D4
D3
D2
D1
D0
TXRDYA#
VCC
RIA#
CDA#
DSRA#
CTSA#
NC
XR16C2550
48-pin TQFP
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
XTAL1
XTAL2
IOW#
CDB#
GND
RXRDYB#
IOR#
DSRB#
RIB#
RTSB#
CTSB#
D4
D3
D2
D1
D0
TXRDYA#
VCC
RIA#
CDA#
DSRA#
CTSA#
XR16C2550
44-pin PLCC
XR16C2550
3
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME 40-PDIP
PIN # 44-PLCC
PIN # 48-TQFP
PIN # TYPE DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
26
27
28
29
30
31
26
27
28
IAddress data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A/B during a data bus transac-
tion.
D7
D6
D5
D4
D3
D2
D1
D0
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
IO Data bus lines [7:0] (bidirectional).
IOR# 21 24 19 IInput/Output Read Strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal
register pointed to by the address lines [A2:A0]. The data byte is
placed on the data bus to allow the host processor to read it on the
rising edge.
IOW# 18 20 15 IInput/Output Write S trobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the addre ss lines.
CSA# 14 16 10 IUART channel A select (active low) to enable UART channel A in
the device for data bus operation.
CSB# 15 17 11 IUART channel B select (active low) to enable UART channel B in
the device for data bus operation.
INTA 30 33 30 OUART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default). See MCR[3].
INTB 29 32 29 OUART channel B Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0 (default). See MCR[3].
TXRDYA# - 1 43 OUART channel A Transmitter Ready (active low). The output pro-
vides the TX FIFO/THR status for transmit channel A. See Table 2.
If it is not used, leave it unconnected.
RXRDYA# -34 31 OUART channel A Receiver Ready (active low). This output provides
the RX FIFO/RHR status for receive channel A. See Table 2. If it is
not used, leave it unconnected.
TXRDYB# -12 6 O UART channel B Transmitter Ready (active low). The output pro-
vides the TX FIFO/THR status for transmit channel B. See Table 2.
If it is not used, leave it unconnected.
XR16C2550
4
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
RXRDYB# -23 18 OUART channel B Receiver Ready (active low). This output provides
the RX FIFO/RHR status for receive channel B. See Table 2. If it is
not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA 11 13 7 O UART channel A Transmit Data. If it is not used, leave it uncon-
nected.
RXA 10 11 5 I UART channel A Receive Data. Normal receive data input must idle
at logic 1 condition. If it is not used, tie it to VCC or pull it high via a
100k ohm resistor.
RTSA# 32 36 33 OUART channel A Request-to-Send (active low) or general purpose
output. If it is not used, leave it unconnected.
CTSA# 36 40 38 IUART channel A Clear-to-Send (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
DTRA# 33 37 34 OUART channel A Data-Terminal -Ready (active low) or general pur-
pose output. If it is not used, leave it unconnected.
DSRA# 37 41 39 IUART channel A Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
CDA# 38 42 40 IUART channel A Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
RIA# 39 43 41 IUART channel A Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
OP2A# 31 35 32 OOutput Port 2 Channel A - The output state is defined by the user
and through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output to a logic 0 when MCR[3] is set to a logic
1. INTA is set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTA output function-
ality. If it is not used at all, leave it unconnecte d.
TXB 12 14 8 O UART channel B Transmit Data. If it is not used, leave it uncon-
nected.
RXB 910 4 I UART channel B Receive Data. Normal receive data input must idle
at logic 1 condition. If it is not used, tie it to VCC or pull it high via a
100k ohm resistor.
RTSB# 24 27 22 OUART channel B Request-to-Send (active low) or general purpose
output. If it is not used, leave it unconnected.
CTSB# 25 28 23 IUART channel B Clear-to-Send (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
DTRB# 34 38 35 OUART channel B Data-Terminal -Ready (active low) or general pur-
pose output. If it is not used, leave it unconnected.
Pin Description
NAME 40-PDIP
PIN # 44-PLCC
PIN # 48-TQFP
PIN # TYPE DESCRIPTION
XR16C2550
5
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
DSRB# 22 25 20 IUART channel B Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
CDB# 19 21 16 IUART channel B Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
RIB# 23 26 21 IUART channel B Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
OP2B# 13 15 9 O Output Port 2 Channel B - The output state is defined by the user
and through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output to a logic 0 when MCR[3] is set to a logic
1. INTB is set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTB output function-
ality. If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1 16 18 13 ICrystal or external clock input.
XTAL2 17 19 14 OCrystal or buffered clock output.
RESET 35 39 36 IReset (active high) - A longer than 40 ns logic 1 pulse on this pin will
reset the internal registers and all outputs. The UART transmitter
output will be held at logic 1, the receiver input will be ignored and
outputs are reset during reset period (see External Reset Condi-
tions).
VCC 40 44 42 Pwr 2.97V to 5.5V power supply. All inputs are 5V tolerant.
GND 20 22 17 Pwr Power supply common, ground.
N.C. - - 12, 24,
25, 37 No Connection.
Pin Description
NAME 40-PDIP
PIN # 44-PLCC
PIN # 48-TQFP
PIN # TYPE DESCRIPTION
XR16C2550
6
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
1.0 PRODUCT DESCRIPTION
The XR16C2550 (2550) integrates the functions of two 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The 2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-
parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The 2550 represents such an integration with greatly enhanced features. The 2550 is fabricated with an
advanced CMOS process.
The 2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The 2550 is designed to work with high speed modems and
shared network environments, that require fast data processing time. Increased perfo rmance is re alized in the
2550 by the transmit and receive FIFO’s. This allows the external processor to handle more networking tasks
within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (This example u ses a character length of 11 bits , including st ar t/stop bit s at 115.2 Kbp s). This
means the external CPU will have to service the receive FIFO less than every 100 microseconds. However
with the 16 byte FIFO in the 2550, the dat a buf fer will not require unloading/loading for 1.53 ms. This increases
the service interval giving the external CPU additional time for other applications and reducing the overall
UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is uniquely
provided for maximum data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The 2550 is capable of operation up to 4 Mbps with a 64 MHz external clock. With a crystal or external clock
input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
The rich feature se t of the 2550 is available through int ernal registers. Selectable receive FIF O trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset, the 2550 is software compatible with the previous generation, ST16C2450.
XR16C2550
7
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2550 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections ar e shown in Figure 3.
.2.2 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 11). An active high pulse of at least 40 ns duration will be required to activate the reset
function in the device.
2.3 Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UAR Ts can be useful during power up initialization to write to the same internal re gisters,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table 1.
FIGURE 3. XR16C2550 DATA BUS INTERCONNECTIONS
TABLE 1: CHANNEL A AND B SELECT
CSA# CSB# FUNCTION
1 1 UART de-selected
0 1 Channel A selected
1 0 Channel B selected
0 0 Channel A and B sel e cted
VCC
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
RXRDYA#
TXRDYA#
RXRDYA#
TXRDYA#
RXRDYB#
TXRDYB#
RXRDYB#
TXRDYB#
UART_RESET RESET
Serial Interface of
RS-232, RS-485
Serial Interface of RS-
232, RS-485
2750int
XR16C2550
8
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
2.4 Channel A and B Internal Registers
Each UART channel in the 2550 has a standard register set for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratch pad register (SPR).
2.5 DMA Mode
The device does not support dir ect memory access. Th e DMA Mode ( a legacy ter m) in this docum ent does n ot
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the 2550 is placed in single-character mode for data transmit or receive operation.
When DMA mode is en abled (FC R bit-3 = 1), the user takes adva ntage of block mo de operati on by loadin g or
unloading the FIFO in a block seq uence dete rmined by th e progra mmed trigg er level. The fo llowing t able show
their behavior. Also see Figures 17 through 22.
2.6 INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Tables 3and 4summarize the operating behavior for the transmitter and receiver. Also see Figures 17
through 22.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA M ODE
PINS FCR BIT-0=0
(FIFO DISABLED)FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled) FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B 0 = 1 byte.
1 = no data. 0 = at least 1 byte in FIFO
1 = FIFO empty. 1 to 0 transition when FIFO reaches the trigger
level, or time-out occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B 0 = THR empty.
1 = byte in THR. 0 = FIFO empty.
1 = at least 1 byte in FIFO. 0 = FIFO has at least 1 empty location.
1 = FIFO is full.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin 0 = a byte in THR
1 = THR empty 0 = at least 1 byte in FIFO
1 = FIFO empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin 0 = no data
1 = 1 byte 0 = FIFO below trigger level
1 = FIFO above trigger level
XR16C2550
9
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
2.7 Crystal Oscillator or Exte rnal Clock Input
The 2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. SEE”PROGRAMMABLE BAUD
RATE GENERATOR” ON PAGE 9.
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500kΩ to
1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
2.8 Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24
MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as
shown in Figure 5) it can extend its operation up to 64 MHz (4Mbps serial data rate) at room temperature and
5.0V.
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
C1
22-47 pF C2
22-47 pF
Y1 1.8432 MHz
to
24 MHz
R1
0-120 Ω
(Optional)
R2
500 ΚΩ − 1 Μ Ω
XTAL1 XTAL2
XR16C2550
10
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in Figure 6.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
FIGURE 6. OPERATING FREQUENCY VERSUS POWER SUPPLY CHART.
Requires a 2K ohms pull-up resistor on XTAL2 pin to incre ase operating speed
2K
XTAL1
XTAL2
R1
VCC
External Clock
vcc
gnd
60
50
40
30
3.0 4.5 5.53.5 4.0 5.0
Suppy Voltage
XTAL1 External Clock Frequency in MHz.
70
80
85oC
25oC
-40oC
Operating frequenc y for XR 16 C 255 0
with external clo ck and a 2 K ohm s
pull-up resist or on XTAL2 pin.
XR16C2550
11
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
The 2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock
by any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 5 shows the standard data rates available with a 14.7 456 MHz crystal or extern al clock at 1 6X samplin g
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
2.9 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
insert s the proper p arity-bit if enab led, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Reg iste r (L SR bit- 5 an d bit -6 ).
2.9.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and st op-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.9.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is tran sferred to TSR. THR flag ca n generate a transmit emp ty interrupt (I SR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0 DIVISOR FOR 16x
Clock (Decimal) DIVISOR FOR 16x
Clock (HEX) DLM PROGRAM
VALUE (HEX) DLL PROGRAM
VALUE (HEX) DATA RATE
ERROR (%)
400 2304 900 09 00 0
2400 384 180 01 80 0
4800 192 C0 00 C0 0
9600 96 60 00 60 0
19.2k 48 30 00 30 0
38.4k 24 18 00 18 0
76.8k 12 0C 00 0C 0
153.6k 606 00 06 0
230.4k 404 00 04 0
460.8k 202 00 02 0
921.6k 101 00 01 0
XR16C2550
12
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
2.9.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
2.10 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false st art bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clo cks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register . RHR can generate a receive data ready interrupt upon receiving a char acter or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guarantee d by a re ceive data ready
time-out interrupt when da ta is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 8. TRANSMITTER OPERATION IN FIFO MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X Clock
Transm it Data Shift Register
(TSR)
D ata B yte
THR Interrupt (IS R bit-1) when TX
FIFO becom es empty. FIF O is
enabled by FCR bit-0=1.
Transmit FIFO
16X C lock
TXFIFO1
THR
XR16C2550
13
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
2.10.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 10. RECEIVER OPERATION IN FIFO MODE
Receive Data Shift
Register (RSR)
Receive
D ata Byte
and Errors R HR Interrupt (ISR b it-2)
Receive Data
H o ld in g Registe r
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
Receiv e Data Shi ft
Register (RSR)
RXFIFO1
16X Clock
Error Tags
(16-sets)
Error Tags in
LSR bits 4:2
16 bytes by 11-bit
wide FIFO
Receive Data Characters
Data Bit
Validation
RX FIFO
RHR
Receive Data
Byte and Errors
RHR Interrupt (ISR bi t-2) when FI FO fill s
up to trigger level.
FIFO is Enabled by FCR bit-0=1
XR16C2550
14
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
2.11 Internal Loopback
The 2550 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UAR T functions oper ate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is intern ally routed to th e r ec eiv e sh ift regist er input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
RTSA#/RTSB#
MCR bit-4= 1
VCC
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2A#/OP2B#
VCC
XR16C2550
15
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the 2550 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CSA# or CSB# selecting the channel. The registers are 16C550 compatible. The complete
register set is shown on Table 6 and Table 7.
TABLE 6: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES REGISTER READ/WRITE COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0 RHR - Receive Holding Register
THR - Tran smit Holding Register Read-only
Write-only LCR[7] = 0
0 0 0 DLL - Div Latch Low Byte Read/Write LCR[7] = 1
0 0 1 DLM - Div Latch High Byte Read/Write LCR[7] = 1
0 0 1 IER - Interrupt Enable Register Read/Write LCR[7] = 0
0 1 0 ISR - Interrupt Status Register
FCR - FIFO Control Register Read-only
Write-only
0 1 1 LCR - Line Control Register Read/Write
1 0 0 MCR - Modem Control Register Read/Write
1 0 1 LSR - Line S tatus Register
Reserved Read-only
Write-only
1 1 0 MSR - Modem Status Register
Reserved Read-only
Write-only
1 1 1 SPR - Scratch Pad Register Read/Write
XR16C2550
16
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 12.
4.2 Tr ansmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 11.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
TABLE 7: INTERNAL REGISTERS DESCRIPTION
ADDRESS
A2-A0 REG
NAME
READ/
WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
LCR[7] = 0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 IER RD/WR 0000Modem
Stat.
Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
0 1 0 ISR RD FIFOs
Enabled FIFOs
Enabled 0 0 INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
0 1 0 FCR WR RX FIFO
Trigger RX FIFO
Trigger 0 0 DMA
Mode
Enable
TX
FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
0 1 1 LCR RD/WR Divisor
Enable Set TX
Break Set Par-
ity Even
Parity Parity
Enable Stop
Bits Word
Length
Bit-1
Word
Length
Bit-0
1 0 0 MCR RD/WR 000Internal
Loop-
back
Enable
OP2#/
INT
Output
Enable
Rsrvd
(OP1#) RTS#
Output
Control
DTR#
Output
Control
1 0 1 LSR RD RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty RX
Break RX
Fram-
ing
Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
1 1 0 MSR RD CD#
Input RI#
Input DSR#
Input CTS#
Input Delta
CD# Delta
RI# Delta
DSR# Delta
CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Baud Rate Generator Divisor
0 0 0 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 1
0 0 1 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
XR16C2550
17
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
4.3.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts ( IER BIT-0 = 1) are enabled, the RHR interrupt s
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be clear ed when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit ( LSR BIT-0) is set as soon as a character is transferred from th e shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16C2550 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting resp ective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates Transmit FIFO is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
•Logic 0 = Disable the receive data ready interrupt (default).
•Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
•Logic 0 = Disable Transmit Ready interrupt (default).
•Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
•Logic 0 = Disable the receiver line status interrupt (default).
•Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
•Logic 0 = Disable the modem status register interrupt (default).
•Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
XR16C2550
18
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
4.4 Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 8, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
•LSR is by any of the LSR bits 1, 2, 3 and 4.
•RXRDY is by RX trigger level.
•RXRDY Time-out is by a 4-char plus 12 bits delay timer.
•TXRDY is by TX FIFO empty.
•MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2 Interrupt Clearing:
•LSR interrupt is cleared by a read to the LSR register.
•RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
•RXRDY Time-out interrupt is cleared by reading RHR.
•TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
•MSR interrupt is cleared by a read to the MSR register.
]
ISR[0]: Interrupt Status
•Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine .
•Logic 1 = No interrupt pending (default).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 8).
ISR[5:4]: Reserved
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL ISR REGISTER STATUS BITS SOURCE OF INTERRUPT
BIT-3 BIT-2 BIT-1 BIT-0
1 0 1 1 0 LSR (Receiver Line Status Register)
2 1 1 0 0 RXRDY (Receive Data Time-out)
3 0 1 0 0 RXRDY (Received Data Ready)
4 0 0 1 0 TXRDY (Transmit Ready)
5 0 0 0 0 MSR (Modem Status Register)
- 0 0 0 1 None (default)
XR16C2550
19
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
4.5 FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
•Logic 0 = Disable the transmit and receive FIFO (default) .
•Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•Logic 0 = No receive FIFO reset (default)
•Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•Logic 0 = No transmit FIFO reset (default).
•Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for det ails.
•Logic 0 = Normal Operation (default).
•Logic 1 = DMA Mode.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the char acters in the FIFO c rosse s t he trig ge r lev el. Table 9 shows the complete selections.
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
TABLE 9: RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7 FCR
BIT-6
RECEIVE
TRIGGER
LEVEL COMPATIBILITY
0
0
1
1
0
1
0
1
1 (default)
4
8
14
16C550, 16C2552 ,
16C554, 16C580 com-
patible.
XR16C2550
20
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 10 for parity selection summary below.
•Logic 0 = No parity.
•Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity forma t.
•Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
•Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the sa me format.
BIT-1 BIT-0 WORD LENGTH
0 0 5 (default)
0 1 6
1 0 7
1 1 8
BIT-2 WORD
LENGTH STOP BIT LENGTH
(BIT TIME(S))
05,6,7,8 1 (default)
1 5 1-1/2
16,7,8 2
XR16C2550
21
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR bit-5 selects the forced parity format.
•LCR[5] = logic 0, parity is not forced (d efault).
•LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
•LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•Logic 0 = No TX break condition (default).
•Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors (DLL/DLM) Enable
•Logic 0 = Data registers are select ed (defa ult ).
•Logic 1 = Divisor latch registers are selected.
4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•Logic 0 = Force DTR# output to a logic 1 (default).
•Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•Logic 0 = Force RTS# output to a logic 1 (default).
•Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the 2550. But it is available for use during In ternal Loopbac k Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
TABLE 10: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3 PARITY SELECTION
X X 0 No parity
0 0 1 Odd parity
0 1 1 Even parity
1 0 1 Force parity to mark, “1”
1 1 1 Forced parity to space, “0”
XR16C2550
22
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be
used as a general purpose output.
•Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set to a logic 1 (default).
•Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# outpu t set to a logic 0.
MCR[4]: Internal Loopback Enable
•Logic 0 = Disable loopback mode (default).
•Logic 1 = Enable local loopback mode, see loopback section and Figure 11.
MCR[7:5]: Reserved
4.8 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART a nd the host.
LSR[0]: Receive Data Ready Indicator
•Logic 0 = No data in receive holding register or FIFO (default).
•Logic 1 = Data has been re ceived and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
•Logic 0 = No overrun error (default).
•Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error. An interrupt will be generated
immediately if LSR interrupt is enabled (IER bit-2).
LSR[2]: Receiv e Data Parity Error Flag
•Logic 0 = No parity error (default).
•Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RH R. If the LSR interrupt is enabled (IER
bit-2), an interrupt will be generated when the character is in the RHR.
LSR[3]: Receive Data Framing Error Flag
•Logic 0 = No framing error (default).
•Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. If the LSR interrupt is enabled (IER bit-2), an interrupt will be
generated when the character is in the RHR.
LSR[4]: Receive Break Flag
•Logic 0 = No break condition (default).
•Logic 1 = The receiver received a break signal (RX was a logi c 0 for at least one characte r frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1. If the LSR interrupt is enabled (IER bit-2), an interrupt will
be generated when the character is in the RHR.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a ne w ch arac ter f or tra nsmis sion. In a ddition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last d ata byte is transferred from
the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurre ntly with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty, it is cleared when the transmit FIFO conta ins at least 1 byte.
XR16C2550
23
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
•Logic 0 = No FIFO error (default).
•Logic 1 = A global indicato r for the sum of all er ror bit s in the RX FIFO. At least one parity error , framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
4.9 Modem Status Regist er (M SR) - Rea d On ly
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits
are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general
purpose inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
•Logic 0 = No change on CTS# input (default).
•Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
•Logic 0 = No change on DSR# input (default).
•Logic 1 = The DSR# in put has chan ged state since the last time it was monitor ed. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
•Logic 0 = No change on RI# input (default).
•Logic 1 = The RI# input has change d from a logi c 0 to a logic 1, ending of the ringi ng signal. A mode m st atus
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
•Logic 0 = No change on CD# input (default).
•Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is
equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when
the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. Th e RI# inpu t ma y be use d as a gen er al pu rp o se inp u t whe n the mo de m inte rfa ce is not us ed .
XR16C2550
24
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
MSR[7]: CD Input Status
Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16 -b it counte r that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’.
SEE”PROGRAMMABLE BAUD RATE GENERATOR” ON PAGE 9.
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS RESET STATE
DLM Bits 7-0 = 0xXX
DLL Bits 7-0 = 0xXX
RHR Bits 7-0 = 0xXX
THR Bits 7-0 = 0xXX
IER Bits 7-0 = 0x00
FCR Bits 7-0 = 0x00
ISR Bits 7-0 = 0x01
LCR Bits 7-0 = 0x00
MCR Bits 7-0 = 0x00
LSR Bits 7-0 = 0x60
MSR Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR Bits 7-0 = 0xFF
I/O SIGNALS RESET STATE
TX Logic 1
OP2# Logic 1
RTS# Logic 1
DTR# Logic 1
RXRDY# Logic 1
TXRDY# Logic 0
INT Three-State Condition
XR16C2550
25
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
ABSOLUTE MAXIMUM RATINGS
Power Supply Range 7 Volts
Voltage at Any Pin GND-0.3 V to VCC+0.3 V
Operating Temperature -40o to +85oC
Storage Temperature -65o to +150oC
Package Dissipation 500 mW
PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (48-TQFP) theta-ja =59oC/W, theta-jc = 16oC/W
Thermal Resistance (44-PLCC) theta-ja = 50oC/W, theta-jc = 21oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC = 2.97V TO 5.5V
SYMBOL PARAMETER
3.3V
LIMITS
MIN MAX
5.0V
LIMITS
MIN MAX
UNITS CONDITIONS
VILCK Clock Input Low Level -0.3 0.6 -0.5 0.6 V
VIHCK Clock Input High Level 2.4 5.5 3.0 5.5 V
VIL Input Low Voltage -0.3 0.8 -0.5 0.8 V
VIH Input High Voltage 2.0 5.5 2.2 5.5 V
VOL Output Low Voltage 0.4 0.4 V
VIOL = 6 mA
VOH Output High Voltage 2.0 2.4 V
VIOL = 4 mA
IIL Input Low Leakage Current ±10 ±10 uA IOH = -6 mA
IIH Input High Leakage Current ±10 ±10 uA IOH = -1 mA
CIN Input Pin Capacitance 5 5 pF
ICC Power Supply Current 1.3 3mA
XR16C2550
26
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS
TA=-40O TO +85OC, VCC = 2.97V TO 5.5V, 70 PF LOAD WHERE APPLICABLE
SYMBOL PARAMETER 3.3
LIMITS
MIN MAX
5.0
LIMITS
MIN MAX UNIT COMMENTS
-Crystal Frequency 20 24 ns
CLK Clock Pulse Duration 17 8ns
OSC External Clock Frequency 30 64 MHz
TAS Address Setup T im e 5 0 ns
TAH Address Hold Time 10 5ns
TCS Chip Select Width 70* 40 ns * 55ns if VCC =
3.3V +10%/-5%
and
TA = 0 to 70oC
(See Figure 12)
TRD IOR# Strobe Width 70* 40 ns
TDY Read or Write Cycle Delay 70* 40 ns
TRDV Data Access Time 35 25 ns
TDD Data Disable Time 025 015 ns
TWR IOW# Strobe Width 40 25 ns
TDS Data Setup Time 20 15 ns
TDH Data Hold Time 5 5 ns
TWDO Delay From IOW# To Output 50 40 ns
TMOD Delay To Set Interrupt From MODEM
Input 40 35 ns
TRSI Delay To Reset Interrupt From IOR# 40 35 ns
TSSI Delay From Stop To Set Inte rrupt 1 1 Bclk
TRRI Delay From IOR# To Reset Interrupt 45 40 ns
TSI Delay From Start To Interrupt 45 40 ns
TINT Delay From Initial INT Reset To Transmit
Start 824 824 Bclk
TWRI Delay From IOW# To Reset Interrupt 45 40 ns
TSSR Delay From Stop To Set RXRDY# 1 1 Bclk
TRR Delay From IOR# To Reset RXRDY# 45 40 ns
TWT Delay From IOW# To Set TXRDY# 45 40 ns
TSRT Delay From Center of Start To Reset
TXRDY# 8 8 Bclk
TRST Reset Pulse Width 40 40 ns
NBaud Rate Divisor 1216-1 1216-1 -
Bclk Baud Clock 16X of data rate Hz
XR16C2550
27
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
a
FIGURE 12. AC TIMING VALUES
FIGURE 13. CLOCK TIMING
48
53
63
70
27
34
40
16
22 25
55
26
0
10
20
30
40
50
60
70
80
Temperat ure (deg C)
Time (ns)
TCS, TRD, TDY: 3.3V +10%/- 5%
TCS, TRD, TDY: 3.3V ± 10%
TWR: 3.3V ± 10%
TCS, TRD, TDY: 5V ± 10%
TWR: 5V ± 10%
-40 25 70 85
OSC
CLK
CLK
EXTERNAL
CLOCK
XR16C2550
28
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
FIGURE 15. DATA BUS READ TIMING
IOW#
RTS#
DTR#
CD#
CTS#
DSR#
INT
IOR#
RI#
TWDO
TMOD TMOD
TRSI
TMOD
Active
Active
Change of state Change of state
Active Active Active
Chan ge of state Change of state
Change of state
Active Active
TAS
TDD
TAH
TRD
TRDV
TDY
TDD
TRDV
TAH
TAS TCS
Valid Address Valid Address
Valid Da ta Valid D a ta
A0-A2
CSA#/
CSB#
IOR#
D0-D7
RDTm
TCS
TRD
XR16C2550
29
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
FIGURE 16. DATA BUS WRITE TIMING
FIGURE 17. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
16Write
TAS
TDH
TAH
TWR
TDS
TDY
TDH
TDS
TAH
TAS TCS
Valid Address Valid Address
Valid Data Valid Data
A0-A2
CSA#/
CSB#
IOW#
D0-D7
TCS
TWR
RX
RXRDY#
IOR#
INT
D0:D7
Start
Bit D0:D7
Stop
Bit D0:D7
TSSR
1 Byte
in RHR
Active
Data
Ready
Active
Data
Ready
Active
Data
Ready
1 Byte
in RHR 1 Byte
in RHR
TSSR TSSR
RXNFM
TRR TRR TRR
TSSR TSSR TSSR
(Reading data
out of RHR)
XR16C2550
30
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
D0:D7
Start
Bit D0:D7
Stop
Bit D0:D7
TWT
TXNonFIFO
TWT TWT
TWRI TWRI TWRI
TSRT TSRT TSRT
*INT is cleared when the ISR is read or when data is loaded into the THR.
ISR is read ISR is readISR is read
(Loading data
into THR)
(Unloading)
IER[1]
enabled
RX
RXRDY#
IOR#
INT
D0:D7
S
TSSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
First Byte is
Received in
RX FIFO
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit
Stop
Bit
TRR
TRRI
TSSI
(Reading data out
of RX FIFO)
XR16C2550
31
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
S
TSSR
RXFIFODMA
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below R X
Trigger Level
FIFO
Empties
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit Stop
Bit
TRR
TRRI
TSSI
(Reading da ta out
of RX FIFO)
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit Stop
Bit
TWRI
(Unloading)
(Loading d ata
into FIFO)
Last Data Byte
Transmitted
TX FIFO no
longer empty
Data in
TX FIFO
TX FIFO
Empty
TWT
TSRT
TX FIFO
Empty
T
TS
TSI
ISR is read
IER[1]
enabled
*INT is cleare d when t he I S R i s r ead or when th er e i s at lea s t on e c h ar acter i n t h e F IFO.
XR16C2550
32
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
TXDMA
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit Stop
Bit
TWRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO no
longer empty
TX FIFO
Empty
TX FIFO
Empty
T
TS
TSI
ISR is read
IER[1]
enabled
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
At least 1
empty loc at ion
in FIFO
TSRT
TX FIFO
Full
TWT
XR16C2550
33
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.039 0.047 1.00 1.20
A1 0.002 0.006 0.05 0.15
A2 0.037 0.041 0.95 1.05
B0.007 0.011 0.17 0.27
C0.004 0.008 0.09 0.20
D0.346 0.362 8.80 9.20
D1 0.272 0.280 6.90 7.10
e0.020 BSC 0.50 BSC
L0.018 0.030 0.45 0.75
α0°7°0°7°
36 25
24
13
11
2
37
48
D
D
1
D
D
1
B
e
α
A
2
A
1
A
Seating
Plane
L
C
XR16C2550
34
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
PACKAGE DIMENSIONS (44 PIN PLCC)
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.165 0.180 4.19 4.57
A1 0.090 0.120 2.29 3.05
A2 0.020 --- 0.51 ---
B0.013 0.021 0.33 0.53
B10.026 0.032 0.66 0.81
C0.008 0.013 0.19 0.32
D0.685 0.695 17.40 17.65
D1 0.650 0.656 16.51 16.66
D20.590 0.630 14.99 16.00
D30.500 typ. 12.70 typ.
e0.050 BSC 1.27 BSC
H10.042 0.056 1.07 1.42
H20.042 0.048 1.07 1.22
R0.025 0.045 0.64 1.14
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
1
D
D
1
A
A
1
D D
1
D
3
B
A
2
B
1
e
Seating Plane
D
2
244
D
3
C
R
45
°
x H
2
45
°
x H
1
35
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits descr ibed herein , conveys no license unde r any p atent or other ri ght, and makes no represent ation th at
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user ’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect it s safety or effectiveness. Products ar e not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected un de r the circumstances.
Copyright 2007 EXAR Corporation
Datasheet February 2007.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
XR16C2550
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REVISION HISTORY
Date Revision Description
December 2004 1.0.0 Initial Datasheet. This datasheet applies to devices with top mark date code of "B2
YYWW" and newer.
January 2005 1.0.1 Clarified AC Electrical Characteristics.
February 2007 1.0.2 40-pin PDIP package is no longer offered and has been removed from the ordering
information.
XR16C2550 xr
REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
I
5.0 TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS................................................................................................................................................1
FEATURES .....................................................................................................................................................1
FIGURE 1. XR16C2550 BLOCK DIAGRAM......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION.................................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION .....................................................................................................................6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................7
2.1 CPU INTERFACE .............................................................................................................................................. 7
FIGURE 3. XR16C2550 DATA BUS INTERCONNECTIONS ................................................................................................................. 7
2.2 DEVICE RESET ................................................................................................................................................ 7
2.3 CHANNEL A AND B SELECTION .................................................................................................................... 7
TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 7
2.4 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8
2.5 DMA MODE ....................................................................................................................................................... 8
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE............................................................................................. 8
2.6 INTA AND INTB OUTPUTS .............................................................................................................................. 8
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 8
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................... 8
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ............................................................................. 9
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 9
2.8 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 9
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE.......................................................................................... 10
FIGURE 6. OPERATING FREQUENCY VERSUS POWER SUPPLY CHART.............................................................................................. 10
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 11
2.9 TRANSMITTER ............................................................................................................................................... 11
2.9.1 TRANSMIT HOLDING REGISTER (TH R) - WRITE ONLY......................................................................................... 11
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................. 11
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 12
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 12
FIGURE 8. TRANSMITTER OPERATION IN FIFO MODE...................................................................................................................... 12
2.10 RECEIVER .................................................................................................................................................... 12
2.10.1 RECEIVE HOLDING REGISTER (RHR) - REA D-ONLY .......................................................................................... 13
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 13
FIGURE 10. RECEIVER OPERATION IN FIFO MODE.......................................................................................................................... 13
2.11 INTERNAL LOOPBACK ............................................................................................................................... 14
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B .................... ..................... ..................... .................... ..................... ......... 14
3.0 UART INTERNAL REGISTERS ...........................................................................................................15
TABLE 6: UART CHANNEL A AND B UART INTERNAL REGISTERS...................................................................................... 15
TABLE 7: INTERNAL REGISTERS DESCRIPTION................................................................................................................... 16
4.0 INTERNAL REGISTER DESCRIPTIO NS ... ... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... .... ...16
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 16
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ................... ................. ........................................ 16
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 16
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 17
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 17
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 18
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 18
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 18
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 18
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 19
TABLE 9: RECEIVE FIFO TRIGGER LEVEL SELECTION ..................................................................................................................... 19
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 19
TABLE 10: PARITY SELECTION ........................................................................................................................................................ 21
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 21
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 22
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 23
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 24
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 24
xr XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.0.2
II
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 24
ABSOLUTE MAXIMUM RATINGS ..................................................................................25
PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)................25
ELECTRICAL CHARACTERISTICS................................................................................25
DC ELECTRICAL CHARACTERISTICS..............................................................................................................25
AC ELECTRICAL CHARACTERISTICS..............................................................................................................26
TA=-40o to +85oC, Vcc = 2.97V to 5.5V, 70 pF load where applicable....................................................................26
FIGURE 12. AC TIMING VALUES ..................................................................................................................................................... 27
FIGURE 13. CLOCK TIMING............................................................................................................................................................. 27
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B................................................................................................. 28
FIGURE 15. DATA BUS READ TIMING.............................................................................................................................................. 28
FIGURE 16. DATA BUS WRITE TIMING ............................................................................................................................................ 29
FIGURE 17. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 29
FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 30
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 30
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 31
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 31
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 32
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)................................................33
PACKAGE DIMENSIONS (44 PIN PLCC).......................................................................34
REVISION HISTORY............................................................................................................................ 35
5.0 TABLE OF CONTENTS ..........................................................................................................................I
