XRD5408/10/12
5V,LowPower,Voltage Output
Serial8/10/12-BitDACFamily
Rev.1.20
EXAR Corporation,48720 KatoRoad,Fremont, CA94538 z(510)668-7000 z(510)668-7017
E2000
May2000-2
FEATURES
D8/10/12-BitResolution
DOperatesfromaSingle 5V Supply
DBuffered Voltage Output: 13msTypicalSettling Time
D240mWTotalPowerConsumption (typ)
DGuaranteed MonotonicOverTemperature
DFlexibleOutputRange:0VtoVDD
D8 Lead SOICand PDIP Package
DPowerOnReset
DSerialDataOutput forDaisy Chaining
APPLICATIONS
DDigitalCalibration
DBatteryOperated Instruments
DRemoteIndustrialDevices
DCellularTelephones
DMotion Control
GENERALDESCRIPTION
The XRD5408/10/12 arelowpower,voltage output
digital-to-analog converters(DAC)for+3Vpowersupply
operation.The partsdrawonly70mAofquiescentcurrent
and are availablein both an 8-lead PDIPand SOIC
package.
The XRD5408/10/12 havea3wireserialportwith an
outputallowing the userto daisy chainseveralof them
together.The serialportwill supportbothMicrowiret,
SPIt,and QSPItstandards.
The outputsof the XRD5408/10/12 aresetata gain of+2.
The outputshortcircuitcurrentis7mAtypical.
ORDERINGINFORMATION
PartNo.PackageOperating
TemperatureRange
XRD5408AID8 Lead 150 Mil JEDECSOIC-40°Cto+85°C
XRD5408AIP8 Lead 300 Mil PDIP-40°Cto+85°C
XRD5410AID8 Lead 150 Mil JEDECSOIC-40°Cto+85°C
XRD5410AIP8 Lead 300 Mil PDIP-40°Cto+85°C
XRD5412AID8 Lead 150 Mil JEDECSOIC-40°Cto+85°C
XRD5412AIP8 Lead 300 Mil PDIP-40°Cto+85°C
XRD5408/10/12
2
Rev.1.20
BLOCK DIAGRAM
Figure 1.Block Diagram
Shift Register
-
+
VREFIN
VDD
CS
SCLK
SDIN
PowerOn
Reset
Switch
Matrix
AGND VDD
DOUT
VOUT
R R
2n
PIN CONFIGURATION
VDD
VOUT
VREFIN
AGND
SDIN
SCLK
CS
DOUT
8LeadSOIC(Jedec,0.150”)
81
54
2
3
7
6
8LeadPDIP(0.300”)
VDD
VOUT
VREFIN
AGND
SDIN
SCLK
CS
DOUT
1
2
3
4
8
7
6
5
PIN DESCRIPTION
Pin#SymbolDescription
1SDINSerialDataInput
2SCLK SerialDataClock
3CSChipSelect(ActiveHigh)
4DOUTSerialDataOutput
5AGND Analog Ground
6VREFINVoltage ReferenceInput
7VOUTDACOutput
8VDD SupplyVoltage
XRD5408/10/12
3
Rev.1.20
ELECTRICALCHARACTERISTICS
TestConditions:VDD=5V,GND=0V,REFIN=2.048V(External),RL=10kW,CL=100pF,TA=TMINto TMAX,
Unless Otherwise Noted.
SymbolParameterMin.Typ.Max.UnitConditions
StaticPerformance XRD5408
N Resolution 8 Bits
INLRelativeAccuracy 0.25 0.5 LSB
DNLDifferentialNonlinearity0.25 0.5±LSB Guaranteed Monotonic
VOSOffsetError038mV
TCVOSOffsetTempco 2 ppm/°C
PSRR Offset-ErrorPower-Supply
Rejection Ratio0.5 1 mV4.5V±VDD ±5.5V
GEGainError0.1 0.4%FS
TCGEGain-ErrorTempco 10 ppm/°C
PSRR Power-Supply
Rejection Ratio0.1 1.25 mV4.5V±VDD ±5.5V,Measured at
FS
StaticPerformance XRD5410
N Resolution 10 Bits
INLRelativeAccuracy 0.5 1 LSB
DNLDifferentialNonlinearity0.25 0.5±LSB Guaranteed Monotonic
VOSOffsetError038mV
TCVOSOffsetTempco 2 ppm/°C
PSRR Offset-ErrorPower-Supply
Rejection Ratio0.5 1 mV4.5V±VDD ±5.5V
GEGainError0.1 0.4%FS
TCGEGain-ErrorTempco 10 ppm/°C
PSRR Power-Supply
Rejection Ratio0.1 1.25 mV4.5V±VDD ±5.5V,Measured at
FS
StaticPerformance XRD5412
N Resolution 12 Bits
INLRelativeAccuracy 2 4 LSB
DNLDifferentialNonlinearity0.5-1 LSB Guaranteed Monotonic
+1.25 LSB
VOSOffsetError038mV
TCVOSOffsetTempco 2 ppm/°C
PSRR Offset-ErrorPower-Supply
Rejection Ratio0.5 1 mV4.5V±VDD ±5.5V
GEGainError0.1 0.4%FS
TCGEGain-ErrorTempco 10 ppm/°C
PSRR Power-Supply
Rejection Ratio0.1 1.25 mV4.5V±VDD ±5.5V,Measured at
FS
XRD5408/10/12
4
Rev.1.20
ELECTRICALCHARACTERISTICS(CONT’D)
TestConditions:VDD=5V,GND=0V,REFIN=2.048V(External),RL=10kW,CL=100pF,TA=TMINto TMAX,
Unless Otherwise Noted.
SymbolParameterMin.Typ.Max.UnitConditions
VoltageOutput (VOUT)XRD5408/10/12
VOOutputVoltage Range 0 VDD--0.4V
VREGOutputLoad Regulation 2 4 mV VOUT=2V,RL=2kW
+ISCShort-CircuitCurrent, Sink13 mA VOUT=VDD
-ISCShort-CircuitCurrent, Source 7 mA VOUT=GND
VoltageReference Input (VREFIN)XRD5408/10/12
VREFINVoltage Range 0 VDD VOutputSwing Limited,NotCode Dependent
RINInputResistance 40 65 kW
TCRINInputResistanceTempco 1500 ppm/°C
CINInputCapacitance 32 40 pFNotCode Dependent
ACFT ACFeedthrough -80 dBREFIN=1kHz,2Vp-p,SDIN=000h
Digital Inputs(SDIN,SCLK,CS)XRD5408/10/12
VIHInputHigh 3.5V
VILInputLow1V
IINInputCurrent±1mA VIN=0VorVDD
CINInputCapacitance 10 pF
DigitalOutput (DOUT)XRD5408/10/12
VOHOutputHigh VDD-1VISOURCE=4mA
VOLOutputLow0.4VISINK=4mA
DynamicPerformance XRD5408/10/12
SRVoltage-OutputSlew Rate 0.13 0.21 V/msTA=+25°C
tsVoltage-OutputSettling Time 13 15 ms±1/2LSB,VOUT=2V
DFT DigitalFeedthrough 1 nV-sCS=VDD,SDIN=SCLK=100kHz
SINADSignal-to-NoisePlusDistortion 68 dB VREFIN=1kHz,2Vp-pF.S., SDIN=Full
Scale,--3dB BW=250kHz
PowerSupplyXRD5408/10/12
VDD PositiveSupplyVoltage 4.5 5.5V
IDD PowerSupplyCurrent35 60 mA All Inputs=0VorVDD,Output=No Load,
IREFNot Included,VO=0V(Note1)
Switching Characteristics XRD5408/10/12
tCSS CS Setup Time 10 20 ns
tCSH0SCLKFall toCSFall HoldTime 5 ns
tCSH1SCLKFall toCSRiseHoldTIme 0 ns
tCH SCLKHigh Width 20 35 ns
tCLSCLKLowWidth 20 35 ns
Notes:
1Totalsupply currentconsumption =IDD +IREF+(VO/70K.)
XRD5408/10/12
5
Rev.1.20
ELECTRICALCHARACTERISTICS(CONT’D)
TestConditions:VDD=5V,GND=0V,REFIN=2.048V(External),RL=10kW,CL=100pF,TA=TMINto TMAX,
Unless Otherwise Noted.
SymbolParameterMin.Typ.Max.UnitConditions
tDSDINSetup Time 10 45 ns
tDH DINHoldTime 0 ns
tDODOUTValidPropagation Delay8 15 nsCL=50pF
tCSWCSHigh PulseWidth 20 40 ns
tCS1CSRisetoSCLKRiseSetup
Time10 20 ns
Specifications are subject tochangewithoutnotice
ABSOLUTEMAXIMUMRATINGS
VDD toGND -0.3V,+7V..........................
DigitalInputVoltage toGND -0.3V,VDD +0.3V. . . . . .
VREFIN-0.3V,VDD +0.3V.........................
VOUT1VDD,GND...............................
ContinuousCurrent, AnyPin-20mA,+20mA. . . . . . . .
Package PowerDissipation Ratings(TA= +70°C)
PDIP(derate 9mW/°Cabove+70°C)117mW. . . .
SOIC(derate 6mW/°Cabove+70°C)155mW. . .
Operating TemperatureRange -40°Cto+85°C. . . . .
Storage TemperatureRange -65°Cto+165°C. . . . . .
Lead Temperature(soldering,10 sec)+300°C. . . . . .
Notes
1Stressesabovethoselisted under “AbsoluteMaximumRatings”may cause permanentdamage tothe device.Thisisa
stress rating onlyand functionaloperation atorabovethis specification isnotimplied.Exposuretomaximumrating
conditionsforextended periodsmayaffectdevicereliability.
2Anyinputpinwhichcan seeavalue outside the absolutemaximumratings should be protected bySchottky diode clamps
(HP5082-2835)frominputpintothe supplies.All inputshave protection diodeswhichwill protect the devicefromshort
transientsoutside the suppliesofless than 100mAforless than 100ms.
XRD5408/10/12
6
Rev.1.20
TIMING
CS
SCLK
SDIN
DOUT
tCSW
tCS1
tCSH1
tCL
tD0
tDH
tDS
tCH
tCSS
tCSH0
Figure 2.Timing Diagram
InputOutput
1111 1111 (0000)
1000 0001 (0000)
1000 0000 (0000)
0111 1111 (0000)
0000 0001 (0000)
0000 0000 (0000)0V
Note:
Write 8-bitdatawordswithfoursub-LSB 0sbecausethe DACinputlatch
is12 bitswide.
Table 1.BinaryCodeTable
+2(VREFIN)127
256
+2(VREFIN)129
256
+2(VREFIN)255
256
+2(VREFIN)128
256 = + VREFIN
+2(VREFIN)1
256
XRD5408/10/12
7
Rev.1.20
THEORYOFOPERATION
XRD5408/10/12 Description
The XRD5408/10/12 aremicro-power,voltage output,
serialdaisy-chain programmableDACsoperating froma
single 5Vpowersupply.The DACsare builton a 0.6
micron CMOSprocess.The featuresof theseDACs
makeitwell suited forindustrialcontrol,lowdistortion
audio,batteryoperated devicesand costsensitive
designsthatwant tominimize pincounton ICs.
ResistorString DAC
Aresistorstring architectureconvertsdigitaldata using a
switchmatrixto an analog signalas showninFigure 3.
Figure 3.XRD5408/10/12 DAC Architecture
Shift Register
-
+
VREFIN
VDD
CS
SCLK
SDIN
PowerOn
Reset
Switch
Matrix
AGND VDD
DOUT
VOUT
R R
2n
The resistorstring architecture providesa non-inverted
outputvoltage (VOUT)of the referenceinput(VREFIN)for
singlesupplyoperation whilemaintaining a constantinput
resistance.Unlikeinverted R-2Rarchitecturesthe
referenceinputresistancewill remainconstant
independentofcode.Thisgreatly simplifiesthe analog
driving sourcerequirementsforthe referencevoltage and
minimizesdistortion.Similarlyinputcapacitancevaries
onlyapproximately4pFoverall codes.
FixedGain+2VoltageOutputAmplifier
Ahigh open-loop gain operationalamplifierbuffersthe
resistorstring with a stable, fixed gain of+2.The voltage
outputwill settlewithin 13s.The outputis shortcircuit
protected and can regulate an outputload of2Vinto 2k
within 2mVat25°C.
Whilethe referenceinputwill acceptavoltage from
rail-to-rail, the linearinputvoltage range is constrained by
the outputswing of the fixed +2closed-loop gain amplifier.
Full scale outputswing isachieved with an external
reference ofapproximately1/2VDD.The reference
voltage mustbe positive becausethe XRD5408/10/12
DACisnon-inverting.
SerialDaisy-ChainableDigital Interface
The three wireserial interfaceincludesaDOUTto enable
daisy-chaining ofseveralDACs.Thisminimizespin
countnecessaryofdigitalasics orcontrollersto address
multipleDACS.The serial interfaceisdesigned for
CMOSlogiclevels.Timing is showninFigure 2.The
binary coding table(Table 1)showsthe DACtransfer
function.
Apoweron resetcircuit forcesthe DACtoreset to all “0”s
on powerup.
APPLICATION NOTES
Serial Interface
The XRD5408/10/12 familyhasathree wireserial
interfacethatis compatiblewithMicrowiret,SPItand
QSPItstandards.Typicalconfigurationsareshownin
Figure 4 and Figure 5.Maximumserialportclock rateis
limited bythe minimumpulsewidth of tCH and tCL.
Feedthrough noisefromthe serialport tothe analog
output(VOUT)isminimized bylowering the frequency of
the serialportand holding the digitaledgesto>5ns.
XRD5408/10/12
8
Rev.1.20
Microwiret
Port
SK
SO
I/O
SCLK
SDIN
CS
VOUT
GND VDD
VREFIN
XRD5412
1.25V
MP5010
+5V
0-2.5V
+5V
0.1mF
Figure 4.TypicalMicrowiretApplication Circuit
SPIt
Port
SK
MOSI
I/O
SCLK
SDIN
CS
VOUT
GND VDD
VREFIN
XRD5410
1.25V
MP5010
+5V
0-2.5V
+5V
0.1mF
Figure 5.TypicalSPItApplication Circuit
XRD5408/10/12
9
Rev.1.20
Figure 6.Shift RegisterFormat
DOUT
SDINX X X X
DAC
MSB
n
The DACsare programmedbya 16 bitword ofserialdata.
The formatof the serial inputregisteris showninFigure 6.
The leading 4 bitsare notused to updatethe DAC. If the
DACisnotdaisy-chained then onlya 12 bitserialwordis
needed to programthe DAC.The next8,10 or12 bits
afterthe 4 leading bitsare data bits.The XRD5408’sfirst
8 bitsarevalid data and the trailing 4 bitsmustbe set to 0.
Figure 7 demonstratesthe 16 bitdigitalwordforthe 8,
10,12 bitDACs.
Part
Leading
Unused
Bits
DataBits
MSBLSB
Trailing
“0”
Bits
XRD5412 XXXX XXXXXXXX None
XRD5410 XXXX XXXXXXXX 00
XRD5408 XXXX XXXXXXXX 0000
Table 2.16-BitDigitalWordRegisterforXRD5408,
XRD5410,XRD5412.
SCLKshould be heldlow when CStransitionslow.Datais
clocked inonthe rising edge ofSCLKwhen CSislow.
SDINdataisheldin a 16 bitserialshift register.The DAC
isupdated withthe data bitson the rising edge ofCS.
When CSishigh dataisnotshifted intothe
XRD5408/10/12.
Daisy-Chaining
The digitaloutputport(DOUT)hasa 4mAdriveforgreater
fan-outcapabilitywhen daisy-chaining.DOUTallows
cascading ofmultipleDACswiththe sameserialdata
stream.The data atSDINappearsatDOUTafter16 clock
cyclesplusone clock width(tCH)and a propagation delay
(tDO).DOUTremainsinthe state of the lastdata bitwhen
CSishigh.DOUTchangeson the falling edge ofSCLK
when CSislow.
AnynumberofDACs can be connected inthiswayby
connecting DOUTofone DACtoSDINof the nextDAC.
ACFT Feedthrough (DAC Code=0)
ACFeedthrough fromVREFINtoVOUTisminimized with
lowimpedance grounding as showninFigure 7. If the
DACdatais set to all “0”sthen VOUTisafunction of the
dividerbetween the DACstring impedance and ground
impedance.See the PowerSupplyand Grounding
section for recommendations.The typicalAC
feedthrough fora 1kHz2Vpp signalwithcode =0is
-80dB.
Figure 7.ACFT Feedthrough Equivalent
Circuit,DAC Code=0
VREFIN
XRD5408/10/12
VOUT
GND
RGND
Analog GND
RIN
--
+
CompatiblewithMAX515 &MAX539
The XRD5408/10/12 familyofDACsarefunctionally
campatiblewiththe MAX515 &MAX539 while providing
significantimprovements.The XRD5408/10/12 DACs
havelowerpower, fasterserialports,and a constant
referenceimpedancetominimizethe reference driving
requirementsand maximizesystemlinearity.The DOUT
XRD5408/10/12
10
Rev.1.20
portalso has4mAdriving capabilityforgreaterfan-out
when daisy-chaning to otherdigital inputs.
Monotonicity
The XRD5408/10/12 familyofDACsaremonotonicover
the entiretemperaturerange.
Micro-PowerOperation
The XRD5408 isthe lowestpowerintheirclass.The
quiescentcurrentrating doesnotinclude the reference
laddercurrent. Powercan be saved whenthe partisnotin
use by setting the DACcode to all “0”sassuming the
outputload isreferenced to ground.Thisminimizesthe
DACoutputload current. An analog switch placed in
serieswiththe referenceladdercan togglethe reference
voltage off when the circuitisinactivetominimize power
consumption.
PowerSupply and Grounding
Bestparametricresultsare obtained bypowering the
XRD5408/10/12 familyofDACsfroman analog +5V
powersupplyand analog ground.Digitalpowersupplies
and grounds shouldbeseparated orconnected tothe
analog suppliesand groundsonlyat the low-impedance
power-supply source.Thisisbestaccomplished on a
multilayerPCBwith dedicated planesto ground and
power.The DACs should be locallybypassed with both
0.1Fand 2.2Fcapacitorsmounted as close aspossible
tothe powersupplypin(VDD).Surfacemountceramic
capacitorsarerecommended forlowimpedance,wide
band powersupplybypass. If onlyone +5Vpowersupply
isavailableforboth analog and digitalcircuityisolatethe
analog powersupplytothe XRD5408/10/12 DAC with an
inductororferrite bead beforethe localbypass
capacitors.
PERFORMANCECHARACTERISTICS
Figure 8.XRD5408 INL
Figure 9.XRD5408 DNL
LSB
CODE
LSB
CODE
--0.2
0
0.2
0.4
0 64 128 192
--0.1
0.0
0.2
0.35
255
0 64 128 192 255
XRD5408/10/12
11
Rev.1.20
Figure 10.OutputSource Current
vs.OutputVoltage
0 50.5V/div
10
1mA/div
0
0 10.1V/div
Figure 11.OutputSinkCurrent
vs.OutputVoltage
Figure 12.OutputSink and Source Cur-
rentvs.OutputVolatge
0
1.5mA/div
--15
500.1V/div
7
0
2mA/div
--14
IO(mA)
VOUT(V)
IO(mA)
IO(mA)
VOUT(V)
VOUT(V)
XRD5408/10/12
12
Rev.1.20
VOUT
CS
Figure 13.VoltageOutputSettling Time(ts),
VDD =5V,VREFIN=1V,No Load
20
22
24
26
28
30
32
34
36
38
40
-40 -20 0 20 40 60 80 100
Temp(°C)
Figure 14. IDD vs.Temperature
IDD A)(
XRD5408/10/12
13
Rev.1.20
Figure 15.Closed Loop Gainvs.Frequency
-2
-1
0
1
2
3
4
5
6
7
8
10 100 1000
Frequency (KHz)
Gain (dB)
Figure 16.Closed Loop Phase vs.Frequency
-120
-100
-80
-60
-40
-20
0
10 100 1000
Frequency (KHz)
Phase ( )
°
MicrowiretisatrademarkofNationalSemiconductorCorproation.
SPItand QSPItaretrademarks ofMotorolaCorporation.
XRD5408/10/12
14
Rev.1.20
SYMBOLMINMAXMINMAX
A0.053 0.069 1.35 1.75
A10.004 0.010 0.10 0.25
B0.013 0.020 0.33 0.51
C0.007 0.010 0.19 0.25
D0.189 0.197 4.80 5.00
E0.150 0.157 3.80 4.00
e 0.050 BSC1.27 BSC
H0.228 0.244 5.80 6.20
L 0.016 0.050 0.40 1.27
a0°8°0°8°
INCHES MILLIMETERS
8LEAD SMALL OUTLINE
(150 MILJEDECSOIC)
Rev.1.00
e
8 5
4
D
EH
B
A
L
C
A1
Seating
Planea
Note:The controldimension isthe millimetercolumn
XRD5408/10/12
15
Rev.1.20
8LEAD PLASTIC DUAL-IN-LINE
(300 MILPDIP)
Rev.2.00
8
1
5
4
D
A1
E1
E
A
L
Seating
Plane
SYMBOLMINMAXMINMAX
INCHES
A0.145 0.210 3.68 5.33
A10.015 0.070 0.38 1.78
A20.115 0.195 2.92 4.95
B0.014 0.024 0.36 0.56
B10.030 0.070 0.76 1.78
C0.008 0.014 0.20 0.38
D0.348 0.430 8.84 10.92
E0.300 0.325 7.62 8.26
E10.240 0.280 6.10 7.11
e 0.100 BSC2.54 BSC
eA0.300 BSC7.62 BSC
eB0.310 0.430 7.87 10.92
L 0.115 0.160 2.92 4.06
a0°15°0°15°
MILLIMETERS
A2
a
eB
C
eB1
B
Note:The controldimension isthe inchcolumn
eA
XRD5408/10/12
16
Rev.1.20
NOTICE
EXAR Corporation reservesthe right tomakechangestothe products contained inthispublication in ordertoim-
prove design,performance or reliability.EXAR Corporation assumesno responsibilityforthe use ofany circuitsde-
scribed herein,conveys no license underanypatentorother right, and makesno representation that the circuitsare
free ofpatentinfringement. Chartsand schedules contained herein are onlyforillustration purposesand may vary
depending upon a user’s specificapplication.Whilethe information inthispublication hasbeen carefully checked;
no responsibility,however,isassumed forinaccuracies.
EXAR Corporation doesnotrecommend the use ofanyofitsproductsinlifesupportapplicationswherethe failure or
malfunction of the productcan reasonablybe expected tocausefailure of the lifesupportsystemortosignificantly
affectits safetyoreffectiveness.Productsare notauthorized foruseinsuch applicationsunless EXAR Corporation
receives,inwriting,assurancestoits satisfaction that: (a)the risk ofinjuryordamage hasbeen minimized;(b)the
userassumesall suchrisks;(c)potential liabilityofEXAR Corporation isadequatelyprotected underthe circum-
stances.
All trademarks and registered trademarks are propertyof their respective owners.
Copyright2000 EXAR Corporation
DatasheetMay2000
Reproduction,in partorwhole,without the priorwritten consentofEXAR Corporation isprohibited.
