PF1245-01 Micro MINI S1C60N08/60R08 4-bit Single Chip Microcomputer ge oltan V o Lowerati ts p c u O od Pr S1C6200C Core CPU Built-in LCD Driver Serial Interface DESCRIPTION The S1C60N08 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200C, ROM (4,096 words x 12 bits), RAM (832 words x 4 bits), LCD driver, serial interface, event counter with dial input function, watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consumption, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems. The S1C60R08 is a microcomputer with a CMOS 4-bit core CPU S1C6200C as main component, and a built-in programmable RAM (ROM emulator). The S1C60R08 has almost the same functions as the S1C60N08/60A08. The mask ROM in the S1C60N08/60A08 has been changed to a ROM emulator that allows the user to rewrite programs using a Serial EEPROM. CONFIGULATION The S1C60N08 Series is configured as follows, depending on supply voltage and oscillation circuits. Model Supply voltage Oscillation circuit Evaluation tool S1C60N08 3.0 V OSC1 only (Single clock) S1C60A08 3.0 V OSC1 and OSC3 (Twin clock) S1C60R08 S1C60L08 1.5 V OSC1 only (Single clock) - FEATURES OSC1 oscillation circuit ................... Crystal oscillation circuit 32.768 kHz (Typ.)/38.400 kHz (Typ.) OSC3 oscillation circuit ................... CR or ceramic oscillation circuit (1) 500 kHz (Typ.) ...S1C60A08/60R08 only Instruction set .................................. 108 types Instruction execution time ............... CLK = 32.768 kHz: 153 sec, 214 sec, 366 sec (differs depending on instruction) CLK = 38.400 kHz: 130 sec, 182 sec, 313 sec (CLK: CPU operation frequency) CLK = 500 kHz: 10 sec, 14 sec, 24 sec...S1C60A08/60R08 only ROM capacity ................................. 4,096 words x 12 bits Serial EEPROM interface ............... Built-in (Microchip 24AA65 two wire bus protocol interfaces ...S1C60R08 only RAM capacity .................................. 832 words x 4 bits Input ports ....................................... 9 bits (pull-down resistor can be added 1) Output ports .................................... 8 bits (BZ, BZ, FOUT and SIOF outputs are available 1) I/O ports .......................................... 8 bits (pull-down resistor is added during input data read-out) Serial interface ................................ 1 port (8-bit clock synchronous system) LCD driver ....................................... 48 segments x 4, 3, or 2 commons (1) V-3 V 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in) Time base counter .......................... Two types (timer and stopwatch) Watchdog timer ............................... Built-in (1) 1 S1C60N08/60R08 Event counter .................................. Two 8-bit inputs (dial input evaluation or independent) Sound generator ............................. Programmable in 8 sounds (8 frequencies) Digital envelope built-in (1) Analog comparator.......................... Inverted input x 1, non-inverted input x 1 Battery low detection circuit (BLD) .. Dual system (programmable in 8 values and a fixed value) 2.4 V, 2.2-2.55 V ...S1C60N08/60A08/60R08 1.2 V, 1.05-1.4 V ...S1C60L08 External interrupt ............................ Input interrupt: 3 systems Internal interrupt .............................. Time base counter interrupt: Serial interface interrupt: 2 systems 1 system Supply voltage ................................ 3.0 V (1.8-3.5 V) 1.5 V (0.9-1.7 V) ...S1C60N08/60A08/60R08 ...S1C60L08 Current consumption ...................... S1C60N08 Halt state: 1.0 A when CLK = 32.768 kHz (Typ.) Run state: 2.2 A when CLK = 32.768 kHz (Typ.) S1C60L08 Halt state: 1.0 A when CLK = 32.768 kHz (Typ.) Run state: 2.2 A when CLK = 32.768 kHz (Typ.) S1C60A08 Halt state: 1.1 A when CLK = 32.768 kHz (Typ.) Run state: 3.0 A when CLK = 32.768 kHz (Typ.) Run state: 50 A when CLK = 500 kHz (Typ.) S1C60R08 Halt state: 1.0 A when CLK = 32.768 kHz (Typ.)...Target for S1C60N08 1.1 A when CLK = 32.768 kHz (Typ.)...Target for S1C60A08 Run state: 6.5 A when CLK = 32.768 kHz (Typ.)...Target for S1C60N08 7.5 A when CLK = 32.768 kHz (Typ.)...Target for S1C60A08 Run state: 115 A when CLK = 500 kHz (Typ.)...Target for S1C60A08 only Package .......................................... QFP5-100pin, QFP15-100pin (plastic) or chip 1: Can be selected with mask option 2 S1C60N08/60R08 BLOCK DIAGRAM S1C60N08/60L08/60A08 ROM 4,096 words x 12 bits : S1C60A08 only System Reset Control RESET Core CPU S1C6200C OSC1 OSC2 OSC3 OSC4 OSC Interrupt Generator RAM Input Port 832 words x 4 bits COM0-3 SEG0-47 VDD VL1 VL2 VL3 CA CB VS1 VSS AMPP AMPM S1C60R08 SDA SCL LCD Driver 48 SEG x 4 COM K00-K03, K10 K20-K23 TEST I/O Port P00-P03 P10-P13 Output Port R00-R03 R10-R13 Power Controller Sound Generator SVD Serial I/F Event Counter Timer Comparator Stopwatch Serial EEPROM Interface ROM Emulator 4,096 words x 12 bits Error Detecting Circuit System Reset Control SIN SOUT SCLK ERROUT OTPRST RESET Core CPU S1C6200C OSC1 OSC2 OSC3 OSC4 OSC Interrupt Generator RAM Input Port 832 words x 4 bits COM0-3 SEG0-47 VDD VL1 VL2 VL3 CA CB VS1 VSS AMPP AMPM LCD Driver 48 SEG x 4 COM K00-K03, K10 K20-K23 TEST I/O Port P00-P03 P10-P13 Output Port R00-R03 R10-R13 Power Controller Sound Generator SVD Serial I/F Event Counter Timer Comparator Stopwatch SIN SOUT SCLK 3 S1C60N08/60R08 PIN CONFIGURATION S1C60N08/60L08/60A08 Pin Configuration QFP5-100pin 80 51 81 50 S1C60N08/60L08/60A08 INDEX 31 100 1 30 QFP15-100pin 75 51 50 76 S1C60N08/60L08/60A08 INDEX 26 100 1 4 25 No. Pin name 1 COM1 2 COM0 3 SEG47 4 SEG46 5 SEG45 6 SEG44 7 SEG43 8 SEG42 9 SEG41 10 SEG40 11 SEG39 12 SEG38 13 SEG37 14 SEG36 15 SEG35 16 SEG34 17 SEG33 18 SEG32 19 SEG31 20 SEG30 No. Pin name 21 SEG29 22 SEG28 23 SEG27 24 SEG26 25 SEG25 26 SEG24 27 TEST 28 SEG23 29 SEG22 30 SEG21 31 SEG20 32 SEG19 33 SEG18 34 SEG17 35 SEG16 36 SEG15 37 SEG14 38 SEG13 39 SEG12 40 SEG11 No. Pin name 41 SEG10 42 SEG9 43 SEG8 44 SEG7 45 SEG6 46 SEG5 47 SEG4 48 SEG3 49 SEG2 50 SEG1 51 SEG0 52 AMPP 53 AMPM 54 K23 55 K22 56 K21 57 K20 58 K10 59 K03 60 K02 No. Pin name No. Pin name 61 K01 81 R12 62 K00 82 R11 63 SIN 83 R10 64 SOUT 84 R13 65 N.C. 85 VSS 66 SCLK 86 RESET 67 P03 87 OSC4 68 P02 88 OSC3 69 P01 89 VS1 70 P00 90 OSC2 71 N.C. 91 OSC1 72 N.C. 92 VDD 73 P13 93 VL3 74 P12 94 VL2 75 P11 95 VL1 76 P10 96 CA 77 R03 97 CB 78 R02 98 N.C. 79 R01 99 COM3 80 R00 100 COM2 N.C. = No Connection No. Pin name 1 SEG47 2 SEG46 3 SEG45 4 SEG44 5 SEG43 6 SEG42 7 SEG41 8 SEG40 9 SEG39 10 SEG38 11 SEG37 12 SEG36 13 SEG35 14 SEG34 15 SEG33 16 SEG32 17 SEG31 18 SEG30 19 SEG29 20 SEG28 No. Pin name 21 SEG27 22 SEG26 23 SEG25 24 SEG24 25 TEST 26 SEG23 27 SEG22 28 SEG21 29 SEG20 30 SEG19 31 SEG18 32 SEG17 33 SEG16 34 SEG15 35 SEG14 36 SEG13 37 SEG12 38 N.C. 39 SEG11 40 SEG10 No. Pin name 41 SEG9 42 SEG8 43 SEG7 44 SEG6 45 SEG5 46 SEG4 47 SEG3 48 SEG2 49 SEG1 50 SEG0 51 AMPP 52 AMPM 53 K23 54 K22 55 K21 56 K20 57 K10 58 K03 59 K02 60 K01 No. Pin name No. Pin name 61 K00 81 R10 62 SIN 82 R13 63 SOUT 83 VSS 64 N.C. 84 RESET 65 SCLK 85 OSC4 66 N.C. 86 OSC3 67 P03 87 VS1 68 P02 88 OSC2 69 P01 89 OSC1 70 P00 90 VDD 71 P13 91 VL3 72 P12 92 VL2 73 P11 93 VL1 74 P10 94 CA 75 R03 95 CB 76 R02 96 N.C. 77 R01 97 COM3 78 R00 98 COM2 79 R12 99 COM1 80 R11 100 COM0 N.C. = No Connection S1C60N08/60R08 S1C60N08/60L08/60A08 Pin Description Pin name VDD VSS VS1 VL1 VL2 VL3 CA, CB OSC1 OSC2 OSC3 OSC4 K00-K03 K10 K20-K23 P00-P03 P10-P13 R00-R03 R10 R13 R11 R12 SIN SOUT SCLK AMPP AMPM SEG0-47 COM0-3 RESET TEST Pin No. QFP5-100 QFP15-100 92 90 85 89 95 94 93 96, 97 91 90 88 87 62-59 58 Function 83 (I) (I) Power supply pin (+) Power supply pin (-) 87 93 92 - - - 91 94, 95 89 - - I Oscillation and internal logic system voltage output pin LCD drive voltage output pin (approx. -1.05 V or 1/2*VL2) LCD drive voltage output pin (2*VL1 or approx. -2.10 V) LCD drive voltage output pin (3*VL1 or 3/2*VL2) Boost capacitor connecting pin 88 86 85 O I O 61-58 57 56-53 I I I 57-54 70-67 70-67 76-73 74-71 80-77 78-75 83 81 84 82 82 80 81 79 63 62 64 63 66 65 52 51 53 52 51-28, 26-3 50-39, 37-26, 24-1 2, 1, 100, 99 100-97 86 84 27 I/O 25 I/O I/O O O O O O I O I/O I I O Cryctal oscillation input pin Crystal oscillation output pin CR or ceramic oscillation input pin (N.C. for S1C60N08 and S1C60L08) CR or ceramic oscillation output pin (N.C. for S1C60N08 and S1C60L08) Input port pin Input port pin Input port pin I/O port pin I/O port pin Output port pin Output port pin or BZ output pin Output port pin or BZ output pin Output port pin or SIOF output pin Output port pin or FOUT output pin Serial interface data input pin Serial interface data output pin Serial interface clock input/output pin Analog comparator non-inverted input pin Analog comparator inverted input pin LCD segment output pin or DC output pin O I LCD common output pin (1/2, 1/3 or 1/4 duty are selectable ) I Input pin for test Initial reset input pin Can be selected by mask option 5 S1C60N08/60R08 S1C60R08 Pin Configuration QFP5-100pin 80 51 50 81 S1C60R08 INDEX 31 100 1 30 QFP15-100pin 75 51 50 76 S1C60R08 INDEX 26 100 1 6 25 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin name COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin name SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 AMPP AMPM K23 K22 K21 K20 K10 K03 K02 No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin name K01 K00 SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 P10 R03 R02 R01 R00 No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin name R12 R11 R10 R13 VSS RESET OSC4 OSC3 VS1 OSC2 OSC1 VDD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin name SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin name SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin name SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin name R10 R13 VSS RESET OSC4 OSC3 VS1 OSC2 OSC1 VDD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 COM1 COM0 S1C60N08/60R08 S1C60R08 Pin Description Pin name Pin No. QFP5-100 QFP15-100 I/O Function 92 85 90 83 (I) Power supply pin (+) (I) Power supply pin (-) 89 87 95 94 93 92 - - 93 91 - Oscillation and internal logic system voltage output pin LCD drive voltage output pin (approx. -1.05 V or 1/2*VL2) LCD drive voltage output pin (2*VL1 or approx. -2.10 V) LCD drive voltage output pin (3*VL1 or 3/2*VL2) 96, 97 94, 95 OSC1 OSC2 91 90 89 88 - I Boost capacitor connecting pin Crystal oscillation input pin O Crystal oscillation output pin OSC3 88 86 I 87 62-59 85 60-57 O I CR or ceramic oscillation input pin * CR or ceramic oscillation output pin * 58 56 I K20-K23 P00-P03 57-54 70-67 55-52 68-65 I I/O P10-P13 76-73 74-71 R00-R03 R10 R11 80-77 83 82 78-75 81 80 I/O O O I/O port pin Output port pin Output port pin or BZ output pin * O Output port pin or SIOF output pin * 81 84 63 79 82 61 O O I Output port pin or FOUT output pin * Output port pin or BZ output pin * 64 66 62 64 O I/O I Serial interface data output pin Serial interface clock input/output pin Analog comparator non-inverted input pin I O O Analog comparator inverted input pin LCD segment output pin or DC output pin * LCD common output pin (1/2, 1/3 or 1/4 duty are selectable *) I I Initial reset input pin Input pin for test Serial EEPROM clock output pin Serial EEPROM data input/output pin Errout detecting singnal output for download program Cold reset pin for re-start download program from EEPROM VDD VSS VS1 VL1 VL2 VL3 CA, CB OSC4 K00-K03 K10 R12 R13 SIN SOUT SCLK AMPP AMPM SEG0-47 COM0-3 RESET TEST SCL SDA ERROUT OTPRST 52 50 53 51 51-28, 26-3 49-26, 24-1 2, 1, 100, 99 86 27 100-97 84 25 71 72 98 65 69 70 96 63 - O I/O O I Input port pin Input port pin Input port pin I/O port pin Serial interface data input pin Can be selected by mask option 7 S1C60N08/60R08 OPTION LIST 1. DEVICE TYPE * DEVICE TYPE ................................... * CLOCK TYPE (for Evaluation board) 1. S1C60N08 (Normal Type) 2. S1C60L08 (Low Power Type) (Note) 3. S1C60A08 (Twin Clock Type) 1. 32 kHz 2. 38 kHz 2. OSC3 SYSTEM CLOCK (only for S1C60A08) 1. CR 2. Ceramic 3. MULTIPLE KEY ENTRY RESET * COMBINATION .................................. * TIME AUTHORIZE ............................. 1. Not Use 2. Use K00, K01 3. Use K00, K01, K02 4. Use K00, K01, K02, K03 1. Use 2. Not Use 4. WATCHDOG TIMER 1. Use 2. Not Use 5. INPUT INTERRUPT NOISE REJECTOR * K00-K03 ............................................ 1. Use * K10 ..................................................... 1. Use * K20-K23 ............................................ 1. Use 2. Not Use 2. Not Use 2. Not Use 6. INPUT PORT PULL DOWN RESISTOR * K00 ..................................................... * K01 ..................................................... * K02 ..................................................... * K03 ..................................................... * K10 ..................................................... * K20 ..................................................... * K21 ..................................................... * K22 ..................................................... * K23 ..................................................... 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 7. OUTPUT PORT SPECIFICATION (R00-R03) * R00 ..................................................... * R01 ..................................................... * R02 ..................................................... * R03 ..................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 8. R10 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................. 1. DC Output 2. Pch-OpenDrain 2. Buzzer Output 9. R11 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................. 1. DC Output 2. Pch-OpenDrain 2. SIO Flag 10. R12 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary 2. Pch-OpenDrain * OUTPUT TYPE .................................. 1. DC Output 2. FOUT 32768 or 38400 [Hz] 3. FOUT 16384 or 19200 [Hz] 4. FOUT 8192 or 9600 [Hz] 5. FOUT 4096 or 4800 [Hz] 6. FOUT 2048 or 2400 [Hz] 7. FOUT 1024 or 1200 [Hz] 8. FOUT 512 or 600 [Hz] 9. FOUT 256 or 300 [Hz] 8 S1C60N08/60R08 11. R13 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary 2. Pch-OpenDrain * OUTPUT TYPE .................................. 1. DC Output 2. Buzzer Inverted Output (R13 Control) 3. Buzzer Inverted Output (R10 Control) 12. I/O PORT SPECIFICATION * P00 ..................................................... * P01 ..................................................... * P02 ..................................................... * P03 ..................................................... * P10 ..................................................... * P11 ..................................................... * P12 ..................................................... * P13 ..................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 13. SIN PULL DOWN RESISTOR 1. With Resistor 2. Gate Direct 1. Complementary 2. Pch-OpenDrain * PULL DOWN RESISTOR .................. 1. With Resistor * OUTPUT SPECIFICATION ............... 1. Complementary * LOGIC ................................................ 1. Positive 2. Gate Direct 2. Pch-OpenDrain 2. Negative 14. SOUT SPECIFICATION 15. SCLK SPECIFICATION 16. SIO DATA PERMUTATION 1. MSB First 2. LSB First 17. EVENT COUNTER NOISE REJECTOR 1. 2048 or 2400 [Hz] 2. 256 or 300 [Hz] 18. LCD SPECIFICATION * BIAS SELECTION S1C60N08 .......................................... S1C60L08 (Note) ............................... S1C60A08 .......................................... 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/2 Bias, Regulator Not Used, LCD 3 V 3. 1/3 Bias, Regulator Not Used, LCD 4.5 V 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V * DUTY SELECTION ............................ 1. 1/4 Duty 2. 1/3 Duty 3. 1/2 Duty 19. SEGMENT MEMORY ADDRESS 1. 0 Page (040-06F) 2. 2 Page (240-26F) Note: The S1C60R08 does not support the S1C60L08. 9 S1C60N08/60R08 S1C60R08 ROM EMULATOR/ROM EMULATOR PROGRAMMER The S1C60R08 has a built-in ROM emulator, which is constructed by RAM, to emulate mask ROM. The ROM emulator is programmed from outside through the serial interface (programmer) circuit and then its data is read by the CPU. This chapter explain the ROM emulator and the Programmer circuit. Configuration of ROM Emulator The built-in ROM emulator is the same structure with the mask ROM built-in S1C60N08. And used for loading the user-program. That has a capacity of 4,096 steps x 12 bits. The program area consists of 16 (0-15) pages x 256 (00H-FFH) steps. After initial reset, the program beginning address is set to bank 0, page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H-0FH. Bank 0 Step 00H Program start address Page 0 Page 1 Step 01H Page 2 Interrupt vector area Page 3 Step 0FH Step 10H Page 15 Step FFH 12 bits The ROM emulator data is downloaded from an external Serial EEPROM through the Programmer circuit. After power on or a HIGH pulse is input to the OTPRST pin, the ROM emulator data is initialized and downloading will be started. Configuration of ROM Emulator Programmer The ROM emulator data is written through the Programmer. The Programmer supports data transmit/receive communication with Serial EEPROM, interface data error check and system reset signal generation. S1C60R08 OSC1 RESET VDD System reset CPU and peripheral circuit A1 A0 SDA SCL ERROUT Error Detect Circuit VSS Terminals The Programmer uses the following input/output terminals. SCL: Serial EEPROM control clock output terminal SDA: Serial EEPROM data transmit/receive terminal ERROUT: Data check result output terminal OTPRST: Data re-loading start input terminal 10 ROM Emulator 4,096 x 12 bits A2 Serial EEPROM OTPRST EEPROM Interface Circuit Configuration flag CPU S1C60N08/60R08 Operation The S1C60R08 has two operation modes, * Programming mode: Load the data from the Serial EEPROM * Normal mode: Work as if the mask ROM type The following describes how to operate the S1C60R08. 1) Make an application software. 2) Convert the software to the Serial EEPROM format with winedg in the S1C60R08 package. 3) Write the program which is converted to the Serial EEPROM format to the Serial EEPROM. 4) Set up the S1C60R08, the Serial EEPROM and the other peripheral components on the user target application. (The example is described in "BASIC EXTERNAL CONNECTION DIAGRAM".) 5) The application power on. 6) The S1C60R08 enters to the Programming mode, and starts data loading from the Serial EEPROM to the built-in ROM emulator automatically. In the loading, internal circuit is kept as system reset condition except the Programmer. And data error checking is done at the same time. 7) If the data error happens, the ERROUT pin goes HIGH level and data loading is terminated. 8) If the data has loaded without any error, the S1C60R08 enters to the Normal mode automatically. Then the CPU read the ROM emulator data as the instruction and start to run as if the mask ROM type. 9) If you want to re-load the data, input a HIGH pulse to the OTPRST pin. Then the S1C60R08 enters to Programming mode and starts re-loading. SUMMARY OF NOTES Target Type for S1C60N08 Series The S1C60N08 has 3 types (S1C60N08, S1C60A08 and S1C60L08). In these models, the S1C60R08 supports the following 2 types as the ROM emulator model. S1C60N08 VDD = 3.0 V (Typ.), OSC1 S1C60A08 VDD = 3.0 V (Typ.), OSC1/OSC3 Refer the "S1C60N08/60R08 Technical Manual". Mask/Segment Option The S1C60R08 can load ROM emulator data. But cannot load the mask option and segment option. Therefore customer must make the function option data and segment option data by the S1C60R08 development tool at first. Then send the data to SEIKO EPSON and order the mask. SEIKO EPSON makes the S1C60R08 with a customized option according to this request. Serial EEPROM The external Serial EEPROM is necessary for programming the ROM emulator data, and this component is recommended. Recommended component: AK6010A/12A (AKM) M24C64/32 (SGS-THOMSON) BR24C64 (ROHM) 24AA64 (Microchip) Note: Use larger EEPROM than program memory size. 11 S1C60N08/60R08 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings S1C60N08/60A08/60R08 (VDD=0V) Rating Value Unit Symbol Supply voltage -5.0 to 0.5 V VSS Input voltage (1) VI VSS-0.3 to 0.5 V Input voltage (2) VIOSC VS1-0.3 to 0.5 V Permissible total output current 1 IVSS 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldering temperature / time Tsol 260C, 10sec (lead section) - Permissible dissipation 2 PD 250 mW 1: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in). 2: In case of plastic package. S1C60L08 (VDD=0V) Rating Value Unit Symbol Supply voltage -2.0 to 0.5 V VSS Input voltage (1) VI VSS-0.3 to 0.5 V Input voltage (2) VIOSC VS1-0.3 to 0.5 V Permissible total output current 1 IVSS 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldering temperature / time Tsol 260C, 10sec (lead section) - Permissible dissipation 2 PD 250 mW 1: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in). 2: In case of plastic package. Recommended Operating Conditions S1C60N08 Condition Supply voltage Oscillation frequency Symbol VSS fOSC1 Remark Min. -3.5 - - (Ta=-20 to 70C) Typ. Max. Unit -3.0 -1.8 V 32.768 - kHz 38.400 - kHz Remark Min. -1.7 -1.7 -1.7 - - (Ta=-20 to 70C) Typ. Max. Unit -1.5 -1.1 V -1.5 -0.9 2 V -1.5 -1.2 V 32.768 - kHz 38.400 - kHz Min. -3.5 - - 50 (Ta=-20 to 70C) Typ. Max. Unit -3.0 -2.2 1 V 32.768 - kHz 38.400 - kHz 500 600 kHz VDD=0V Either one is selected S1C60L08 Condition Supply voltage Symbol VSS Oscillation frequency fOSC1 VDD=0V VDD=0V, with software control 1 VDD=0V, when analog comparator is used Either one is selected 1: When switching to heavy load protection mode. 2: The possibility of LCD panel display differs depending on the characteristics of the LCD panel. S1C60A08/60R08 Condition Supply voltage Oscillation frequency (1) Symbol VSS fOSC1 Remark VDD=0V Either one is selected fOSC3 duty 505%, VSS=-2.2 to -3.5V Oscillation frequency (2) 1: -1.8V when the S1C60R08 is used as the S1C60N08. 12 S1C60N08/60R08 DC Characteristics S1C60N08/60A08/60R08 (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Characteristic Max. Unit Symbol Condition Min. Typ. High level input voltage (1) 0 V VIH1 K00-03, K10, K20-23, P00-03, P10-13 0.2*VSS SIN, (SDA) 1 High level input voltage (2) 0 V VIH2 SCLK, RESET, TEST, (OTPRST) 1 0.1*VSS Low level input voltage (1) 0.8*VSS V VIL1 K00-03, K10, K20-23, P00-03, P10-13 VSS SIN, (SDA) 1 Low level input voltage (2) VIL2 SCLK, RESET, TEST, (OTPRST) 1 VSS 0.9*VSS V High level input current (1) A IIH1 VIH1=0V K00-03, K10, K20-23, P00-03, P10-13 0 0.5 No pull-down SIN, SCLK, AMPP, AMPM (SDA) 1 High level input current (2) A 4 16 IIH2 VIH2=0V K00-03, K10, K20-23 With pull-down SIN, SCLK High level input current (3) A 25 100 VIH3=0V IIH3 P00-03, P10-13, RESET, TEST With pull-down (OTPRST) 1 Low level input current A -0.5 0 IIL VIL=VSS K00-03, K10, K20-23, P00-03, P10-13 SIN, SCLK, AMPP, AMPM, RESET, TEST (OTPRST), (SDA) 1 High level output current (1) mA -1.8 IOH1 VOH1=0.1*VSS R10, R11, R13 High level output current (2) mA -0.9 IOH2 VOH2=0.1*VSS R00-03, R12, P00-03, P10-13, SOUT SCLK, (SDA), (ERROUT), (SCL) 1 Low level output current (1) mA 6.0 IOL1 VOL1=0.9*VSS R10, R11, R13 Low level output current (2) mA 3.0 IOL2 VOL2=0.9*VSS R00-03, R12, P00-03, P10-13, SOUT SCLK, (SDA), (ERROUT), (SCL) 1 Common output current A -3 IOH3 VOH3=-0.05V COM0-3 A 3 IOL3 VOL3=VL3+0.05V Segment output current A -3 IOH4 VOH4=-0.05V SEG0-47 (during LCD output) A 3 IOL4 VOL4=VL3+0.05V Segment output current A -200 IOH5 VOH5=0.1*VSS SEG0-47 (during DC output) A 200 IOL5 VOL5=0.9*VSS 1: ( ) indicate the S1C60R08 pins. S1C60L08 (Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25C, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Characteristic Condition Min. Typ. Max. Unit Symbol High level input voltage (1) K00-03, K10, K20-23, P00-03, P10-13 0.2*VSS 0 V VIH1 SIN High level input voltage (2) VIH2 SCLK, RESET, TEST 0.1*VSS 0 V Low level input voltage (1) VIL1 K00-03, K10, K20-23, P00-03, P10-13 VSS 0.8*VSS V SIN Low level input voltage (2) VIL2 SCLK, RESET, TEST VSS 0.9*VSS V High level input current (1) IIH1 VIH1=0V K00-03, K10, K20-23, P00-03, P10-13 0 0.5 A No pull-down SIN, SCLK AMPP, AMPM High level input current (2) IIH2 VIH2=0V K00-03, K10, K20-23 2 10 A With pull-down SIN, SCLK High level input current (3) IIH3 VIH3=0V P00-03, P10-13 12 60 A With pull-down RESET, TEST Low level input current IIL VIL=VSS K00-03, K10, K20-23, P00-03, P10-13 -0.5 0 A SIN, SCLK, AMPP, AMPM RESET, TEST High level output current (1) IOH1 VOH1=0.1*VSS R10, R11, R13 -300 A High level output current (2) IOH2 VOH2=0.1*VSS R00-03, R12, P00-03, P10-13 -150 A SOUT, SCLK Low level output current (1) IOL1 VOL1=0.9*VSS R10, R11, R13 1400 A Low level output current (2) IOL2 VOL2=0.9*VSS R00-03, R12, P00-03, P10-13 700 A SOUT, SCLK IOH3 VOH3=-0.05V COM0-3 Common output current -3 A IOL3 VOL3=VL3+0.05V 3 A IOH4 VOH4=-0.05V SEG0-47 Segment output current -3 A IOL4 VOL4=VL3+0.05V (during LCD output) 3 A IOH5 VOH5=0.1*VSS SEG0-47 Segment output current -100 A IOL5 VOL5=0.9*VSS (during DC output) 100 A 13 S1C60N08/60R08 Analog Circuit Characteristics and Current Consumption S1C60N08 (Normal Operating Mode) (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Condition Min. Typ. Characteristic Max. Unit Symbol 1/2*VL2 LCD drive voltage 1/2*VL2 V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) - 0.1 x0.9 -2.30 -2.10 -1.90 VL2 Connect 1 M load resistor between VDD and VL2 V (without panel load) VL3 Connect 1 M load resistor between VDD and VL3 3/2*VL2 3/2*VL2 V (without panel load) - 0.1 x0.9 VB0 BLC="0" -2.35 -2.20 -2.05 BLD voltage 1 V VB1 BLC="1" -2.40 -2.25 -2.10 V VB2 BLC="2" -2.45 -2.30 -2.15 V VB3 BLC="3" -2.50 -2.35 -2.20 V VB4 BLC="4" -2.55 -2.40 -2.25 V VB5 BLC="5" -2.60 -2.45 -2.30 V VB6 BLC="6" -2.65 -2.50 -2.35 V VB7 BLC="7" -2.70 -2.55 -2.40 V BLD circuit response time tB 100 sec VBS Sub-BLD voltage -2.55 -2.40 -2.25 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V VIM Inverted input (AMPM) input voltage VOF Analog comparator 10 mV offset voltage tAMP VIP=-1.5V Analog comparator 3 msec VIM=VIP15mV response time During HALT Without IOP Current consumption 1.0 2.0 A panel load During operation 2 2.2 4.0 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. S1C60N08 (Heavy Load Protection Mode) (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Condition Min. Typ. Characteristic Max. Unit Symbol 1/2*VL2 LCD drive voltage 1/2*VL2 V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) - 0.1 x0.9 -2.30 -2.10 -1.90 VL2 Connect 1 M load resistor between VDD and VL2 V (without panel load) VL3 Connect 1 M load resistor between VDD and VL3 3/2*VL2 3/2*VL2 V (without panel load) - 0.1 x0.9 -2.35 -2.20 -2.05 VB0 BLC="0" BLD voltage 1 V VB1 BLC="1" -2.40 -2.25 -2.10 V VB2 BLC="2" -2.45 -2.30 -2.15 V VB3 BLC="3" -2.50 -2.35 -2.20 V VB4 BLC="4" -2.55 -2.40 -2.25 V VB5 BLC="5" -2.60 -2.45 -2.30 V VB6 BLC="6" -2.65 -2.50 -2.35 V VB7 BLC="7" -2.70 -2.55 -2.40 V BLD circuit response time tB 100 sec VBS Sub-BLD voltage -2.55 -2.40 -2.25 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V input voltage VIM Inverted input (AMPM) VOF Analog comparator 10 mV offset voltage tAMP VIP=-1.5V Analog comparator 3 msec VIM=VIP15mV response time IOP During HALT Without Current consumption 10 20 A panel load During operation 2 12 25 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. 14 S1C60N08/60R08 S1C60L08 (Normal Operating Mode) (Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Condition Min. Typ. Characteristic Max. Unit Symbol -1.15 -1.05 -0.95 LCD drive voltage V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) 2*VL1 VL2 Connect 1 M load resistor between VDD and VL2 2*VL1 V (without panel load) - 0.1 x0.9 VL3 Connect 1 M load resistor between VDD and VL3 3*VL1 3*VL1 V (without panel load) - 0.1 x0.9 VB0 BLC="0" -1.15 -1.05 -0.95 BLD voltage 1 V VB1 BLC="1" -1.20 -1.10 -1.00 V VB2 BLC="2" -1.25 -1.15 -1.05 V VB3 BLC="3" -1.30 -1.20 -1.10 V VB4 BLC="4" -1.35 -1.25 -1.15 V VB5 BLC="5" -1.40 -1.30 -1.20 V VB6 BLC="6" -1.45 -1.35 -1.25 V VB7 BLC="7" -1.50 -1.40 -1.30 V BLD circuit response time tB 100 sec Sub-BLD voltage VBS -1.30 -1.20 -1.10 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V VIM Inverted input (AMPM) input voltage VOF Analog comparator 20 mV offset voltage tAMP VIP=-1.1V Analog comparator 3 msec VIM=VIP30mV response time During HALT Without IOP Current consumption 1.0 2.0 A panel load During operation 2 2.2 4.0 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. S1C60L08 (Heavy Load Protection Mode) (Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Condition Characteristic Min. Typ. Max. Unit Symbol LCD drive voltage -1.15 -1.05 -0.95 V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) 2*VL1 VL2 Connect 1 M load resistor between VDD and VL2 2*VL1 V (without panel load) - 0.1 x0.85 VL3 Connect 1 M load resistor between VDD and VL3 3*VL1 3*VL1 V (without panel load) - 0.1 x0.85 BLD voltage 1 -1.15 -1.05 -0.95 VB0 BLC="0" V VB1 BLC="1" -1.20 -1.10 -1.00 V VB2 BLC="2" -1.25 -1.15 -1.05 V VB3 BLC="3" -1.30 -1.20 -1.10 V VB4 BLC="4" -1.35 -1.25 -1.15 V VB5 BLC="5" -1.40 -1.30 -1.20 V VB6 BLC="6" -1.45 -1.35 -1.25 V VB7 BLC="7" -1.50 -1.40 -1.30 V BLD circuit response time tB 100 sec VBS Sub-BLD voltage -1.30 -1.20 -1.10 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V VIM Inverted input (AMPM) input voltage VOF Analog comparator 20 mV offset voltage tAMP VIP=-1.1V Analog comparator 3 msec VIM=VIP30mV response time IOP During HALT Without Current consumption 6.5 10 A panel load During operation 2 8.5 15 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. 15 S1C60N08/60R08 S1C60A08 (Normal Operating Mode) (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Min. Typ. Characteristic Max. Unit Symbol Condition -1.15 -1.05 -0.95 LCD drive voltage V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) 2*VL1 VL2 Connect 1 M load resistor between VDD and VL2 2*VL1 V (without panel load) - 0.1 x0.9 VL3 Connect 1 M load resistor between VDD and VL3 3*VL1 3*VL1 V (without panel load) - 0.1 x0.9 VB0 BLC="0" BLD voltage 1 -2.35 -2.20 -2.05 V VB1 BLC="1" -2.40 -2.25 -2.10 V VB2 BLC="2" -2.45 -2.30 -2.15 V VB3 BLC="3" -2.50 -2.35 -2.20 V VB4 BLC="4" -2.55 -2.40 -2.25 V VB5 BLC="5" -2.60 -2.45 -2.30 V VB6 BLC="6" -2.65 -2.50 -2.35 V VB7 BLC="7" -2.70 -2.55 -2.40 V BLD circuit response time tB 100 sec Sub-BLD voltage VBS -2.55 -2.40 -2.25 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V input voltage VIM Inverted input (AMPM) Analog comparator 10 VOF mV offset voltage Analog comparator 3 tAMP VIP=-1.5V msec response time VIM=VIP15mV Current consumption 1.1 2.0 IOP During HALT Without A 3.0 5.0 During operation 2 panel load A 50 70 During operation at 500kHz 2 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. S1C60A08 (Heavy Load Protection Mode) (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Min. Typ. Characteristic Max. Unit Condition Symbol -1.15 -1.05 -0.95 LCD drive voltage V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) 2*VL1 VL2 Connect 1 M load resistor between VDD and VL2 2*VL1 V (without panel load) - 0.1 x0.9 VL3 Connect 1 M load resistor between VDD and VL3 3*VL1 3*VL1 V (without panel load) - 0.1 x0.9 VB0 BLC="0" BLD voltage 1 -2.35 -2.20 -2.05 V VB1 BLC="1" -2.40 -2.25 -2.10 V VB2 BLC="2" -2.45 -2.30 -2.15 V VB3 BLC="3" -2.50 -2.35 -2.20 V VB4 BLC="4" -2.55 -2.40 -2.25 V VB5 BLC="5" -2.60 -2.45 -2.30 V VB6 BLC="6" -2.65 -2.50 -2.35 V VB7 BLC="7" -2.70 -2.55 -2.40 V BLD circuit response time tB 100 sec Sub-BLD voltage VBS -2.55 -2.40 -2.25 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V input voltage VIM Inverted input (AMPM) Analog comparator VOF 10 mV offset voltage Analog comparator 3 tAMP VIP=-1.5V msec response time VIM=VIP15mV Current consumption IOP During HALT Without 6.5 10 A During operation 2 8.5 15 panel load A 55 75 During operation at 500kHz 2 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. 16 S1C60N08/60R08 S1C60R08 (Normal Operating Mode) Target: S1C60N08 (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Condition Min. Typ. Characteristic Max. Unit Symbol 1/2*VL2 LCD drive voltage 1/2*VL2 V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) - 0.1 x0.9 -2.30 -2.10 -1.90 VL2 Connect 1 M load resistor between VDD and VL2 V (without panel load) VL3 Connect 1 M load resistor between VDD and VL3 3/2*VL2 3/2*VL2 V (without panel load) - 0.1 x0.9 VB0 BLC="0" -2.35 -2.20 -2.05 BLD voltage 1 V VB1 BLC="1" -2.40 -2.25 -2.10 V VB2 BLC="2" -2.45 -2.30 -2.15 V VB3 BLC="3" -2.50 -2.35 -2.20 V VB4 BLC="4" -2.55 -2.40 -2.25 V VB5 BLC="5" -2.60 -2.45 -2.30 V VB6 BLC="6" -2.65 -2.50 -2.35 V VB7 BLC="7" -2.70 -2.55 -2.40 V BLD circuit response time tB 100 sec VBS Sub-BLD voltage -2.55 -2.40 -2.25 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V VIM Inverted input (AMPM) input voltage VOF Analog comparator 10 mV offset voltage tAMP VIP=-1.5V Analog comparator 3 msec VIM=VIP15mV response time During HALT Without IOP Current consumption 1.0 2.0 A panel load During operation 2 6.5 9.0 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. S1C60R08 (Heavy Load Protection Mode) Target: S1C60N08 (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Condition Min. Typ. Characteristic Max. Unit Symbol 1/2*VL2 LCD drive voltage 1/2*VL2 V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) - 0.1 x0.9 -2.30 -2.10 -1.90 VL2 Connect 1 M load resistor between VDD and VL2 V (without panel load) VL3 Connect 1 M load resistor between VDD and VL3 3/2*VL2 3/2*VL2 V (without panel load) - 0.1 x0.9 VB0 BLC="0" -2.35 -2.20 -2.05 BLD voltage 1 V VB1 BLC="1" -2.40 -2.25 -2.10 V VB2 BLC="2" -2.45 -2.30 -2.15 V VB3 BLC="3" -2.50 -2.35 -2.20 V VB4 BLC="4" -2.55 -2.40 -2.25 V VB5 BLC="5" -2.60 -2.45 -2.30 V VB6 BLC="6" -2.65 -2.50 -2.35 V VB7 BLC="7" -2.70 -2.55 -2.40 V BLD circuit response time tB 100 sec Sub-BLD voltage VBS -2.55 -2.40 -2.25 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V input voltage VIM Inverted input (AMPM) VOF Analog comparator 10 mV offset voltage tAMP VIP=-1.5V Analog comparator 3 msec VIM=VIP15mV response time During HALT Without IOP Current consumption 6.5 10 A panel load During operation 2 11.5 20 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. 17 S1C60N08/60R08 S1C60R08 (Normal Operating Mode) Target: S1C60A08 (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Min. Typ. Characteristic Max. Unit Symbol Condition -1.15 -1.05 -0.95 LCD drive voltage V VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) 2*VL1 VL2 Connect 1 M load resistor between VDD and VL2 2*VL1 V (without panel load) - 0.1 x0.9 VL3 Connect 1 M load resistor between VDD and VL3 3*VL1 3*VL1 V (without panel load) - 0.1 x0.9 VB0 BLC="0" BLD voltage 1 -2.35 -2.20 -2.05 V VB1 BLC="1" -2.40 -2.25 -2.10 V VB2 BLC="2" -2.45 -2.30 -2.15 V VB3 BLC="3" -2.50 -2.35 -2.20 V VB4 BLC="4" -2.55 -2.40 -2.25 V VB5 BLC="5" -2.60 -2.45 -2.30 V VB6 BLC="6" -2.65 -2.50 -2.35 V VB7 BLC="7" -2.70 -2.55 -2.40 V BLD circuit response time tB 100 sec Sub-BLD voltage VBS -2.55 -2.40 -2.25 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V input voltage VIM Inverted input (AMPM) Analog comparator 10 VOF mV offset voltage Analog comparator 3 tAMP VIP=-1.5V msec response time VIM=VIP15mV Current consumption 1.1 2.0 IOP During HALT Without A 7.5 10 During operation 2 panel load A 115 150 During operation at 500kHz 2 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. S1C60R08 (Heavy Load Protection Mode) Target: S1C60A08 (Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F) Characteristic Max. Unit Min. Typ. Condition Symbol LCD drive voltage V -1.15 -1.05 -0.95 VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) VL2 Connect 1 M load resistor between VDD and VL2 2*VL1 V 2*VL1 (without panel load) - 0.1 x0.9 VL3 Connect 1 M load resistor between VDD and VL3 3*VL1 3*VL1 V (without panel load) - 0.1 x0.9 BLD voltage 1 VB0 BLC="0" -2.35 -2.20 -2.05 V VB1 BLC="1" -2.40 -2.25 -2.10 V VB2 BLC="2" -2.45 -2.30 -2.15 V VB3 BLC="3" -2.50 -2.35 -2.20 V VB4 BLC="4" -2.55 -2.40 -2.25 V VB5 BLC="5" -2.60 -2.45 -2.30 V VB6 BLC="6" -2.65 -2.50 -2.35 V VB7 BLC="7" -2.70 -2.55 -2.40 V BLD circuit response time tB 100 sec Sub-BLD voltage VBS -2.55 -2.40 -2.25 V Sub-BLD circuit response time tBS 100 sec Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 VDD-0.9 V input voltage VIM Inverted input (AMPM) Analog comparator VOF 10 mV offset voltage Analog comparator tAMP VIP=-1.5V 3 msec response time VIM=VIP15mV Current consumption IOP During HALT Without 6.5 10 A During operation 2 panel load 12.5 20 A During operation at 500kHz 2 120 160 A 1: The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2: The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. 18 S1C60N08/60R08 Oscillation Characteristics Oscillation characteristics will vary according to different conditions (elements used, boad pattern). Use the following characteristics are as reference values. S1C60N08/60R08 (OSC1 Crystal Oscillation) (Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C) Characteristic Symbol Condition Min. Typ. Max. Unit Oscillation start voltage Vsta -1.8 V tsta5sec (VSS) tstp10sec (VSS) Oscillation stop voltage Vstp -1.8 V Including the parasitic capacitance inside the chip Built-in capacitance (drain) CD 20 pF f/V VSS=-1.8 to -3.5V Frequency/voltage deviation 5 ppm f/IC Frequency/IC deviation -10 10 ppm f/CG CG=5 to 25pF Frequency adjustment range 35 45 ppm (VSS) Harmonic oscillation start voltage Vhho -3.5 V Rleak Between OSC1 and VDD Permitted leak resistance 200 M S1C60L08 (OSC1 Crystal Oscillation) (Unless otherwise specified: VDD=0V, VSS=-1.5V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C) Condition Symbol Min. Typ. Max. Unit tsta5sec (VSS) Vsta -1.1 V tstp10sec (VSS) Vstp -1.1 V (-0.9)1 Including the parasitic capacitance inside the chip Built-in capacitance (drain) CD 20 pF f/V VSS=-1.1 (-0.9)1 to -1.7V Frequency/voltage deviation 5 ppm f/IC -10 Frequency/IC deviation 10 ppm f/CG CG=5 to 25pF 35 Frequency adjustment range 45 ppm (VSS) Harmonic oscillation start voltage Vhho -1.7 V Rleak Between OSC1 and VDD 200 Permitted leak resistance M 1: Parentheses indicate value for operation in heavy load protection mode. Characteristic Oscillation start voltage Oscillation stop voltage S1C60A08 (OSC1 Crystal Oscillation) (Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C) Characteristic Symbol Condition Min. Typ. Max. Unit Oscillation start voltage Vsta -2.2 V tsta5sec (VSS) tstp10sec (VSS) Oscillation stop voltage Vstp -2.2 V Including the parasitic capacitance inside the chip Built-in capacitance (drain) CD 20 pF f/V VSS=-2.2 to -3.5V Frequency/voltage deviation 5 ppm f/IC Frequency/IC deviation -10 10 ppm f/CG CG=5 to 25pF Frequency adjustment range 35 45 ppm (VSS) Harmonic oscillation start voltage Vhho -3.5 V Between OSC1 and VDD Rleak Permitted leak resistance 200 M S1C60A08/60R08 (OSC3 CR Oscillation) Characteristic Symbol Oscillation frequency dispersion fOSC3 Vsta (VSS) Oscillation start voltage tsta VSS=-2.2 to -3.5V Oscillation start time Vstp (VSS) Oscillation stop voltage (Unless otherwise specified: VDD=0V, VSS=-3.0V, RCR=82k, Ta=25C) Condition Min. Typ. Max. Unit -30 480kHz 30 % -2.2 V 3 msec -2.2 V S1C60A08/60R08 (OSC3 Ceramic Oscillation) Characteristic Oscillation start voltage Oscillation start time Oscillation stop voltage (Unless otherwise specified: VDD=0V, VSS=-3.0V, Ceramic oscillator: 500kHz, CGC=CDC=100pF, Ta=25C) Symbol Condition Min. Typ. Max. Unit Vsta (VSS) -2.2 V tsta VSS=-2.2 to -3.5V 5 msec Vstp (VSS) -2.2 V 19 S1C60N08/60R08 BASIC EXTERNAL CONNECTION DIAGRAM S1C60N08 and S1C60L08 SIO VL1 VL3 VDD X'tal S1C60N08 S1C60L08 OSC2 OSC3 N.C. OSC4 N.C. 3.0 V (S1C60N08) or 1.5 V (S1C60L08) X'tal Crystal oscillator Trimmer capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor R10 (BZ) R13 (BZ) R11 (LAMP) RESET Lamp CGX C1 C2 C3 C4 C5 CP RA1 RA2 C5 VS1 [The potential of the substrate (back of the chip) is VDD.] R12 (FOUT) O CGX OSC1 AMPM AMPP R00 : R03 Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. VL2 P00 : P03 P10 : P13 SIN SOUT SCLK CA + TEST CP VSS Piezo 32.768 kHz or 38.400 kHz, CI = 35 k 5-25 pF 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F 100 100 R10 (BZ) I/O C1 CB R13 (BZ) I COM3 K00 : K03 K10 K20 : K23 SEG47 COM0 SEG0 LCD panel RA1 RA2 Piezo When the piezoelectric buzzer is driven directly Note: The above tables are simply an example, and are not guaranteed to work. 20 S1C60N08/60R08 S1C60A08 I/O P00 : P03 P10 : P13 CB CA VL1 VL2 VL3 VDD OSC2 [The potential of the substrate (back of the chip) is VDD.] VS1 C5 CGC OSC3 OSC4 R10 (BZ) R13 (BZ) R11 (LAMP) Lamp 3.0 V CR CDC 1 2 + TEST CP VSS Piezo R13 (BZ) 32.768 kHz or 38.400 kHz, CI = 35 k 5-25 pF Trimmer capacitor 500 kHz Ceramic oscillator 100 pF Gate capacitor 100 pF Drain capacitor Resistor for CR oscillation 82 k 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 3.3 F Capacitor 100 Protection resistor 100 Protection resistor 1 Ceramic oscillation 2 CR oscillation X'tal Crystal oscillator CGX CR CGC CDC RCR C1 C2 C3 C4 C5 CP RA1 RA2 RCR RESET R12 (FOUT) O CGX X'tal S1C60A08 AMPM AMPP R00 : R03 Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. OSC1 SIN SOUT SCLK SIO C1 R10 (BZ) I COM3 K00 : K03 K10 K20 : K23 SEG47 COM0 SEG0 LCD panel RA2 RA1 Piezo When the piezoelectric buzzer is driven directly Note: The above tables are simply an example, and are not guaranteed to work. 21 S1C60N08/60R08 S1C60R08 (Target for S1C60N08) CA VL1 VL3 VDD P00 : P03 P10 : P13 X'tal S1C60R08 OSC2 [The potential of the substrate (back of the chip) is VDD.] R13 (BZ) R11 (LAMP) R12 (FOUT) ERROUT SDA SCL A1 NC X'tal CGX C1 C2 C3 C4 C5 CP RA1 RA2 IC1 OSC3 N.C. OSC4 N.C. 3.0 V + TEST CP VSS Piezo SCL SDA Crystal oscillator Trimmer capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor Serial EEPROM 32.768 kHz or 38.400 kHz 5-25 pF 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F 100 100 : See "Serial EEPROM" R10 (BZ) VSS IC1 VCC C5 VS1 RESET Lamp A0 A2 CGX OSC1 SIN SOUT SCLK OTPRST AMPM AMPP SIO Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. VL2 R13 (BZ) I/O C1 CB R10 (BZ) I COM3 K00 : K03 K10 K20 : K23 SEG47 COM0 SEG0 LCD panel RA1 RA2 Piezo When the piezoelectric buzzer is driven directly Note: The above tables are simply an example, and are not guaranteed to work. 22 S1C60N08/60R08 S1C60R08 (Target for S1C60A08) I VL2 VL3 VDD NC CGX X'tal S1C60R08 OSC2 [The potential of the substrate (back of the chip) is VDD.] VS1 C5 CGC OSC3 OSC4 RCR 3.0 V CR CDC 1 2 R10 (BZ) R13 (BZ) R11 (LAMP) R12 (FOUT) ERROUT RESET SDA SCL A1 IC1 VCC Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. OSC1 Lamp A0 C1 CA SIN SOUT SCLK OTPRST AMPM AMPP SIO + TEST CP VSS Piezo 1 Ceramic oscillation 2 CR oscillation SCL SDA X'tal CGX CR CGC CDC RCR C1 C2 C3 C4 C5 CP RA1 RA2 IC1 Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitor Drain capacitor Resistor for CR oscillation Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor Serial EEPROM 32.768 kHz or 38.400 kHz 5-25 pF 500 kHz 100 pF 100 pF 82 k 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F 100 100 : See "Serial EEPROM" R10 (BZ) VSS R13 (BZ) A2 CB VL1 P00 : P03 P10 : P13 I/O COM3 K00 : K03 K10 K20 : K23 SEG47 COM0 SEG0 LCD panel RA1 RA2 Piezo When the piezoelectric buzzer is driven directly Note: The above tables are simply an example, and are not guaranteed to work. 23 S1C60N08/60R08 PACKAGE Plastic QFP5-100pin 25.60.4 200.1 80 51 140.1 INDEX 31 100 1 30 0.30.1 0.26 2.70.1 0.65 3.4max 19.60.4 50 81 0.150.05 0 12 1.5 2.8 Plastic QFP15-100pin 160.4 140.1 75 51 160.4 50 140.1 76 INDEX 100 26 1.40.1 25 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.50.2 0.1 1.7max 1 1 Unit: mm 24 S1C60N08/60R08 PAD LAYOUT S1C60N08/60L08/60A08 Diagram of Pad Layout 20 15 10 5 1 95 25 90 30 Y (0, 0) 35 3.73 mm 85 X 80 40 Die No. 75 45 50 55 60 65 70 Chip thickness: 400 m Pad opening: 95 m 3.74 mm S1C60N08/60L08/60A08 Pad Coordinates No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pad name AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 SIN SOUT SCLK P03 P02 P01 P00 P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 R10 R13 VSS RESET X 1,294 1,164 1,034 904 774 644 514 384 254 124 -7 -137 -267 -397 -527 -657 -787 -917 -1,048 -1,178 -1,308 -1,438 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 Y 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,686 1,556 1,426 1,296 1,166 1,036 812 682 457 327 No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pad name OSC4 * OSC3 * VS1 OSC2 OSC1 VDD VL3 VL2 VL1 CA CB COM3 COM2 COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 X -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,415 -1,285 -1,155 -1,025 -895 -765 -635 -505 -375 -245 -115 15 145 275 405 535 665 Y 176 46 -84 -214 -344 -503 -633 -763 -893 -1,022 -1,153 -1,283 -1,413 -1,543 -1,673 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pad name SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 Unit: m X Y 795 -1,699 925 -1,699 1,055 -1,699 1,185 -1,699 1,315 -1,699 1,445 -1,699 1,704 -1,621 1,704 -1,465 1,704 -1,310 1,704 -1,180 1,704 -1,050 1,704 -920 1,704 -790 1,704 -660 1,704 -530 1,704 -400 1,704 -270 1,704 -140 1,704 -10 1,704 120 1,704 250 1,704 380 1,704 510 1,704 640 1,704 770 1,704 900 1,704 1,030 1,704 1,160 1,704 1,290 1,704 1,420 1,704 1,550 1,704 1,680 : S1C60A08 only 25 S1C60N08/60R08 S1C60R08 Diagram of Pad Layout Die No. 25 15 20 10 1 5 100 30 95 35 Y (0, 0) 7.00 mm 90 X 85 40 45 80 50 60 55 65 70 75 Chip thickness: 400 m Pad opening: 95 m 8.35 mm S1C60R08 Pad Coordinates No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 26 Pad name AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 R10 R13 VSS X 2,893 2,638 2,382 2,127 1,871 1,616 1,360 1,105 849 594 339 83 -85 -260 -438 -683 -863 -1,064 -1,275 -1,566 -1,821 -2,126 -2,405 -2,685 -2,978 -3,686 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 Y 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,090 2,787 2,657 2,527 2,288 2,064 1,599 1,470 No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pad name REST OSC4 OSC3 VS1 OSC2 OSC1 VDD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 X -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -3,420 -3,116 -2,811 -2,507 -2,203 -1,899 -1,595 -1,290 -986 -682 -378 -74 230 534 838 1,142 1,446 Y 1,340 733 517 300 -576 -793 -958 -1,174 -1,391 -1,607 -1,824 -2,040 -2,241 -2,429 -2,645 -2,862 -3,088 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad name SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 X 1,751 2,055 2,359 2,663 2,967 3,272 3,661 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 Unit: m Y -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,049 -2,590 -2,355 -2,119 -1,883 -1,647 -1,411 -1,175 -939 -703 -467 -231 4 240 476 712 948 1,184 1,420 1,656 1,892 2,128 2,364 2,600 2,836 S1C60N08/60R08 THIS PAGE IS BLANK. 27 S1C60N08/60R08 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) Seiko Epson Corporation 2001 All right reserved. SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ IC Marketing & Engineering Group ED International Marketing Department Europe & U.S.A. 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5812 FAX : 042-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5814 FAX : 042-587-5110 Issue August, 2001 Printed in Japan L