IDT74FCT3807DQI8 - Integrated Device Technology

IDT74FCT3807/A

3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

SEPTEMBER 2001

2001 Integrated Device Technology, Inc. DSC-4647/2c

IDT74FCT3807/A

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

3.3V CMOS

1-TO-10 CLOCK DRIVER

DESCRIPTION:

The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS

technology. This low skew clock driver offers 1:10 fanout. The large fanout from

a single input reduces loading on the preceding driver and provides an efficient

clock distribution network. The FCT3807/A offers low capacitance inputs with

hysteresis for improved noise margins. Multiple power and grounds reduce

noise. Typical applications are clock and signal distribution.

FUNCTIONAL BLOCK DIAGRAM

O10

PIN CONFIGURATION

GND

VCC

GND

VCC

GND

VCC

GND

VCCIN

O10

10 11

SOIC/ SSOP/ QSOP

TOP VIEW

FEATURES:

• 0.5 MICRON CMOS Technology

• Guaranteed low skew < 350ps (max.)

• Very low duty cycle distortion < 350ps (max.)

• High speed: propagation delay < 3ns (max.)

• Very low CMOS power levels

• TTL compatible inputs and outputs

• 1:10 fanout

• Maximum output rise and fall time < 1.5ns (max.)

• Low input capacitance: 4.5pF typical

•VCC = 3.3V ± 0.3V

• Inputs can be driven from 3.3V or 5V components

• Available in SSOP, SOIC, and QSOP packages

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

IDT74FCT3807/A

3.3V CMOS 1-TO-10 CLOCK DRIVER

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 3.3V, +25°C ambient.

3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fi)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V)

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

fi = Input Frequency

All currents are in milliamps and all frequencies are in megahertz.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Description Max Unit

VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V

VTERM(3) Terminal Voltage with Respect to GND –0.5 to +7 V

VTERM(4) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V

TSTG Storage Temperature –65 to +150 °C

IOUT DC Output Current –60 to +60 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. VCC terminals.

3. Input terminals.

4. Outputs and I/O terminals.

CAPACITANCE (TA = +25OC, f = 1.0MHz)

Symbol Parameter(1) Conditions Typ. Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6 pF

COUT Output Capacitance VOUT = 0V 5.5 8 pF

NOTE:

1. This parameter is measured at characterization but not tested.

PIN DESCRIPTION

Pin Names Description

IN Clock Inputs

Ox Clock Outputs

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

∆ICC Quiescent Power Supply Current VCC = Max. — 10 30 µA

TTL Inputs HIGH VIN = VCC –0.6V(3)

ICCD Dynamic Power Supply Current(4) VCC = Max. VIN = VCC — 0.31 0.45 mA/

Input toggling VIN = GND M H z

50% Duty Cycle

Outputs Open

ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 15.5 22.8 mA

Input toggling VIN = GND

50% Duty Cycle

Outputs Open VIN = VCC –0.6V — 15.5 22.8

fi = 50MHz VIN = GND

IDT74FCT3807/A

3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified

Commercial: TA = 0°C to +75°C, Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V

Symbol Parameter Test Conditions(1) Min. Typ. Max. Unit

VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2 — 5 .5 V

Input HIGH Level (I/O pins) 2 — VCC + 0.5

VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level –0.5 — 0.8 V

IIH Input HIGH Current (Input pins) VCC = Max. VI = 5.5V — — ±1

Input HIGH Current (I/O pins) VI = VCC ——±1µA

IIL Input LOW Current (Input pins) VCC = Max. VI = GND — — ±1

Input LOW Current (I/O pins) VI = GND — — ±1

IOZH High Impedence Output Current VCC = Max. VO = VCC ——±1µA

IOZL (3-State Output Pins) VO = GND — — ±1

VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V

IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 –60 –110 mA

IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) 50 90 200 mA

VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VCC–0.2 — — V

VIN = VIH or VIL IOH = –8mA 2.4 (5) 3—

VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2

VIN = VIH or VIL IOL = 16mA — 0.2 0.4 V

IOL = 24mA — 0.3 0.5

IOFF Input Power Off Leakage VCC = 0V, V IN = 4.5V — — ±1µA

IOS Short Circuit Current(4) VCC = Max., VO = GND(3) –60 –135 –240 mA

VHInput Hysteresis — — 150 — mV

ICCL Quiescent Power Supply Current VCC = Max. — 0.1 10 µA

ICCH VIN = GND or VCC

ICCZ

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 3.3V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

4. This parameter is guaranteed but not tested.

5. VOH = Vcc - 0.6V at rated current.

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

IDT74FCT3807/A

3.3V CMOS 1-TO-10 CLOCK DRIVER

NOTES:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.

4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.

FCT3807 FCT3807A

Symbol Parameter Conditions(1) Min.(2) Max.Min.(2) Max.Unit

tPLH Propagation Delay CL = 30pF 1.5 4.5 1.5 4 ns

tPHL f ≤ 67MHz

tROutput Rise Time (See figure 3) — 1.5 — 1.5 ns

tFOutput Fall Time — 1.5 — 1.5 ns

tSK(O) Output skew: skew between outputs of — 0.5 — 0.35 ns

same package (same transition)

tSK(P) Pulse skew: skew between opposite transitions — 0.5 — 0.35 ns

of same output (|tPHL -– tPLH|)

tSK(T) Package skew: skew between outputs of different — 1 — 0.75 ns

packages at same power supply voltage,

temperature, package type and speed grade

FCT3807 FCT3807A

Symbol Parameter Conditions(1) Min.(2) Max.Min.(2) Max.Unit

tPLH Propagation Delay CL = 50pF 1.5 4.8 1.5 4.3 ns

tPHL f ≤ 40MHz

tROutput Rise Time (See figure 4) — 1.5 — 1.5 ns

tFOutput Fall Time — 1.5 — 1.5 ns

tSK(O) Output skew: skew between outputs of — 0.5 — 0.35 ns

same package (same transition)

tSK(P) Pulse skew: skew between opposite transitions — 0.5 — 0.35 ns

of same output (|tPHL -– tPLH|)

tSK(T) Package skew: skew between outputs of different — 1 — 0.75 ns

packages at same power supply voltage,

temperature, package type and speed grade

SWITCHING CHARACTERISTICS OVER OPERATING RANGE - COMMERCIAL(3,4)

FCT3807 FCT3807A

Symbol Parameter Conditions(1) Min.(2) Max.Min.(2) Max.Unit

tPLH Propagation Delay 50Ω to VCC/2 1.5 3.5 1.5 3 ns

tPHL CL = 10pF

tROutput Rise Time (See figure 1) — 1.5 — 1.5 ns

tFOutput Fall Time or 10Ω AC — 1.5 — 1.5 ns

tSK(O) Output skew: skew between outputs of termination, — 0.5 — 0.35 ns

same package (same transition) CL = 50pF

tSK(P) Pulse skew: skew between opposite transitions (See figure 2) — 0.5 — 0.35 ns

of same output (|tPHL -– tPLH|) f ≤ 100MHz

tSK(T) Package skew: skew between outputs of different Outputs — 0.9 — 0.65 ns

packages at same power supply voltage, connected in

temperature, package type and speed grade groups of two

IDT74FCT3807/A

3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

NOTES:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.

4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.

FCT3807 FCT3807A

Symbol Parameter Conditions(1) Min.(2) Max.Min.(2) Max.Unit

tPLH Propagation Delay CL = 30pF 1.5 4.5 1.5 4 ns

tPHL f ≤ 67MHz

tROutput Rise Time (See figure 3) — 1.5 — 1.5 ns

tFOutput Fall Time — 1.5 — 1.5 ns

tSK(O) Output skew: skew between outputs of — 0.6 — 0.45 ns

same package (same transition)

tSK(P) Pulse skew: skew between opposite transitions — 0.6 — 0.45 ns

of same output (|tPHL -– tPLH|)

tSK(T) Package skew: skew between outputs of different — 1 — 0.75 ns

packages at same power supply voltage,

temperature, package type and speed grade

FCT3807 FCT3807A

Symbol Parameter Conditions(1) Min.(2) Max.Min.(2) Max.Unit

tPLH Propagation Delay CL = 50pF 1.5 4.8 1.5 4.3 ns

tPHL f ≤ 40MHz

tROutput Rise Time (See figure 4) — 1.5 — 1.5 ns

tFOutput Fall Time — 1.5 — 1.5 ns

tSK(O) Output skew: skew between outputs of — 0.6 — 0.45 ns

same package (same transition)

tSK(P) Pulse skew: skew between opposite transitions — 0.6 — 0.45 ns

of same output (|tPHL -– tPLH|)

tSK(T) Package skew: skew between outputs of different — 1 — 0.75 ns

packages at same power supply voltage,

temperature, package type and speed grade

SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL(3,4)

FCT3807 FCT3807A

Symbol Parameter Conditions(1) Min.(2) Max.Min.(2) Max.Unit

tPLH Propagation Delay 50Ω to VCC/2 1.5 3.5 1.5 3 ns

tPHL CL = 10pF

tROutput Rise Time (See figure 1) — 1.5 — 1.5 ns

tFOutput Fall Time or 50Ω AC — 1.5 — 1.5 ns

tSK(O) Output skew: skew between outputs of termination, — 0.6 — 0.45 ns

same package (same transition) CL = 10pF

tSK(P) Pulse skew: skew between opposite transitions (See figure 2) — 0.6 — 0.45 ns

of same output (|tPHL -– tPLH|) f ≤ 100MHz

tSK(T) Package skew: skew between outputs of different Outputs — 0.9 — 0.65 ns

packages at same power supply voltage, connected in

temperature, package type and speed grade groups of two

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

IDT74FCT3807/A

3.3V CMOS 1-TO-10 CLOCK DRIVER

D.U.T.

Pulse

Generator

VIN VOUT

VCC

100Ω

10pF

D.U.T.

Pulse

Generator

VIN VOUT

VCC

50Ω10pF

220pF

30pF

D.U.T.

Pulse

Generator

VIN VOUT

VCC

RTCL

50pF

D.U.T.

Pulse

Generator

VIN VOUT

VCC

RTCL

50pF

D.U.T.

Pulse

Generator

VIN VOUT

VCC

RT500Ω

500Ω

GND

Figure 1. ZO = 50

ΩΩ

Ω

to VCC/2, CL = 10pF The capacitor value for ac termination is determined by the operating frequency. For very

low frequencies a higher capacitor value should be selected.

Figure 3. CL = 30pF Circuit

ENABLE AND DISABLE TIME

SWITCH POSITION

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Figure 3. CL = 50pF Circuit

Figure 2. ZO = 50

ΩΩ

Ω

AC Termination, CL = 10pF

Test Switch

Disable LOW 6V

Enable LOW

Disable HIGH G ND

Enable HIGH

TEST CIRCUITS

Figure 5. Enable and Disable Time Circuit

IDT74FCT3807/A

3.3V CMOS 1-TO-10 CLOCK DRIVER COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

tPLH1

OUTPUT 1

OUTPUT 2

tSK(o)

tPLH2

VOH

1.5V

VOL

VOH

1.5V

VOL

INPUT tPHL1

tPHL2

tSK(o)

tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

1.5V

3.5V

SWITCH

CLOSED

SWITCH

OPEN

VOL

VOH

0.3V

tPLZ

tPZL

tPZH tPHZ

3.5V

1.5V

ENABLE DISABLE

VOH

tPLH tPHL

VOL

1.5V

tRtF

2.0V

0.8V

INPUT

OUTPUT

IN P UT tPLH1

PACKAGE 1 OUTPUT

PACKAGE 2 OUTPUT

tSK(t)

tPLH2

VOH

1.5V

VOL

VOH

1.5V

VOL

tPHL1

tPHL2

tSK(t)

tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

tPLH tPHL

VOH

1.5V

VOL

tSK(p) = |tPHL - tPLH|

INPUT

OUTPUT

TEST WAVEFORMS

Enable and Disable Times

Package 1 and Package 2 are same device type and speed grade

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

Pulse Skew - tSK(P) Package Skew - tSK(T)

Package Delay Output Skew - tSK(O)

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

IDT74FCT3807/A

3.3V CMOS 1-TO-10 CLOCK DRIVER

ORDERING INFORMATION

IDT74FCT Temp. Range

XXXX

Device Type X

Package

1-to-10 3.3V Clock Driver

3807

3807A

Small Outline IC

Shrink Small Outlin e IC

Quarter-size Small Outline IC

Blank

ICommer c ial (0°C to +70°C)

Industr ial ( -40°C to +85°C)

CORPORATE HEADQUARTERS for SALES: for Tech Support:

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