April 1998
Application Note 42037
ML4423 Application Guidelines
INTRODUCTION
Depending on the application, the focus of a given motor
control design can fall on one of many specific
parameters. Different applications may require that
special attention be given to a specific control method to
guarantee the desired performance. This Application Note
defines and clarifies industry terminology for these control
parameters, and will assist in utilizing the ML4423 for
many different AC motor control applications.
3rd HARMONIC INJECTION
A review of basic inverter output waveforms will help
introduce the concept of the 3rd harmonic injection.
When 3-phase, 120 degree sinusoidal voltage PWM
waveforms are supplied to the power inverter H and L
inputs (Figure 1), the integrated PWM phase output
waveforms will look like Figure 2 (phase C has been
omitted for clarity).
For this discussion, VBUS is equal to the relative amplitude
of 1.0. The VBUS ground (GND) will be referenced to the
relative amplitude of -1.0. This constrains the peak value
of the phase waveforms (Figure 2) to the maximum value
of ±1.0 (for unclipped sinusoidal waveforms). So, when
the differential waveform is at its positive peak, (Figure 2,
point B) the Q1 switch is modulating near VBUS and the
Q4 switch is modulating near GND (Figure 1). When the
differential waveform is at its negative peak, the Q3
switch is modulating near VBUS and the Q2 switch is
modulating near GND. In this instance, neither phase
amplitude (Figure 2, point A) is at its peak value when
the differential amplitude is at its peak value (Figure 2,
point B). For this condition, VBUS is not being fully
utilized. The differential amplitude is √3 x VPHASE. The
differential amplitude peaks when the phase amplitude is
at 0.865 of its maximum. For a sinusoidal waveform, the
bus voltage required is expressed in this formula:
VV
BUS DIFFRMS
=×
2
0 865. (1)
Reordering to solve for VDIFFRMS:
VV
DIFFRMS BUS
=×0 612.
Figure 3 shows a phase voltage waveform and its 3rd
harmonic. When the 3rd harmonic is summed with the
phase waveform, a new 3rd harmonic+phase waveform is
created. The amplitude of the 3rd harmonic signal has
been equalized slightly to maintain a peak value of 1.0 in
the resulting 3rd harmonic+phase waveform. Figure 3. Creating 3rd Harmonic Waveform
Figure 2. Sinusoidal Waveforms
Figure 1. Power Inverter
H
L
PHASE A PHASE B PHASE C
VBUS
GND
Q1 Q3
Q2 Q4
H
L
H
L
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
RELA TIVE AMPLITUDE
DEGREES
0 90 180 360270
V
DIFF
PHASE A
PHASE B
A
B
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
RELA TIVE AMPLITUDE
DEGREES
0 90 180 360270
3rd-HARMONIC
PHASE A
PHASE A + 3rd
REV. 1.0 10/25/2000
Application Note 67
2REV. 1.0 10/25/2000
Figure 4 shows two output phase waveforms with their 3rd
harmonics added, and the resulting differential waveform.
When the differential waveform is at its positive peak,
the Q1 switch is at VBUS and the Q4 switch is at GND
(Figure 1). When the differential waveform is at its
negative peak the Q3 switch is at VBUS and the Q2 switch
is at GND. The peak differential amplitude is ± VBUS.
Since the differential waveform is higher in amplitude
than in Figure 2, a new equation is used to derive VBUS.
The equation is:
VV
BUS DIFFRMS
=×2(2)
VV
BUS =×=220 2 311
It should also be noted that:
VV
DIFF PEAK DIFFRMS()
=×
2
VV
DIFF PEAK()
=×=220 2 311
The ML4423 can be configured to provide similar results.
Slight clipping will occur with the ML4423, because the
phase voltages are trapezoidal in nature (when VSPEED is
at 4.4V). Note that the 3rd harmonic phase waveforms
have dips in the center (Figure 3). This slight dip keeps
the differential waveform from saturating near its peak
amplitude. For this case VBUS is fully utilized. Using the
ML4423 in this way allows:
VV
DIFFRMS BUS
=2(3)
CONFIGURING THE ML4423
To configure the ML4423 for pseudo-3rd harmonic
injection, determine the value of VBUS to satisfy the
following parameters:
•V
SPEED = 4.4V
•V
SINEREF @ 1VRMS × √ 2, =1.5V peak
•V
MOTOR = 220VRMS
To find SENSEA, SENSEB, SENSEC feedback divider ratio,
the desired output voltage is configured as indicated (see
Figure 5):
VRR2
R2 V
MOTOR PEAK SINE PEAK() ()
=
+
F
H
G
I
K
J
×
1(4)
Solving for R1:
RVR2
VR2
MOTOR PEAK
SINE PEAK
1=×
F
H
GI
K
J−
()
()
RV
Vk1
311 1000
15 1000 206 3=×
F
H
GI
K
J−=
ΩΩΩ
..
Total harmonic distortion of 6% is shown in Figure 6.
Figure 6. Fast Forier Transform of Sense A-B Waveforms
Figure 4. 3rd Harmonic Waveforms
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
RELA TIVE AMPLITUDE
DEGREES
0 90 180 360270
VDIFF
PHASE A + 3rd
PHASE B + 3rd
SENSEA–B
SENSEB–C
SENSEC–A
FFT SENSEA–B
3rd HARMONIC INJECTION (Continued)
Figure 5. R1/R2 Divider
VMOTOR A, B, C
SENSEA, B, C
R1
R2
1kΩ
Application Note 67
REV. 1.0 10/25/2000 3
Figure 7. DC Braking Circuit
DC INJECTION BRAKING
DC injection braking works on the principle that if a DC
current is imposed on the motor windings, the resulting
stationary flux will cause the rotor to slow.
To utilize DC injection braking (Figure 7), provide a high
signal on the DC brake, which will cause Q3 to pull the
COAST signal low, and will briefly disable the output
PWM. The COAST signal low state will remain for the
time period set by the RC network of a 1µF capacitor and
a 100kΩ resistor. At the same time Q2 will pull the
VSPEED signal to 0V. Next, Q1 raises the voltage on the
VMIN signal. Then Q3 releases the COAST signal after
the RC network discharges and the PWM comes back on.
At that time the motor will receive a near DC current to
each winding for the time period set by the RC network of
a 5µF capacitor and a 1MΩ resistor. When the RC time
expires the VMIN signal will return to its original setting
and the PWM will remain on. The values given should be
adequate for a preliminary design.
This technique forces the motor to slow down much faster
than coasting. With regenerative schemes, a load
dissipater, an added switch, and some support circuitry
would be required. No overvoltage will develop at the
inverter since the slip on the motor will be large during
braking.
SOFT START
Increasing the capacitance on the VSPEED signal would
allow a soft start to occur when the DC brake signal is
pulled low.
4
5
6
7
12
13
14
25
24
23
22
17
16
15
VMIN
VSPEED
RSPEED
VREF
C0
CPWM
COAST
5V/12V SEL
H A
H C
H B
GND
ISENSE
F/R
ML4423
RMIN
100kΩ
RBRAKE
RSPEED
100kΩ
15kΩ
1MΩ
100kΩ100kΩ
5µF
1µF
CSOFTSTART
Q1 Q2 Q3
2N70002N70002N7000
1N5818
DC BRAKE
Application Note 67
4REV. 1.0 10/25/2000
LOOP CHARACTERISTICS
OPEN LOOP CONTROL
The ML4423 can be forced to operate in an open loop
configuration. In order to do this, the PWM outputs must
be fed back to the SENSEA, SENSEB, and SENSEC inputs.
Open loop control offers a softer response to load
variations. The ML4423 will not respond to a higher
motor current demand (by adjusting the PWM duty cycle),
limiting the available power to the motor.
This may be a preferred manner of control since the
resistors to select the proper motor voltage are now fixed
and the available bus voltage will determine the
available motor voltage. These characteristics are
beneficial for low cost, offline applications dealing with a
wide variety of motors and bus voltage variations.
Note that the VMIN potentiometer may need to be
adjusted to provide a voltage boost to the motor since the
PWM signal is not modified based on motor loading.
Differential Observer Circuit
The circuit in Figure 9 will allow observation of the
differential motor voltages without tying up scope
channels. The circuit provides the voltage waveforms at
the SENSEA, SENSEB, and SENSEC inputs of the ML4423.
Changing to Exponential V/F Control
Using the current sink circuit shown in Figure 11 with a
range of zero to 100µA in the place of resistor RSPEED will
allow the output frequency to be varied over the range
allowed by the CO capacitor (Figure 10). Blower and fan
applications in this configuration can run quietly at low
speed with no motor growling, unlike the closed loop
linear V/F scheme. The V/F function can be further
separated by connecting the Q1 base input to a voltage
source other than the VSPEED potentiometer wiper. This
controls the output frequency independently, while the
output amplitude is controlled by the VSPEED
potentiometer. R1 is selected to give the desired
maximum operating frequency when VSPEED = 4.4V.
Temperature coefficients require the transistors to be
closely mounted to minimize drift over temperature.
Figure 8. Open Loop Control Circuit
1
2
3
28
27
26
25
24
23
22
21
20
19
17
+
–
+
–
10kΩ
1kΩ
1kΩ
1kΩ
0.15µF0.15µF 0.15µF +
–
10kΩ
+
–
10kΩ
1
3
2
4
11
9
10
12
57
6
8
13 14
TL074
TL074
TL074
TL074
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
5kΩ
5kΩ
5kΩ
10kΩ
10kΩ
0.1µF
TO
OUTPUT
STAGE
12V
12V
½VCC
1nF 1nF
SENSEA
SENSEC
SENSEB
ML4423
CGM2
CGM1
VCC
5V/12V SEL
H A
H C
H B
L A
L C
L B
GND
Application Note 67
REV. 1.0 10/25/2000 5
Figure 9. Differential Observer Circuit
Figure 11. Current Sink CircuitFigure 10. Linear and Exponential V/F
LOOP CHARACTERISTICS (Continued)
5
6
7
12 17
VSPEED
RSPEED
VREF
COGND
10kΩ
10kΩ
Q1
2N3906
2N3904
2N3904
R1
2.7kΩ
V
SPEED
C
O
ML4423
1.2
1.0
0.8
0.6
0.4
0.2
0
SINE REFERENCE
FREQUENCY (Hz)
020 60
40
FEEDBACK GAIN VS. FREQUENCY
The internal GM amplifiers can operate with no bypass
capacitors. In some cases it may be necessary to lower
the loop gain to reduce the feedback bandwidth and
eliminate subharmonic oscillations. The GM amplifiers
have a high open loop gain, and with capacitance on the
GM1 and GM2 outputs, the gain can be tailored to rolloff
at predicted frequencies. Figures 12 through 17 are
examples of gain vs. frequency for the given capacitance.
SPEED LOOP
Closing a speed loop using the ML4423 can be done by
using a shaft speed sensor. The sensor generates an error
signal, which is used to close a loop around a reference
speed signal, and is then fed into the ML4423 speed input
pin (Figure 18).
There are additional benefits when using the slip control
loop, which enables the motor slip to be set to a valve.
When the motor accelerates, the motor current is limited
to the value set by the slip control circuit. This ensures
that the motor will accelerate at a predetermined rate,
and will operate within the current limit of the ML4423.
1
2
326
17
100kΩ
+
–
14 13
12
4
11
+
–
76
5
100kΩ
100kΩ
100kΩ
10kΩ
10kΩ
100kΩ
+
–
89
10
100kΩ
100kΩ
100kΩ
100kΩ
+
–
12
3
100kΩ
100kΩ
100kΩ
A – C/C – A
A – B
B – C
TO
OUTPUT VOL T AGE
DIVIDER NETWORK
FOR OSCILLOSCOPE VIEWING
SIGNAL
INVERT
SENSEA
SENSEC
SENSEB
ML4423
VCC
GND
Application Note 67
6REV. 1.0 10/25/2000
Figure 14. Bode Plot with a 1nF Capacitor
Figure 16. Bode Plot with a 10nF Capacitor
Figure 12. Bode Plot with no Capacitor
60
50
40
30
20
10
0
AMPLITUDE (dB)
FREQUENCY (kHz)
.001 .01 0.1 1 10 100
60
50
40
30
20
10
0
AMPLITUDE (dB)
FREQUENCY (kHz)
.001 .01 0.1 1 10 100
60
50
40
30
20
10
0
AMPLITUDE (dB)
FREQUENCY (MHz)
.001 .01 0.1 1 10 100
Figure 15. Phase Response with a 1nF Capacitor
Figure 17. Phase Response with a 10nF Capacitor
Figure 13. Phase Response with no Capacitor
0
–20
–40
–60
–80
–100
PHASE (DEGREES)
FREQUENCY (kHz)
.001 .01 0.1 1 10 100
0
–20
–40
–60
–80
–100
PHASE (DEGREES)
FREQUENCY (kHz)
.001 .01 0.1 1 10 100
0
–20
–40
–60
–80
–100
PHASE (DEGREES)
FREQUENCY (MHz)
.0001 .001 0.01 0.1 1 10
Application Note 67
REV. 1.0 10/25/2000 7
Figure 18. Closing the Speed Loop
+
–
VSPEED
(ML4423)
10kΩ10kΩ
10kΩ
100kΩ
100kΩ10kΩ
20kΩ
ADJ
10kΩ
3kΩ
10kΩ
500kΩ
10kΩ
10kΩ
100kΩ
3.9nF
1µF
100kΩ
100kΩ
12V
SPEED IN
60PPR SPEED
LM2907J
LM6134 LM6134
LM6134
LM6134
LM6134 LM6134
LM6134
7
6
5
7
8
10
9
1
211
3
4
1
6
5
211
4
3
8
9
10
13 14
12
1
2
3
4
512
11
10
9
SLIP
10kΩ
–
+
5kΩ
–
+
–
+
–
+
–
+
–
+
Application Note 67
8REV. 1.0 10/25/2000
OFFLINE OPERATION
Offline bias circuits can range from the leaky cap style to
low cost 120V to 12V AC transformers (Figure 19). The
transformer does offer isolation, but the power stage
coupled to the line defeats it, since RSENSE provides a
connection to the AC return. Fast rising and falling noise
spikes coupled on the 12V supply will ruin a good PCB
layout. The ML4423 and inverter bootstrap circuitry
typically consume 50mA at 12V DC.
OFF-LINE APPLICATIONS
A simple voltage doubler circuit will raise the 110V line
to about 325VDC. This allows operation with 115V
motors with sufficient headroom in the closed loop mode.
In open loop mode the bus voltage determines the motor
voltage. The capacitor RMS ripple current is equal to
ISENSE / √2 / √3.
SINGLE & TWO-PHASE OPERATION
The ML4423 can be used to operate single-phase motors.
The IC would drive the appropriate gate buffers and H
bridge transistors. The ML4423 HA, LA, HC, LC, SENSEA,
and SENSEC pins would provide the necessary I/O
functions. SENSEB input would be grounded, and the
motor voltage would be fed back from phase A to SENSEA
and phase C to SENSEC with a resistive divider network.
The two phase mode is selected.
For the two-phase mode, the component count required is
the same as for the three phase mode inverter
configuration. The main motor winding is connected to A
and C inverter outputs and the secondary motor winding is
connected to B inverter output. The two phase mode is
selected. The ML4423 contains no boost feature on the
secondary winding, which is required for some two phase
motors to produce adequate starting torque.
Figure 19. Low Cost 12V AC Transformer/120V Boost
+BUS
–BUS
OUT
IN
GND
7812
AC
HOT
AC
NEUTRAL
GND
12V
CLOSE SWITCH
FOR 120VAC
Application Note 67
REV. 1.0 10/25/2000 9
LAYOUT CONSTRAINTS
Figure 20 shows the current loop areas relating to circuit
layout and function. Critical loop areas are:
• Diode recovery
• Gate drives
• Bootstrap charging
• Motor di/dt
Since the current sense resistor is utilized by three of the
four loops, it needs to be a low inductance type. Diode
recovery currents are diverted from the current sense
resistor by the film capacitor, since the peak recovery
currents can be higher than the actual motor current. This
would prematurely trip the current limit.
Figure 20. Current Loops
The film capacitor should have sufficient energy storage
to handle the diode recovery time. An R/C filter on the
ISENSE pin is needed to filter any spikes. Typical values
range from 330pF to 1nF (R = 1kΩ). Minor loops not
highlighted include the voltage and current feedback
paths to the ML4423.
The PCB layout itself can make or break a successful
design. Circuit layouts without these considerations will
operate erratically under load, and may cause the output
power stage, gate drivers, and/or ML4423 to fail. The PCB
design examples on the following pages reflect loop area
control.
BOOTSTRAP
CHARGING
LOOP
AREA
VCC
H A
L A
GND
ISENSE
ML4423
26
24
21
17
16
LOOP AREA FILM
CAP
ELECTROLYTIC
CAP
DIODE
RECOVERY
LOOP
AREA
MOTOR
DI/DT
LOOP
AREA
GATE
DRIVE
LOOP
AREA
HIGH
DI/DT
ISENSE
+VBUS
GND
12V
Application Note 67
10 REV. 1.0 10/25/2000
THROUGH-HOLE PCB EXAMPLE
The ML4423 through-hole PCB in Figures 21a through 21f
illustrates the use of a ground plane. A single sided
layout should never be attempted. This is because of the
possibility of ground bounce. Whenever ground
referenced sensing is used the ground itself must be stable
and low in noise. Single layer boards can’t satisfy this
requirement since the gradients, or differences, in
voltages occur at different points on the board due to stray
inductance. The voltage differences in ground traces
creates voltage differences at the control IC. The CO pin
on the ML4423 is susceptible to any form of noise
because of its low amplitude of 300mVP-P. Therefore,
proper layout is essential for reliable circuit operation.
The most straightforward solution is a separate ground
plane. This layer, either as the top or bottom layer of the
PCB, reduces the gradient voltage effect across the PCB.
The stray inductance is also reduced since the trace
currents are mirrored on the ground plane. A possible
difficulty occurs when a power inverter has to occupy the
same PCB as the control IC. In this case, the phase
output tabs, upper gate drivers, and output voltage
feedback resistors should have clearance away from the
ground plane to reduce the opportunity of high frequency
combined with high voltage switching transients being
coupled by capacitance into the ground plane (see the
ML44xx PCB layout).
SURFACE MOUNT PCB EXAMPLE
The surface mount PCB in Figures 22a through 22i follows
the listed guidelines. The control IC has a ground plane
and is a combination surface mount and through-hole.
The power inverter does not have an active ground plane,
but uses parallel traces to reduce loop area, uses surface
mount devices, and uses the isolation of the FR-4 material
for its dielectric withstand capability. The bus power PCB
has the plus and minus bus on opposite sides, near critical
power transistor collector/emitter connections, reducing
the stray inductance loop area. The ground loops are
managed locally, then connected together by traces. This
assembly controls motors to 1/2HP with a suitable
heatsink.
Figure 21a. ML4423 Silkscreen Figure 21b. ML4423 Top Layer
LAYOUT CONSTRAINTS (Continued)
Application Note 67
REV. 1.0 10/25/2000 11
Figure 21c. ML4423 Bottom Layer Figure 21d. ML44xx Silkscreen
Application Note 67
12 REV. 1.0 10/25/2000
Figure 21e. ML44xx Top Layer Figure 21f. ML44xx Bottom Layer
Application Note 67
REV. 1.0 10/25/2000 13
Figure 22a. Control PCB Silkscreen
Figure 22b. Control PCB Top Layer
Figure 22c. Control PCB Bottom Layer
Figure 22d. Power PCB Silkscreen
Figure 22e. Power PCB Top Layer
10ΩΩ
ΩΩ
Ω
2512 X 8
JUMPERS
Application Note 67
14 REV. 1.0 10/25/2000
COMPONENT SELECTION
CAPACITORS
Since the ML4423 uses an external R/C to set up the low
frequency oscillator, drift over temperature is directly
related to the component tolerances at this node. If tight
frequency tolerance is necessary this should be reflected
in the component tolerances for the anticipated operating
temperature range.
RESISTORS & CURRENT SENSE RESISTORS
For best results, use 1% resistors in the voltage feedback
path. Wirewound resistors must not be used in the current
feedback path. A wirewound resistor can add 200nH of
circuit loop inductance, or the equivalent of a 20” long
trace. With a 200ns fall time, 5A of current translates
into a 5V spike across the current sense resistor for that
period of time. This will trip the current limit on the
ML4423 and cause problems with the bootstrap circuit
and the associated level shifter.
LEVEL SHIFTERS
The ML4423 and the level shifter used to drive the upper
IGBTs must provide the correct polarity signal to the IGBT
or a shootthrough short circuit will occur. Some level
shifters do not incorporate a pulse filter which rejects
small pulse widths. This may cause the level shifter to
latch in one mode and not reset. This typically occurs
near the crest of the output phase waveform, so when the
latch is not reset the ML4423 feedback error increases
and you lose part of the output cycle. If the bootstrap cap
discharges to the undervoltage lockout of the level shifter
the output cycle may also drop out.
BOOTSTRAP DIODES
The diodes used for generating the bootstrap voltage must
be ultra-fast (< 75ns). Slow devices will have a long
recovery time and can cause dV/dt induced noise
coupling problems. The diode should have at least 100V
of margin over the maximum bus voltage.
POWER DEVICES
IGBTs are suited to compete with MOSFETs to 20kHz.
The co-pack IGBT’s have softer and faster internal diodes
than MOSFETs. The relatively slow and snappy
characteristics of MOSFET diodes (in freewheel mode,
common for motor control) may cause chaos on ground
referenced current limit schemes, and will require larger
R/C filtering on the ISENSE pin. EMI considerations will
also play a role in device selection.
POTENTIAL DESIGN ISSUES
Other design issues to consider include: power switch
size, power dissipation and heatsinking, gate drive power,
gate charge, cost and reliability, and PCB layout.
Figure 22f. Bus Power PCB Top Silkscreen
Figure 22g. Bus Power PCB Top Layer
Figure 22h. Bus Pow er PCB Bottom Layer
Figure 22i. Bus Power PCB Bottom Silkscreen
Application Note 67
REV. 1.0 10/25/2000 15
COMPONENT SELECTION (Continued)
EXAMPLE: SELECTING IGBT AND HEATSINK
The following exercise selects a suitable power device
and heatsink for a 1/2 HP inverter. The selected IGBT is an
IRGBC20UD2. The requirements are:
• 1/2 HP 220VAC three phase induction motor
• DC input (VBUS) ≅ 360V DC
• motor power factor (PF) ≅ 0.7
• motor efficiency (ME) ≅ 0.7
• inverter modulation index (D) = 0.612 (Eq.1, p.1)
•f
PWM = 20kHz
• Ambient Temperature TA = 40°C
IGBT datasheet characteristics of interest are:
•V
CEON @ IC
•V
DIODE @ IC
•E
ON @ IC
•E
OFF @ IC
• Gate charge
•θJC
•θCS
1. Calculate motor phase current required:
IP
VPfDM
PHASE MOTOR
BUS E
=××××3(5)
I
W
HP HP
VA
PHASE RMS
=×
F
H
GI
K
J
××××
=
746 05
3 360 0 7 0 612 0 7 2
.
.. .
Then peak device collector current is:
II A
CPK PHASE
=×=2283.
2. Calculate IGBT conduction losses:
VCEON for peak operating current ≅ 2V
PI V D
PF
ON CPK CEON
=× × +
F
H
GI
K
J
×0125 3
.π(6)
PV W
ON =×× +
F
H
GI
K
J
×=283 2 0125 0 612
307 075..
.
..
π
3. Calculate IGBT switching losses:
ETOT switching losses = 0.71mJ
PE F
SW TOT mJ PWM kHz
=× ×
() ()
1
π(7)
PW
SW =××=071 20 1452..
π
4. Calculate diode conduction loss:
Diode voltage drop = 1.6V @ 2.83A
DIV D
PF
COND CPK DIODE
=× × +
F
H
GI
K
J
×0125 3
.π(8)
DV W
COND =×× +
F
H
GI
K
J
×=283 16 0125 0 612
307 060.. . ...
π
5. Calculate total losses:
TP P D
PD ON SW COND
=++ (9)
TWWWW
PD =++=075 452 06 587....
6. Calculate total power dissipation to select heatsink
size. Total inverter losses:
PT
INV PD
=×6(10)
PW W
INV =×=
587 6 3522..
7. Calculate heatsink size with TSINK selected at 125ºC.
Thermal impedance is:
θSA SINK A
INV
TT
P
=–(11)
θSA CC
WCW
=°− °=°
125 40
3522 24
../
8. Calculate IGBT and diode junction temperature for the
selected TSINK:
IGBT junction temperature is:
TT PP
JIGBT SINK ON SW JC CS
=++×+
bg
di
θθ (12)
TC
JIGBT =+ + ×+ = °125 075 452 21 0 5 1387.. .. .
afaf
Diode junction temperature is:
TTD
JDIODE SINK COND JC CS
=+ ×+θθ
di (13)
TC
JDIODE =+ ×+ = °125 0 60 21 0 5 126 6... .
af
Note: For reliable operation, TJIGBT and TJDIODE should be
lower than 125°C., forcing a reduction in the RQSA
requirement.
9. Calculate the RSENSE resistor value:
II
SENSE PEAK PHASE()
=×
2(14)
IA A
SENSE PEAK() ..=× =2 1414 283
RV
I
SENSE SENSE
=05. (15)
Application Note 67
16 REV. 1.0 10/25/2000
Figure 23. Clipped Phase C
COMPONENT SELECTION (Continued)
RV
A
SENSE ==
05
283 0176
.
..Ω
10. Finally, calculate resistor power dissapation:
PIR
DISS SENSE PEAK SENSE
=F
H
GI
K
J×
()
2
2
(16)
PAW
DISS =F
H
GI
K
J×=
283
20176 07
2
...Ω
Adjustment factors have not been included for lower bus
voltages.
GATE DRIVE CONSIDERATIONS
Choosing the bootstrap capacitor: The phase output
referenced inverter waveforms pertain to the basic
inverter design and operation. The formulas provided by
IR for selecting the Bootstrap capacitor value address non-
saturating PWM designs. Since the phase waveforms clip
even when the differential waveforms are sinusoidal,
(Figure 22) the upper switch has to stay on for the duration
without being refreshed. This requires the bootstrap
capacitor to be larger than the value initially calculated.
As a quick approximation, 2µF/HP works with the IR2118.
For the following conditions:
• IR2118 high side gate driver
•I
QBS = 50uA, typical
•V
CC = 12V
•T
ON = 5ms
• IGBT gate charge = 22nC (for the IRGBC20UD2)
CQ
IT
V
BOOT G QBS ON
CC
>× +××
−−
22
15 10. (17)
CnC
Ams F
BOOT >× +××
>222 250 5
05 0 544
µµ
..
In this case use a 1µF capacitor.
Note: If IQBS increases to 240µA, CBOOT = 4.88uF
Selecting the value for the series gate resistor should be
based on the available peak driver current of the driver IC
used. Typically, datasheet RG values will work for most
applications.
A – B
B – C
C – A
PHASE C
Application Note 67
REV. 1.0 10/25/2000 17
Figure 24. Inverter Schematic
C10
470µF
400V
1
2
3
4
8
7
6
5
IR2118
C2
1µF
C1
1µF
R30
10Ω
R31
1.0Ω
R35
10Ω
R32
1
2
3
4
8
7
6
5
IR2118
C4
1µF
C3
1µF
R36
10Ω
R37
1.0Ω
R35
10Ω
R38
1
2
3
4
8
7
6
5
IR2118
C6
1µF
C5
1µF
R42
10Ω
R43
1.0Ω
R35
10Ω
R44
Q1 Q3
Q4
Q2
Q5
Q6
D3
D2
D1
C7
1µF C8
1µF
C9
1µF
C13
0.1µF
400V
C14
0.1µF
400V
F1
5A
R49
0.1Ω
U1 U2 U3
PHASE A
SENSE A
PHASE B
SENSE B
PHASE C
SENSE C
Q7
Q8
Q11
Q12
Q9
Q10
+HV IN
I
SENSE
+12V
HA
HB
HC
LC
LB
LA
GND
HV GND
Application Note 67
18 REV. 1.0 10/25/2000
Figure 25. Controller Schematic
ML4423
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C3
0.15µF
C14
220pF SW1
COAST SW3
FWD/REV
C21
1nF C9
0.1µF
C22
1nF
C15
1nF
C15
0.1µF
C15
1µF
C5
1nF
C4
1nF
ISENSE
SENSEASENSEB12V
SENSEC
H A
H C
H B
L A
L C
L B
C8
0.1µF
C13
0.56µF
C11
0.1µF
C2
0.15µF C1
0.15µF
R15
1kΩ
R13
1kΩR27
100kΩ
VMIN
R16
160kΩ
R17
200kΩ
R18
200kΩ
R19
1kΩ
R26
100kΩ
VSPEED
R14
1kΩ
TP1
TP2
Application Note 67
REV. 1.0 10/25/2000 19
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injur y of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably e xpected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com © 2000 Fairchild Semiconductor Corporation
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
