FPD750SOT343
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 04/28/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• PERFORMANCE (1850 MHz)
♦ 0.3 dB Noise Figure at 25% Bias
♦ 20 dBm Output Power (P1dB)
♦ 18 dB Small-Signal Gain (SSG)
♦ 38 dBm Output IP3 at 50% Bias
♦ Evaluation Boards Available
♦ Available in Lead Free Finish: FPD750SOT343E
• DESCRIPTION AND APPLICATIONS
The FPD750SOT343 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron
Mobility Transistor (pHEMT). It utilizes a 0.25 μm x 750 μm Schottky barrier Gate, defined by
high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes
parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a
range of bias conditions and input power levels. The FPD750 is available in die form and in other
packages.
Typical applications include drivers or output stages in PCS/Cellular base station high-intercept-
point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
• ELECTRICAL SPECIFICATIONS AT 22°C
Parameter Symbol Test Conditions Min Typ Max Units
RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL
Minimum Noise Figure NF VDS = 3.3 V; IDS = 50% IDSS
VDS = 3.3 V; IDS = 25% IDSS
0.6
0.3
0.9 dB
Output Third-Order Intercept Point
(from 15 to 5 dB bel o w P1dB)
IP3 VDS = 3.3 V; IDS = 50% IDSS
VDS = 3.3 V; IDS = 25% IDSS
Tuned for Optimum IP3
35.5 38
34
dBm
Small-Signal Gain SSG VDS = 3.3 V; IDS = 50% IDSS
VDS = 3.3 V; IDS = 25% IDSS
16.5 18
17
dB
Power at 1dB Gain Compression P1dB VDS = 3.3 V; IDS = 50% IDSS
VDS = 3.3 V; IDS = 25% IDSS
19 20
18
dBm
Saturated Drain-S o urce Current IDSS VDS = 1.3 V; VGS = 0 V 185 230 280 mA
Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 375 mA
Transconductance GMVDS = 1.3 V; VGS = 0 V 200 mS
Gate-Source Leakage Current IGSO VGS = -5 V 5 μA
Pinch-Off Voltage |VP|V
DS = 1.3 V; IDS = 0.75 mA 0.7 1.0 1.3 V
Gate-Source Breakdown Voltage |VBDGS|I
GS = 0.75 mA 12 16 V
Gate-Drain Breakdown Voltage |VBDGD|I
GD = 0.75 mA 12 18 V
FPD750SOT343
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 04/28/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• ABSOLUTE MAXIMUM RATINGS1
Parameter Symbol Test Conditions Min Max Units
Drain-Source Voltage VDS -3V < VGS < +0V 6 V
Gate-Source Voltage VGS 0V < VDS < +8V -3 V
Drain-Source Current I DS For VDS > 2V IDSS mA
Gate Current IGForward or reverse current 7.5 mA
RF Input Power2PIN Under any acceptable bias state 175 mW
Channel Operating Temperature TCH Under any acceptable bias state 175 ºC
Storage Temperature TSTG Non-Operatin g St o rage -40 150 ºC
Total Power Dissipation PTOT See De-Rating Note below 1.1 W
Gain Compression Comp. Under any bias conditions 5 dB
Simultaneous Combination of Limits32 or more Max. Limits 80 %
1TAmbient = 22°C unless otherwise noted 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Users should avo id exceeding 80% of 2 or more Limits simultaneously
Notes:
• Operating conditio ns that exceed the Abso lute Maximum Ratings will result in permanent damage to the device.
• Total Power Dissi pat i o n defined as: PTOT ≡ (PDC + PIN) – POUT, where:
PDC: DC Bias Power
PIN: RF Input Power
POUT: RF Output Power
• Total Power Dissipation to be de-rated as follows above 22°C:
PTOT= 1.1W – (0.007W /°C) x TPACK
where TPACK = source tab lead temperature above 22
°
C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C source lead temperature: PTOT = 1.1W – (0.007 x (65 – 22)) = 0.8W
• HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
• APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site. Evaluation Boards available upon request.
FPD750SOT343
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 04/28/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• BIASING GUIDELINES
¾ Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD750SOT343.
¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source
bias voltage, and such circuits provide some temperature stabilization for the device. A nominal
value for circuit development is 5.45 Ω for a 50% of IDSS operating point.
¾ For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at
50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25%
to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3
performance.
• PACKAGE OUTLINE
(dimensions in mm)
All information and specifications subject to change without notice.
SOURCE GATE
DRAIN SOURCE
FPD750SOT343
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 04/28/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
Minimum Noise Figure
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (GHz)
FMIN
Output Power (dBm) and
3rd-Order Intermodulation Products (dBc)
vs. Input Power
2
3
4
5
6
7
8
9
10
-14.5 -13.4 -12.3 -11.3 -10.3 -9.3 -8.2
Pin, (d Bm)
Pout, (dBm)
-63.00
-61.00
-59.00
-57.00
-55.00
-53.00
-51.00
3rd-Order IM Products, (dBc)
Pout (dBm) 3rds (dBc)
