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FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
1.0 Features
• Complete programmable control via I2Cä-bus
• Selectable CMOS or PECL compatible outputs
• External feedback loop capability allows genlocking
• Tunable VCXO loop for jitter attenuation
• Commercial (FS6131-01) and industrial (FS6131-01i)
temperature versions available
2.0 Description
The FS6131-01 is a monolithic CMOS clock genera-
tor/rege nerator IC designed to minim ize cost and com po-
nent count in a variet y of electronic system s. Via the I2C-
bus interface, the FS6131-01 can be adapted to many
clock generation requirements.
The abilit y to tune the on-bo ard voltage-controlled crystal
oscillator (VCXO), the length of the Ref erence an d Feed-
back Dividers, their granularity, and the flexibility of the
Post Divider make the FS6131-01 the most flexible
stand-alone phase-locked loop (PLL) clock generator
available.
3.0 Applications
• Frequency Synthesis
• Line-Locked and Genlock Applications
• Clock Multiplication
• Telecom Jitter Attenuation
Figure 1: Pin Configuration
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
SCL
SDA
ADDR
VSS
XIN
XOUT
XTUNE
VDD LOCK/IPRG
EXTLF
VSS
REF
FBK
VDD
CLKP
CLKN
16-pin 0.150" SOIC
FS6131
Figure 2: Block Diagram
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN L O O P
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0]
POST2[1:0]
POST1[1:0]
REFDIV[11:0]
FBKDIV[13:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OUTMUX[1:0]
Clock
Gobbler
GBL
(optional)
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
R
LF
C
LF
C
LP
11
00
10
01
01
00
10
11
1
0
1
0
0
1
10
1
0
2
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN TYPE NAME DESCRIPTION
1 DI SCL Serial I nterf ace Cl ock (requires an external pull-up)
2 DIO SDA Serial I nterf ace Dat a Input/Output (requires an external pull-up)
3 DI ADDR Address S elect Bi t (s ee Sect i on 5.2. 1)
4 P VSS Ground
5 AI XIN VCXO Feedback
6 AO XOUT VCXO Drive
7 AI XTUNE VCXO Tune
8 P VDD Power Supply (+5V)
9 DIO LOCK/IPRG Lock Indicator / PECL Current Drive Programming
10 AI EXTLF External Loop Filter
11 P VSS Ground
12 DI REF Reference Frequenc y Input
13 DI FBK Feedback Input
14 P VDD Power Supply (+5V)
15 DO CLKP Differential Clock Output (+)
16 DO CLK N Differential Clock Output (-)
4.0 Functional Bl ock Descripti on
4.1 Main Loop PLL
The Main Loop Phase Locked Loop (ML-PLL) is a stan-
dard phase- and frequency- locked loop architecture. As
shown in Figure 2, the ML-PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscil-
lator (VCO), a Feedback Divider, and a Post Divider.
During operation, the reference frequency (fREF), gener-
ated by either the on-board crystal oscillator or an exter-
nal frequency source, is first reduced by the Reference
Divider . T he integer va lu e th at th e f r eque ncy is divi de d by
is called the modulus, and is denoted as NR for the Ref-
erence D ivider. T he divided ref erence is then fed into t he
PFD.
The PFD controls the frequency of the VCO (fVCO)
through the charge pump and loop filter. The VCO pro-
vides a high-speed, low noise, continuously variable fre-
quency clock source for the ML-PLL. The output of the
VCO is fed back to the PFD through the Feedback Di-
vider (the modulus is denoted by NF) to close the loop.
The PFD will dr ive t he VCO u p or d own in f requenc y unt il
the divided reference frequency and the divided VCO
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
R
REF
F
VCO N
f
N
f=.
If the VCO frequency is used as the PLL output fre-
quency (fCLK) then the basic PLL equation can be rewrit-
ten as
÷
÷
ø
ö
ç
ç
è
æ
=R
F
REFCLK N
N
ff .
4.1.1 Reference Divider
The Reference Divider is designed for low phase jitter.
The divid er accepts e ither the output of eith er the Cr ystal
Loop (the VCXO output) or an external reference fre-
quency, and provides a divided-down frequency to the
PFD. The Reference Divider is a 12-bit divider, and can
be programmed for any modulus from 1 to 4095. See
both Table 3 and Table 8 for additional programming in-
formation.
3
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
g
rammable Line Lock Clock Generator I C
Pro
g
rammable Line Lock Clock Generator I CPro
g
rammable Line Lock Clock Generator I C
Pro
g
rammable Line Lock Clock Generator I C
4.1.2 Feedback Divider
The Feedback Divider is based on a dual-modulus
prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allo win g the pro gr am mable porti on t o o per at e at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the program-
mable Feedback Divider because of the high speeds at
which the VCO c an op erate. T he dua l-m odulus tec hniqu e
insures r eliable operati on at any spee d that the VCO can
achieve and reduces the overall power consumption of
the divider.
For exam ple, a fixed divide-b y-eight could be used in the
Feedback Divider. Unfortunately, a divide-by-eight would
limit the ef fective modulus of the f eedback divider path t o
multiples of eight. The limitation would restrict the ability
of the PLL to achieve a desired input-frequency-to-
output-f requenc y ratio without m ak ing both the R eferenc e
and Feedback Divider values comparatively large. Large
divider moduli are generall y undesir able due to increase d
phase jitter.
Figure 3: Feedback Divider
Dual-
Modulus
Prescaler
A
Counter
M
Counter
f
vco
To understand the operation, refer to Figure 3. The M-
counter (with a m odulus of M) is cascaded with the dual-
modulus presc aler. If the pres cal er m odulus were f ixed at
N, the overall modulus of the feedback divider chain
would be M×N. However, the A-counter causes the
prescaler modulus to be alter ed to N+1 for the f irst A out-
puts of the prescaler. The A-counter then causes the
dual-modulus prescaler to revert to a modulus of N until
the M-counter reaches its terminal state and resets the
entire divider. The overall modulus can be expressed as
)()1( AMNNA −++ ,
where M ≥ A, which simplifies toANM +× .
4.1.3 Feedback Divider Programming
The requirement that M≥A means that the Feedback Di-
vider can only be pr ogrammed f or certain va lues below a
divider modulus of 56. The selection of divider values is
listed in Table 2.
If the desired Feedback Divider is less than 56, find the
divider value in the tabl e. Follo w the c o lumn up to f in d th e
A-count er pr ogram val ue. Fo l lo w the row to the left to f ind
the M-counter value.
Above a modulus of 56, the Feedback Divider can be
programm ed to an y value up t o 16383. See both T able 3
and Table 8 for additional programming information.
Table 2: Feedback Modulus Below 56
A-COUNTER: FBKDIV[2:0]
M-COUNTER:
FBKDIV[13:3] 000 001 010 011 100 101 110 111
00000000001 89------
00000000010 161718-----
00000000011 24 25 26 27 - - - -
00000000100 32 33 34 35 36 - - -
00000000101 40 41 42 43 44 45 - -
00000000110 48 49 50 51 52 53 54 -
00000000111 56 57 58 59 60 61 62 63
FEEDBACK DIVIDER MODULUS
4.1.4 Post Divider
The Post Divider consists of three individually program-
mable dividers, as shown in Figure 4.
Figure 4: Post Divider
Post
Divider 1
(N
P1
)
Post
Divider 2
(N
P2
)
Post
Divider 3
(N
P3
)
POST3[1:0]POST2[1:0]POST1[1:0]
POST DIVIDER (N
Px
)
f
out
f
GBL
The moduli of the individual dividers are denoted as NP1,
NP2, and NP3, and together they make up the array
modulus NPx.
321 PPPPx NNNN ××=
4
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
The Post Divider perform s several useful functions. First,
it allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it
changes the bas ic PLL equa ti on to
÷
÷
ø
ö
ç
ç
è
æ
÷
÷
ø
ö
ç
ç
è
æ
=PxR
F
REFCLK NN
N
ff 1.
The extra integer in the denominator permits more flexi-
bility in the programming of the loop for many applica-
tions where frequencies must be achieved exactly.
Note that a nominal 50/50 duty factor is preserved for
selections which have an odd modulus.
4.2 Phase Adjust and Sampling
In line-loc ked or ge nloc ked appl icati ons , it is nec ess ary to
know the ex act phase re lation of the output clock relative
to the input clock. Since the VCO is included within the
feedback loop in a simple PLL structure, the VCO output
is exactl y phase aligned with the input clock. Every c ycle
of the input clock equals NR/NF cycles of the VCO clock.
Figure 5: Simple PLL
Phase
Frequency
Detect
Feedback
Divider (N
F
)
VCO
f
IN
f
OUT
Reference
Divider (N
R
)
f
IN
f
OUT
The addition of a Post Divider, while adding flexibility,
makes the phase relation between the input and output
clock unknown because the Post Divider is outside the
feedback loop.
Figure 6: PLL with Post Divider
Phase
Frequency
Detect
Feedback
Divider (N
F
)
VCO
f
IN
f
OUT
Reference
Divider (N
R
)
f
IN
f
VCO
Post
Divider (N
F
)
f
VCO
f
OUT
?
4.2.1 Clock Gobbler (Phase Adjust)
The Clock Gobbler circuit takes advantage of the un-
known relationship between input and output clocks to
permit the adjustment of the CLKP/CLKN output clock
phase relat i ve to the REF in put. The Cloc k Gobbl er c irc uit
removes a VCO clock pulse before the pulse clocks the
Post Divider. In this way, the phase of the output clock
can be slipped until the output phase is aligned with the
input clock phase.
To adjust the phase relationship, switch the Feedback
Divider source to the Post Divider input via the
FBKDSRC bit , and toggle the GBL re gister b it. The Cloc k
Gobbler out put clock is dela yed b y one VCO cl ock period
for each transition of the GBL bit from zero to one.
4.2.2 Phase Alignment
To maintain a fixed phase relation between input and
output clocks, the Post Divider m ust be placed ins ide the
feedback loop. The source for the Feedback Divider is
obtained from the output of the Post Divider via the
FBKDSRC switch. I n additio n, t he Feedbac k Divi der must
be dividing at a multiple of the Post Divider.
Figure 7: Aligned I/O Phase
Phase
Frequency
Detect
Feedback
Divide r (N
F
)
VCO
f
IN
f
OUT
Reference
Divide r (N
R
)Post
Divide r (N
F
)
f
IN
f
OUT
4.2.3 Phase Sampling and Initial Alignment
However, the ability to adjust the phase is useless with-
out knowing the initial relation between output and input
phase. To aid in the initial synchronization of the output
phase to input phase, a Phase Align “flag” makes a tran-
sition (zero to one or one to zero) when the output clock
phase becom es aligned with the feedback source phase.
The feedback source clock is, by definition, locked to the
input clock phase.
First, the F S6131 is used to sample t he output c lock with
the feedback source clock and set/clear the Phase Align
flag when the two clocks match to within a feedback
source clock period. Then, the Clock Gobbler is used to
delay the output phase relative to the input phase one
VCO clock at a time until a transition on the flag occurs.
W hen a transitio n occurs, the output and input c lock s are
phase align ed.
5
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
g
rammable Line Lock Clock Generator I C
Pro
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rammable Line Lock Clock Generator I CPro
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rammable Line Lock Clock Generator I C
Pro
g
rammable Line Lock Clock Generator I C
To enter this mode, set STAT[1] to one and clear
STAT[0] to zero. If the CMOS bit is set to one, the
LOCK/IPRG pin can display the flag. The flag is always
available under software control by reading back the
STAT[1] bit, which will be overwritten by the flag in this
mode.
4.2.4 Feedback Divider Monitoring
The Feedback Divider clock can be brought out the
LOCK/IPRG pin independent of the output clock to allow
monitoring of the Feedback Divider clock. To enter this
mode, set both the ST AT[1] and STAT [0] bits to one. T he
CMOS bit must also be set to one to enable the
LOCK/IPRG pin as an output.
4.3 Loop Gain Analysis
For applications where an external loop filter is required,
the following analysis exam ple can be used to de termine
loop gain and stability.
The loop gain of a PLL is the product of all of the gains
within the loop.
Establish the basic operating parameters:
Set the charge pump current: AIchgpump
µ
10=
Set the loop filter values:
pFC
FC
kRLF
220
015.0
15
2
1=
=Ω=
µ
Set the VCO gain (VCOSPD): VMHzAVCO /230=
Set the Feedback Divider: 3500=
F
N
Set the Reference frequency (at the input to the Phase
Detector: kHzfREF 20=
The transfer function of the Phase Detector and Charge
Pump combination is (in A/rad):
π
2
chgpump
PD
I
K=
The transfer function of the loop filter is (in V/A):
÷
÷
÷
÷
ø
ö
ç
ç
ç
ç
è
æ
÷
ø
ö
ç
è
æ
+
+
=
1
21
1
1
)(
sC
R
sC
sK
LF
LF
The VCO transfer function (in rad/s, and accounting for
the phase integration that occurs in the VCO) is:
s
AsK VCOVCO 1
2)(
π
=
The transfer function of the Feedback Divider is:
F
FN
K1
=
Finally, the sampling effect that occurs in the Phase De-
tector is accounted for by:
REF
f
s
SAMP f
s
e
sK REF
÷
÷
÷
ø
ö
ç
ç
ç
è
æ−
=
÷
ø
ö
ç
è
æ
−
1
)(
The loop gain of the PLL is: )()()()( sKKsKsKKsK SAMPFVCOLFPDLOOP =
Figure 8: Loop Gain vs. Frequency
0.01
Frequency (f
i
)
0.1
0.1kHz 1kHz 10kHz 100kHz
1
10
100
Amplitude
6
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
The loop phase angle is:
[
]
)
2(arg iLOOPi fjK
π
=Θ .
Figure 9: Loop Phase vs. Frequency
-150°
Frequency (f
i
)
-100°
Phase
0.1kHz 1kHz 10kHz 100kHz
A Nyquist plot of gain vs. amplitude is shown below.
Figure 10: Loop Nyquist Plot
45°
0°
315°
270°
225°
180°
135°
90°
0.2
0.4
0.6
0.8
1.0
Phase
Amplitude
1.2
Gain Margin
Phase
Margin
4.4 Voltage-Controlled Crystal Oscillator
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6131 system components.
Loading capacitance for the crystal is internal to the de-
vice. No external components (other than the resonator
itself) are required for operation of the VCXO.
The resonator loading capacitance is adjustable under
register control. This feature permits factory coarse tun-
ing of inexpensive resonators to the necessary precision
for digital video applications. Continuous fine-tuning of
the VCXO fr equency is accomplis hed by varying the volt-
age on the XTUNE pin. The total change (from one ex-
treme to the other) in effective loading capacitance is
1.5pF nom inal, and the effect is shown in Figure 11. The
oscillator operates the crystal resonator in the parallel-
resonant mode. Crystal warping, or the “pulling” of the
crystal oscillation frequency, is accomplished by altering
the eff ective load ca pacitance presented to the crystal b y
the oscillator circuit. T he actual amount that changin g the
load capacitance alters the oscillator frequency will be
dependent o n the charac teristics of the cr ystal as well as
the oscillator circuit itself.
The motional capacitance of the crystal (usually referred
to by crystal m anufacturer s as C1), the stat ic capacita nce
of the crystal (C0), and the load capacitance (CL) of the
oscillator determine the warping capability of the crystal
in the oscillator circuit. A simple formula to determine the
total warping capability of a crystal is
()
()()
CCCC CCC
ppmf LL
LL
1020
6
121
210
)( +×+× ×−×
=∆ ,
where CL1 and CL2 are the two extremes of the applied
load capacitance obtained from Table 11.
Example: A crystal with the following parameters is used
with the FS6131. The total coarse tuning range is:
C1=0.02pF, C0=5.0pF, CL1=10.0pF, CL2=22.66pF
()
()()
ppm
.
..
f305
105662252 10106622020 6=
+×+× ×−×
=∆
7
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
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rammable Line Lock Clock Generator I C
Pro
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rammable Line Lock Clock Generator I CPro
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rammable Line Lock Clock Generator I C
Pro
g
rammable Line Lock Clock Generator I C
4.4.1 VCXO Tuning
The VCX O may be coars e tuned by a programm able ad-
justment of the crystal load capacitance via the XCT[3:0]
control bits. See Table 11 for the control code and the
associated loading capacitance.
The actual amount of frequency warping caused by the
tuning capacitance will depend on the crystal used. The
VCXO tuning capacitance includes an external 6pF load
capacitance (12pF from the XIN pin to ground and 12pF
from the XOUT pin to ground). The fine tuning capability
of the VCXO can be enabled by setting the XLVTEN bit
to a one, or disabled by setting it to a zero.
Figure 11 shows the typical effect of the coarse and fine
tuning m echanism s. The total coars e tune rang e is about
350ppm. The difference in VCXO frequency in parts per
million (ppm) is shown as the fine tuning voltage on the
XTUNE pi n varies f rom 0V to 5 V. Note that as the crysta l
load capacitance is increased the VCXO frequency is
pulled som ewhat less with each c oarse s tep, and the fine
tuning range decreases. The fine tuning range always
overlaps a few coarse tu ning ranges , elim inating th e pos-
sibility of holes in the VCXO response. The different
cr ystal warpin g charac t er is tics ma y change th e s c al ing o n
the Y-axis, but not the overall characteristic of the curves.
Figure 11: VCXO Coarse and Fine Tuning
VCXO Range (ppm) vs. XTUNE Voltage (V)
-200
-150
-100
-50
0
50
100
150
200
0123456789101112131415
Coarse Tune S et ti ng XCT[3: 0]
VCXO Range (ppm)
XTUN E Vo lta g e = 0.0V
XTUN E Vo lta g e = 5.0V
4.5 Crystal Loop
The Crystal Loop is designed to attenuate the jitter on a
highly jittered, low-Q, low frequency reference. The
Crystal Lo op can als o m aintain a co nstant f requenc y out-
put into the Main Loop if the low frequency reference is
intermittent.
The Crystal Loop consists of a Voltage-Controllable
Crystal Os c ill ator (VCX O ), a di vi der, a PF D , and a c h arge
pump that tu nes th e VCX O to a f requenc y ref erence. T he
frequency reference is phase-locked to the divided fre-
quency of an external, high-Q, jitter-free crystal, thereby
lock ing the VCXO to the ref erence f requenc y. The VCXO
can continue to run off the crystal even if the frequency
reference becomes intermittent.
4.5.1 Locking to an External Frequency Source
When the Crystal Loop is synchronized to an external
frequency source, the FS6131 can monitor the Crystal
Loop and detect if the loop unlocks from the external
source. The Crystal Loop tries to drive to zero frequency
if the external source is dr opped, and sets a L ock Status
error flag.
The Crystal Loop can also detect if the VCXO has
dropped out of the Fine Tune range, requiring a change
to the Coarse Tune. The Lock Status also latches the
direction the loop went out of range (high or low) when
the loop became unlocked.
4.5.1.1 Crystal Loop Lock Status Flag
To enabl e this m ode, clear the ST AT[1] and ST AT[0] bits
to zero. If the CMOS bit is s et to one, the LO C K/IP RG pi n
will be low if the Crystal Loop becomes unlocked. The
flag is al ways avail able under s oft ware control by readin g
back the STAT[1] bit, which is overwritten with a the
status flag (low = unlocked) in this mode (see Table 6).
8
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
4.5.1.2 Out-Of-Range High/Low
The direction the loop has gone out-of-range can be de-
term ined b y c lear ing STAT [1] to zero and s etti ng ST AT[0]
bit to one. If the CMOS bit is set to one, the LOC K/IPRG
pin will go high if the Crystal Loo p went o ut of r ange h igh.
If the pin goes to a logic-low, the loop went out of range
low.
The out-of-range information is also available under soft-
ware control by reading back the STAT[1] bit, which is
overwritten by the flag (high = out-of-range high, low =
out-of-range low) in this mode. The bit is set or cleared
only if the Crystal Loop loses lock (see Table 6).
4.5.1.3 Crystal Loop Disable
The Crystal Loop is disabled by setting the XLPDEN bit
to a logic-high (1). The bit disables the charge pump cir-
cuit in the loop.
Setting the X LPDEN bit low (0) perm its the cr ystal loo p to
operate as a control loop.
4.6 Connecting the FS6131 to an
External Reference Frequency
If a crystal oscillator is not used, tie XIN to ground and
shut down the crystal oscillator by setting XLROM[2:0]=1.
The REF and FBK pins do not have pull-up or pull-down
current, but do have a small amount of hysteresis to re-
duce the possibility of extra edges. Signals may be AC-
coupled into these inputs with an external DC-bias circuit
to generate a DC-bias of 2.5V. Any Reference or Feed-
back signal should be square for best results, and the
signals should be rail-to-rail. Unused inputs should be
grounded to avoid unwanted signal injection.
4.7 Differential Output Stage
The differential output stage supports both CMOS and
pseudo- ECL (PE CL) signa ls . T he des ired outpu t i nterface
is chosen via the program registers (see Table 4).
If a PECL interface is used, the transmission line is usu-
ally terminated using a Thévenin termination. The output
stage can only sink current in the PECL mode, and the
amount of sink current is set by a programming resistor
on the LOCK/IPRG pin. The ratio of IPRG current to out-
put driv e current is s hown in Fi gure 12. Sourc e curre nt is
provided by the pull-up resistor that is part of the
Thévenin termination.
Figure 12: IPRG to CLKP/CLKN Current
0.0
5.0
10.0
15.0
20.0
25.0
0 20406080
CLKP/CLKN PE CL O u tp u t Cu r r ent (mA)
IPRG Input Current (mA)
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Pro
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Pro
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5.0 I2C-bus Control Interface
This device is a read/write slave device
meeting all Philips I2C-bus specifications
except a “general call.” The bus has to be
controlled by a master device that generates
the serial c lock SCL, controls bus acc ess, and generates
the START and STOP conditions while the device works
as a slave. Both master and slave can operate as a
transmitter or receiver, but the master device determines
which mode is activated. A device that sends data onto
the bus is defined as the transmitter, and a device re-
ceiving data as the receiver.
I2C-bus logic leve ls noted herein ar e based o n a percent-
age of the power supply (VDD). A logic-one corresponds
to a nominal voltage of VDD, while a logic-zero corre-
sponds to ground (VSS).
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line while the clock line is
high will be interpreted by the device as a START or
STO P conditio n. T he foll owing bus c ondit ions ar e define d
by the I2C-bus protocol.
5.1.1 Not Busy
Both the dat a (SD A) a nd clock (SCL) lin es r em ain hi gh t o
indicate the bus is not bus y.
5.1.2 START Data Transfer
A high to lo w transition of the SDA line while the SCL in-
put is high indicates a START condit ion. A ll co m mands to
the device must be preceded by a START condition.
5.1.3 STOP Data Transfer
A low to high transit ion of the SD A line wh ile SCL is he ld
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
5.1.4 Data Valid
The state of the SD A l in e repr es e nts val id d ata if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the first eight bytes will overflow into the first
register, then the second, and so on, in a first-in, first-
overwritten fashion.
5.1.5 Acknowledge
W hen addressed, the rece iving dev ice is r equired to g en-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The mas ter mus t signal an e nd of data t o t he s l av e by not
generating and acknowledge bit on the last b yte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to enable the master
to generate a STOP condition.
5.2 I2C-bus Operation
All program mable register s can be accessed r andomly or
sequentially via this bi-directional two wire digital inter-
face. T he crystal oscillator does not have to run for com -
munication to occur.
The device accepts the following I2C-bus commands:
5.2.1 Slave Address
After generating a START condition, the bus master
broadcasts a seven-bit slave address followed by a R/W
bit. The address of the device is:
A6 A5 A4 A3 A2 A1 A0
1011X00
where X is controlled by the logic level at the ADDR pin.
The variable ADDR bit allows two different FS6131 de-
vices t o exist on the s am e bus. Not e that e ver y device on
an I2C-bus must have a unique address to avoid bus
conflicts. The default address sets A2 to 0 via the pull-
down on the ADDR pin.
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Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
5.2.2 Random Register Write Procedure
Random write operations allow the master to directly
write to any register. To initiate a write procedure, the
R/W bit that is transmitted after the seven-bit device ad-
dress is a l og ic -lo w. T his i nd ic ates to the ad dr ess ed s l av e
device that a register address will follow after the slave
device acknowledges its device address. The register
address is written into the slave’s address pointer. Fol-
lowing an acknowledge by the slave, the master is al-
lowed to write eight bits of data into the addressed regis-
ter. A final acknowledge is returned by the device, and
the master generates a STOP condition.
If either a STOP or a repeated START condition occurs
during a Register Write, the data that has been trans-
ferred is ignored.
5.2.3 Random Register Read Procedure
Random read operatio ns allo w the m as ter to direc tl y read
from any register. T o perform a read procedure, the R/W
bit that is transmitted after the seven-bit address is a
logic-low, as in the Register Write procedure. This indi-
cates to the addressed slave device that a register ad-
dress will follow after the slave device acknowledges its
device address. The register address is then written into
the slave’s address pointer.
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this tim e to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
the eight- bit word. T he master does not acknowledg e the
transfer but does generate a STOP condition.
5.2.4 Sequential Register Write Procedure
Sequential write operations allow the master to write to
each register in order. The register pointer is automati-
cally incremented after each write. This procedure is
more efficient than the Random Register Write if several
registers must be written.
To initiate a write procedure, the R/W bit that is transmit-
ted after th e seven-b it device addr ess is a l ogic-low. This
indicates to the addressed slave device that a register
address will follow after the slave device acknowledges
its device address. The register address is written into the
slave’s address pointer. Following an acknowledge by the
slave, the master is allowed to write up to eight bytes of
data into the addressed register before the register ad-
dress pointer overflows back to the beginning address.
An acknowledge by the device between each byte of data
must occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not
wait for the STOP condition to occur. Registers are
therefore updated at different times during a Sequential
Register Write.
5.2.5 Sequential Register Read Procedure
Sequent ial read operatio ns allow the m aster to r ead from
each register in order. The register pointer is automati-
call y increm ented b y one after e ach read. T his proc edure
is more efficient than the Random Register Read if sev-
eral registers must be read.
To perform a read procedure, the R/W bit that is trans-
mitted af ter the se ven-bit addr ess is a logic- low, as in the
Register W rite procedur e. This ind icates to th e a ddres s ed
slave device that a register address will follow after the
slave device acknowledges its device address. The reg-
ister address is then written into the slave’s address
pointer.
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this tim e to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
all eight bytes of data starting with the initial addressed
register. The register address pointer will overflow if the
initial register address is larger than zero. After the last
byte of data, the master does not acknowledge the
transfer but does generate a STOP condition.
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Figure 13: Random Register Write Procedure
AA DATAW A
From bus host
to device
S REGISTER ADDRESS P
From device
to bus host
DEVICE ADDRESS
Register Address
Acknowledge STOP Condition
Data
Acknowledge
Acknowledge
START
Command WRITE Command
7-bit Receive
Device Address
Figure 14: Random Register Read Procedure
AR AAAWS REGISTER ADDRESS PS DEVICE ADDRESS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge READ Command
Acknowledge
Data
NO Acknowledge
STOP Condition
From bus host
to device From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS DATA
Repeat START
Figure 15: Sequential Register Write Procedure
AAAWS P
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Data
Acknowledge
Data
STOP Command
AcknowledgeAcknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS DATA DATA DATA
Figure 16: Sequential Register Read Procedure
AWS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge READ Command
NO Acknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address 7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS AR A PS DEVICE ADDRESS DATA DATA
Repeat START
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Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
6.0 Programming Information
All register bits are cleared to zero on power-up. All register bits may be read back as written except STAT[1] (Bit 63).
Table 3: Register Map
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STAT[1]
(Bit 63) STAT[0]
(Bit 62) XLVTEN
(Bit 61) CMOS
(Bit 60) XCT[3]
(Bit 59) XCT[2]
(Bit 58) XCT[1]
(Bit 57) XCT[0]
(Bit 56)
00 = Crystal Loop – Lock Status
01 = Crystal Loop – Out of Range 0 = Fine Tune
Inactive 0 = PECL
10 = Main Loop – Phase Status
BYTE 7
11 = Feedback Divider Output 1 = Fine Tune
Active 1 = CMOS, Lock
Status
VCXO Coarse Tune
See Table 11
XLPDEN
(Bit 55) XLSWAP
(Bit 54) XLCP[1]
(Bit 53) XLCP[0]
(Bit 52) XLROM[2]
(Bit 51) XLROM[1]
(Bit 50) XLROM[0]
(Bit 49) GBL
(Bit 48)
00 = 1.5
µ
A
0 = Crystal Loop
Operates 0 = Use with
External VCXO 01 = 5
µ
A0 = No Clock
Phase Adjust
10 = 8
µ
A
BYTE 6
1 = Crystal Loop
Powered Down 1 = Use with
Internal VCXO 11 = 24
µ
A
Crystal Loop Control
See Table 10 1 = Clock Phase
Delay
OUTMUX[1]
(Bit 47) OUTMUX[0]
(Bit 46) OSCTYPE
(Bit 45) VCOSPD
(Bit 44) LFTC
(Bit 43) EXTLF
(Bit 42) MLCP[1]
(Bit 41) MLCP[0]
(Bit 40)
00 = VCO Output 00 = 1.5
µ
A
01 = Reference Divider Output 0 = Low Phase
Jitter Oscillator 0 = High Speed
Range 0 = Short Time
Constant 0 = Internal Loop
Filter 01 = 5
µ
A
10 = Phase Detector Input 10 = 8
µ
A
BYTE 5
11 = VCXO Output 1 = FS6031
Oscillator 1 = Low Speed
Range 1 = Long Time
Constant 1 = External Loop
Filter 11 = 24
µ
A
FBKDSRC[1]
(Bit 39) FBKDSRC[0]
(Bit 38) FBKDIV[13]
(Bit 37) FBKDIV[12]
(Bit 36) FBKDIV[11]
(Bit 35) FBKDIV[10]
(Bit 34) FBKDIV[9]
(Bit 33) FBKDIV[8]
(Bit 32)
00 = Post Divider Output
01 = FBK Pin 8192 4096 2048 1024 512 256
10 = Post Divider Input
BYTE 4
11 = FBK Pin M Counter
FBKDIV[7]
(Bit 31) FBKDIV[6]
(Bit 30) FBKDIV[5]
(Bit 29) FBKDIV[4]
(Bit 28) FBKDIV[3]
(Bit 27) FBKDIV[2]
(Bit 26) FBKDIV[1]
(Bit 25) FBKDIV[0]
(Bit 24)
128 64 32 16 8 4 2 1
BYTE 3
M Counter A Counter – See Table 2
POST3[1]
(Bit 21) POST3[1]
(Bit 20) POST2[1]
(Bit 19) POST2[0]
(Bit 18) POST1[1]
(Bit 17) POST1[0]
(Bit 16)
00 = Divide by 1 00 = Divide by 1 00 = Divide by 1
01 = Divide by 3 01 = Divide by 3 01 = Divide by 2
10 = Divide by 5 10 = Divide by 5 10 = Divide by 4
BYTE 2 Reserved (0) Reserved (0)
11 = Divide by 4 11 = Divide by 4 11 = Divide by 8
PDFBK
(Bit 15) PDREF
(Bit 14) SHUT
(Bit 13) REFDSRC
(Bit 12) REFDIV[11]
(Bit 11) REFDIV[10]
(Bit 10) REFDIV[9]
(Bit 9) REFDIV[8]
(Bit 8)
0 = Feedback
Divider 0 = Reference
Divider 0 = Main Loop
Operates 0 = VCXO
BYTE 1
1 = FBK Pin 1 = REF Pin 1 = Main Loop
Powered Down 1 = Ref Pin 2048 1024 512 256
REFDIV[7]
(Bit 7) REFDIV[6]
(Bit 6) REFDIV[5]
(Bit 5) REFDIV[4]
(Bit 4) REFDIV[3]
(Bit 3) REFDIV[2]
(Bit 2) REFDIV[1]
(Bit 1) REFDIV[0]
(Bit 0)
BYTE 0 128 64 32 16 8 4 2 1
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Pro
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Pro
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Table 4: Device Configuration Bits
NAME DESCRIPTION
REFerence Divider SouRCe
Bit = 0 Crystal Oscillator (VCXO)
REFDSRC
(Bit 12) Bit = 1 REF pin
main loop SHUT down select
Bit = 0 Disabled (main loop operates)
SHUT
(Bit 13) Bit = 1 Enabled (mai n loop shuts down)
Phase Detector REFerence source
Bit = 0 Reference Divi der
PDREF
(Bit 14) Bit = 1 REF pin
Phase Detector FeedBacK source
Bit = 0 Feedback Divi der
PDFBK
(Bit 15) Bit = 1 FBK pin
FeedBacK Divider SouRCe
Bit 39 = 0
Bit 38 = 0 Post Divi der Output
Bit 39 = 0
Bit 38 = 1 FBK pin
Bit 39 = 1
Bit 38 = 0 VCO Output (Post Divider Input )
FBKDSRC[1:0]
(Bits 39-38)
Bit 39 = 1
Bit 38 = 1 FBK pin
EXTernal Loop Filter select
Bit = 0 Internal Loop Filter
EXTLF
(Bit 42) Bit = 1 EXTLF pin
OSCillator TYPe
Bit = 0 Low Phase Jitter Oscillator
OSCTYPE
(Bit 45) Bit = 1 FS6031 Compatible Oscillator
OUT put MUltipleXer select
Bit 47 = 0
Bit 46 = 0 Main Loop PLL (VCO Output)
Bit 47 = 0
Bit 46 = 1 Reference Divi der Output
Bit 47 = 1
Bit 46 = 0 Phase Detector Input
OUTMUX[1:0]
(Bits 47-46)
Bit 47 = 1
Bit 46 = 1 VCXO Output
clock GobBLer control
Bit = 0 No Clock Phase Adjust
GBL
(Bit 48) Bit = 1 Clock Phase Delay
CLKP/CLKN out put mo de
Bit = 0 PECL Output
(positi ve-E CL output dri ve)
CMOS
(Bit 60) Bit = 1 CMOS Output /
Lock Status Indicator
Table 5: LOCK/IPRG Pin Configuration Bits
NAME DESCRIPTION
crystal loop lock STATus mode /
main loop phase align STATus mode
(see also Table 6)
Bit 63 = 0
Bit 62 = 0 Crystal Loop Lock st atus:
Locked or Unlocked
Bit 63 = 0
Bit 62 = 1 Crystal Loop Lock st atus:
Out of Range High or Low
Bit 63 = 1
Bit 62 = 0 Main Loop Phase Align stat us
STAT[1:0]
(Bits 63-62)
Bit 63 = 1
Bit 62 = 1 Feedback Divider out put
Table 6: Lock Status
CMOS STAT
[1] STAT
[0] LOCK /
IPRG PIN STAT[1]
READ STATUS
1 1 Locked
100 0 0 Unlocked
00
Out-of-
Range: Low
101 11
Out-of-
Range: High
Table 7: Main Loop Tuning Bits
NAME DESCRIPTION
VCO SPeeD range select (see Table 16)
Bit = 0 High Speed Range
VCOSPD
(Bit 44) Bit = 1 Low Speed Range
Main Loop Charge Pump current
Bit 41 = 0
Bit 40 = 0 Current = 1.5µA
Bit 41 = 0
Bit 40 = 1 Current = 5µA
Bit 41 = 1
Bit 40 = 0 Current = 8µA
MLCP[1:0]
(Bits 41-40)
Bit 41 = 1
Bit 40 = 1 Current = 24µA
Loop Filter Time Constant (internal)
Bit = 0 Short Time Constant: 13.5µs
LFTC
(Bit 43) Bit = 1 Long Time Constant: 135µs
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Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
Table 8: Divider Control Bits
NAME DESCRIPTION
REFDIV[11:0]
(Bits 11-0) REFerence DIVider (NR)
FeedBacK DIVider (NF)
FBKDIV[2:0] A-Counter Val ue
FBKDIV[13:0]
(Bits 37-24) FBKDIV[13: 3] M-Counter Value
POST Divider #1 (NP1)
Bit 17 = 0
Bit 16 = 0 Divide by 1
Bit 17 = 0
Bit 16 = 1 Divide by 2
Bit 17 = 1
Bit 16 = 0 Divide by 4
POST1[1:0]
(Bits 17-16)
Bit 17 = 1
Bit 16 = 1 Divide by 8
POST Divider #2 (NP2)
Bit 19 = 0
Bit 18 = 0 Divide by 1
Bit 19 = 0
Bit 18 = 1 Divide by 3
Bit 19 = 1
Bit 18 = 0 Divide by 5
POST2[1:0]
(Bits 19-18)
Bit 19 = 1
Bit 18 = 1 Divide by 4
POST Divider #3 (NP3)
Bit 21 = 0
Bit 20 = 0 Divide by 1
Bit 21 = 0
Bit 20 = 1 Divide by 3
Bit 21 = 1
Bit 20 = 0 Divide by 5
POST3[1:0]
(Bits 21-20)
Bit 21 = 1
Bit 20 = 1 Divide by 4
Reserved (0)
(Bits 23-22) Set these reserved bits to 0
Table 9: Crystal Loop Tuning Bits
NAME DESCRIPTION
Crystal Loop Charge Pump current
Bit 53 = 0
Bit 52 = 0 Current = 1.5µA
Bit 53 = 0
Bit 52 = 1 Current = 5µA
Bit 53 = 1
Bit 52 = 0 Current = 8µA
XLCP[1:0]
(Bits 53-52)
Bit 53 = 1
Bit 52 = 1 Current = 24µA
XLROM[2:0]
(Bits 51-49) Crystal Loop Divider ROM select and Crystal
Oscillator Power-Down (see Table 10)
Crystal Loop Voltage fine Tune ENable
Bit = 0 Disabled (fine t une is inacti ve)
XLVTEN
(Bit 61) Bit = 1 Enabled (fine tune is active)
Crystal Loop SW AP polarity
Bit = 0
Use with an external VCXO that
increases i n frequenc y in re-
sponse to an increasing voltage
at the XTUNE pin.
XLSWAP
(Bit 54)
Bit = 1
Use with a VCXO that increases
in frequency i n response to a
decreasing volt age at the XTUNE
pin.
Use this setting for Intern al
VCXO
Cry stal Loop Power Down Enable
Bit = 0 Disabled (crystal loop operates)
XLPDEN
(Bit 55) Bit = 1 Enabled
(cryst al loop is powered down)
XCT[3:0]
(Bits 59-56) Crystal Coarse Tune (see Table 11)
Table 10: Crystal Loop Control ROM
XLROM
[2] XLROM
[1] XLROM
[0] VCXO
DIVIDER CRYSTAL
FREQUENCY (MHz)
0001 -
0 0 1 3072 24.576
0 1 0 3156 25.248
0 1 1 2430 19.44
1 0 0 2500 20.00
1 0 1 4000 32.00
1 1 0 3375 27.00
1 1 1 Crystal Oscillator Power-Down
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Pro
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6.1 VCXO Coarse Tune
The VCX O may be coars e tuned by a programm able ad-
justment of the crystal load capacitance via XCT[3:0].
The actual amount of frequency warping caused by the
tuning capacitance will depend on the crystal used. The
VCXO tuning capacitance includes an external 6pF load
capacitance (12pF from the XIN pin to ground and 12pF
from the XOUT pin to ground). The fine tuning capability
of the VCXO can be enabled by setting the XLVTEN bit
to a logic-one, or disabled by setting the bit to a logic-
zero.
Table 11: VCXO Coarse Tuning Capacitance
XCT[3] XCT[2] XCT[1] XCT[0] VCXO TUNING
CAPACITANCE (pF)
0 0 0 0 10.00
0 0 0 1 10.84
0 0 1 0 11.69
0 0 1 1 12.53
0 1 0 0 13.38
0 1 0 1 14.22
0 1 1 0 15.06
0 1 1 1 15.91
1 0 0 0 16.75
1 0 0 1 17.59
1 0 1 0 18.43
1 0 1 1 19.28
1 1 0 0 20.13
1 1 0 1 20.97
1 1 1 0 21.81
1 1 1 1 22.66
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Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
7.0 Electrical Specifications
Table 12: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER SYMBOL MIN. MAX. UNITS
Supply Voltage, dc (VSS = ground) VDD VSS-0.5 7 V
Input Voltage, dc VIVSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (V I < 0 or VI > V DD)I
IK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD)I
OK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ150 °C
Lead Temperature (soldering, 10s) 260 °C
Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage res ulting in a loss of functional ity or performance may occur if this devic e is subjected to a high-energy elec-
trostatic discharge.
Table 13: Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Supply Voltage VDD 5V ± 10% 4.5 5 5.5 V
Ambient Operating Temperature Range TA070°C
Crystal Resonator Frequency fXIN 19.44 27 28 MHz
Crystal Resonator Load Capacitance C XL P aral l el resonant, AT cut 18 pF
Crystal Resonator Motional Capacit ance CXM P aral l el resonant , A T cut 25 fF
Serial Data Transfer Rat e Standard mode 10 100 400 kb/s
PECL Mode Programming Current
(LOCK/IPRG Pin High-Level Input Current) IIH PECL Mode 15 mA
Output Driver Load Capacitance CL15 pF
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Pro
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Tabl e 14: DC Electrical Sp ecifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic,
(with Loaded Outputs) IDD fCLK = 66MHz; CMOS Mode, VDD = 5.5V 100 mA
Supply Current, Static IDDL SHUT = 1, XLROM[2:0] = 7, XLPDEN = 1
VDD = 5.5V 12 mA
Serial Communication I/O (SDA, SCL)
High-Level Input V olt age VIH Outputs off 3.5 VDD+0.3 V
Low-Level Input V oltage VIL Outputs off VSS-0.3 1.5 V
Hysteresis Voltage * Vhys Outputs off 2 V
Input Leakage Current II-1 1 µA
Low-Level Output Sink Current (SDA) IOL VOL = 0.4V 20 32 mA
Tristate Output Current IZ-10 10 µA
Address S el ect I nput ( ADDR)
High-Level Input V olt age VIH 2.4 VDD+0.3 V
Low-Level Input V oltage VIL VSS-0.3 0.8 V
High-Level Input Current (pull-down) IIH VIH = V DD = 5.5V 5 16 30 µA
Low-Level Input Current IIL -2 2 µA
Reference Frequency Input (REF, FBK)
High-Level Input V olt age VIH 3.5 VDD+0.3 V
Low-Level Input V oltage VIL VSS-0.3 1.5 V
Hysteresis Voltage Vhys 500 mV
Input Leakage Current II-1 1 µA
Loop Filter Input (EXTLF)
Input Leakage Current IIEXTLF = 0 -1 1 µA
VO = 0.8V; EXTLF =1, MLCP[1:0] = 0 -1.5
VO = 0.8V; EXTLF =1, MLCP[1:0] = 1 -5
VO = 0.8V; EXTLF =1, MLCP[1:0] = 2 -8
High-Level Output Sourc e Current I OH
VO = 0.8V; EXTLF =1, MLCP[1:0] = 3 -24
µA
VO = 4.2V; EXTLF =1, MLCP[1:0] = 0 1.5
VO = 4.2V; EXTLF =1, MLCP[1:0] = 1 5
VO = 4.2V; EXTLF =1, MLCP[1:0] = 2 8
Low-Level Output Sink Current IOL
VO = 4.2V; EXTLF =1, MLCP[1:0] = 3 25
µA
Crystal Oscillator Input (XIN)
Threshold Bias Voltage VTH 1.5 2.2 3.5 V
High-Level Input Current IIH Outputs off; VIH = 5V 10 24 30 mA
Low-Level Input Current IIL Outputs off; VIL = 0V -10 -19 -30 mA
Crystal Loadi ng Capaci tance * CL(xtal) As seen by an external crystal connected
to XIN and XOUT; VCXO tuning disabled 10 pF
Input Loading Capacitance * CL(XIN) As seen by an external clock driver on
XOUT; XIN unconnect ed; VCXO disabled 20 pF
18
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Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
Table 15: DC Electrical Specifications, continued
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Crystal Oscillator Output (XOUT)
High-Level Output Sourc e Current I OH VO = 0V, float XIN -20 -30 -50 mA
Low-Level Output Sink Current IOL VO = 5V, float XIN -20 -40 -50 mA
VCXO Tuning I/O (XTUNE)
High-Level Input V olt age VIH Lock Stat us: Out of Range HIGH 3.2 VDD+0.3 V
Low-Level Input V oltage VIL Lock Stat us: Out of Range LOW VSS-0.3 0.3 V
Hysteresis Voltage Vhys 1.0 V
Input Leakage Current IIXLPDEN = 0 -1 1 µA
VO = 0.8V; XLCP[1 :0] = 0 -1.5
VO = 0.8V; XLCP[1 :0] = 1 -5
VO = 0.8V; XLCP[1 :0] = 2 -8
High-Level Output Sourc e Current I OH
VO = 0.8V; XLCP[1 :0] = 3 -24
µA
VO = 4.2V; XLCP[1 :0] = 0 1.5
VO = 4.2V; XLCP[1 :0] = 1 5
VO = 4.2V; XLCP[1 :0] = 2 8
Low-Level Output Sink Current IOL
VO = 4.2V; XLCP[1 :0] = 3 25
µA
Lock Indicator / PECL Current Program I/O (LOCK/IPRG)
Low-Level Input Current IIL PECL Mode -1 1 µA
High-Level Output Sourc e Current I OH CMOS Mode; VO = 2.4V -25 -38 mA
Low-Level Output Sink Current IOL CMOS Mode; VO = 0 .4V 5 9 mA
zOH VO = 0.5VDD; output driving hi gh 66
Output Impedance * zOL VO = 0.5VDD; output driving l ow 76 Ω
Short Circuit S ource Current * ISCH VO = 0V; shorted for 30s, max. -47 mA
Short Circuit S i nk Current * ISCL VO = 5V; shorted for 30s, max. 47 mA
Clock Outputs, CMOS Mode (CLKN, CLKP)
High-Level Output Sourc e Current I OH VO = 2.4V -45 -68 mA
Low-Level Output Sink Current IOL VO = 0.4V 15 20 mA
zOH VO = 0.5VDD; output driving hi gh 28
Output Impedance * zOL VO = 0.5VDD; output driving l ow 33 Ω
Short Circuit S ource Current * ISCH VO = 0V; shorted for 30s, max. -100 mA
Short Circuit S i nk Current * ISCL VO = 5V; shorted for 30s, max. 100 mA
Clock Outputs, PEC L Mode (CLKN, CLKP)
IPRG Current to Output Current Rat i o 1:4
Low-Level Output Sink Current IOL IPRG input current = 15mA 60 mA
Tristate Output Current IZ-10 10 µA
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Table 16: AC Timing Specifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK
(MHz) MIN. TYP. MAX. UNITS
Overall
CMOS Outputs 130
Output Frequency * fO(max) PECL Outputs 230 MHz
Low Phase Jitter Oscillator (OSCTYPE = 0)
VCOSPD = 0 40 160
VCOSPD = 1 40 100
FS6031 Compatible Oscillator (OSCTYPE = 1)
VCOSPD = 0 40 230
VCO Frequency * fVCO
VCOSPD = 1 40 140
MHz
Low Phase Jitter Oscillator (OSCTYPE = 0)
VCOSPD = 0 125
VCOSPD = 1 75
FS6031 Compatible Oscillator (OSCTYPE = 1)
VCOSPD = 0 130
VCO Gain * AVCO
VCOSPD = 1 78
MHz/V
LFTC = 0 13.5
Loop Filter Time Constant * LFTC = 1 135 µs
Rise Time * trCMOS Outputs, VO = 0 .5V to 4.5V; C L = 15pF 1.1 ns
Fall Time * tfCMOS Outputs, VO = 4. 5V to 0.5V; CL = 15pF 0.8 ns
Frequency Synthesis 200 µs
Lock Time (Main Loop) * Line Locked Modes (8kHz reference) 10 ms
Disable Time * From falling edge of SCL for the last data bit
(SHUT = 1 to 0) to output locked 10 µs
Divider Modulus
Feedback Divider NFFBKDIV[13:0] (See also Table 2) 8 16383
Reference Divider NRREFDIV[11:0] 1 4095
NP1 POST1[1:0] (See also Table 8) 1 8
NP2 POST2[1:0] (See also Table 8) 1 5Post Di vi der NP3 POS T 3[1:0] (S ee also Table 8) 1 5
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Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
Table 17: AC Timing Specifications, continued
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data at TA = 27°C and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK
(MHz) MIN. TYP. MAX. UNITS
Clock Output (CLKP, CLKN)
Duty Cycle * Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period 100 47 54 %
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
CL=15pF, fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054µF,
RLF=15.7kΩ, CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7 1.544 270
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
CL=15pF, fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246µF,
RLF=15.7kΩ, CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7 12.00 160
On rising edges 5ms apart at 2.5V relative to an ideal clock,
CL=15pF, fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015µF,
RLF=15.7kΩ, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7 25.175 100
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2 100 30
Jitter, Long Term (σy(τ)) * tj(LT)
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1 200 30
ps
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054µF, RLF=15.7kΩ,
CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7 1.544 140
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246µF, RLF=15.7kΩ,
CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7 12.00 130
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015µF, RLF=15.7kΩ,
CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7 25.175 105
From rising edge to next rising edge at 2.5V, CL=15pF,
CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2 100 340
Jitter, Period (peak-peak) * tj(∆P)
From rising edge to next rising edge at 2.5V, CL=15pF,
PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1 200 270
ps
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Table 18: Serial Interface Timing Specifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
STAND ARD MODE
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. MAX. UNITS
Clock frequency fSCL SCL 0 400 kHz
Bus free time between STOP and START tBUF 4.7 µs
Set up time, START (repeated) tsu:STA 4.7 µs
Hold time, START thd:STA 4.0 µs
Set up time, data input tsu:DAT SDA 250 ns
Hold time, data input thd:DAT SDA 0 µs
Output data valid from clock t AA Minimum delay to bridge undefined region of the falling
edge of SCL to avoid unintended START or STOP 3.5 µs
Rise time, data and clock tRSDA, SCL 1000 ns
Fall time, data and clock tFSDA, SCL 300 ns
High time, clock tHI SCL 4.0 µs
Low time, clock tLO SCL 4.7 µs
Set up time, STOP tsu:STO 4.0 µs
Figure 17: Bus Timing Data
SCL
SDA
~
~~
~~
~
STOP
t
su:STO
t
hd:STA
START
t
su:STA
ADDRESS OR
DATA VALID DATA CAN
CHANGE
Figure 18: Data Transfer Sequence
SCL
SDA
IN
t
hd:DAT
~
~
t
hd:STA
t
su:STA
t
su:STO
t
LO
t
HI
SDA
OUT
t
su:DAT
~
~~
~
t
BUF
t
R
t
F
t
AA
t
AA
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Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
Table 19: CLKP, CLKN Clock Outputs (CMOS Mode)
Low Drive Current (mA) High Drive Current (mA)
Voltage
(V) MIN. TYP. MAX. Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -58 -98 -153
0.2 7 11 15 0.5 -56 -96 -150
0.5 18 27 37 1 -55 -94 -148
0.7 24 36 50 1.5 -53 -91 -142
1 32 49 69 2 -49 -85 -135
1.2 37 56 80 2.5 -43 -77 -124
1.5 43 66 95 2.7 -40 -73 -119
1.7 46 72 103 3 -35 -67 -111
2 51 79 115 3.2 -31 -62 -105
2.2 53 83 122 3.5 -25 -54 -95
2.5 55 88 130 3.7 -21 -48 -87
2.7 56 91 135 4 -14 -39 -75
3 57 93 140 4.2 -8 -32 -67
3.5 58 95 146 4.5 0 -21 -53
4 59 97 149 4.7 -13 -44
4.5 59 99 152 5 0 -28
5 100 155 5.2 -17
5.5 158 5.5 0
-200
-150
-100
-50
0
50
100
150
200
- 0.51.01.52.02.53.03.54.04.55.05.5
Output Voltage (V)
Output Current (mA)
MIN
TYP
MAX
The data in this table represents nominal characterization data only.
Table 20: LOCK/IPRG Clock Output (CMOS Mode)
Low Drive Current (mA) High Drive Current (mA)
Voltage
(V) MIN. TYP. MAX. Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -35 -46 -61
0.2 4 4 4 0.5 -34 -45 -60
0.5 9 10 11 1 -33 -43 -57
0.7121315 1.5-31-41-54
1 161821 2 -28-37-50
1.2192125 2.5-24-33-45
1.5232630 2.7-23-31-42
1.7252933 3 -20-28-39
2 283238 3.2-17-26-36
2.2293541 3.5-14-22-32
2.5323845 3.7-11-19-29
2.7333948 4 -7-15-25
3 344251 4.2 -4-12-22
3.5354556 4.5 0 -8-17
4 354660 4.7 -5-14
4.5364662 5 0 -9
547635.2 -5
5.5 63 5.5 0
-80
-60
-40
-20
0
20
40
60
80
- 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Output Current ( m A)
MIN
TYP
MAX
The data in this table represents nominal characterization data only.
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8.0 Package Information
Table 21: 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.061 0.068 1.55 1.73
A1 0.004 0.0098 0.102 0.249
A2 0.055 0.061 1.40 1.55
B 0.013 0.019 0.33 0.49
C 0.0075 0.0098 0.191 0.249
D 0.386 0.393 9.80 9.98
E 0.150 0.157 3.81 3.99
e 0.050 BSC 1.27 BSC
H 0.230 0.244 5.84 6.20
h 0.010 0.016 0.25 0.41
L 0.016 0.035 0.41 0.89
Θ0°8°0°8°
Be
DA
1
SEATING PLANE
HE
16
1ALL RADII:
0.005" TO 0.01"
BASE PLANE
A
2
C
L
θ
7° typ.h x 45°
A
AMERICAN MICROSYSTEMS, INC.
R
Table 22: 16-pin SOIC (0.150") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 ft./mi n. 108 °C/W
Corner lead 4.0
Lead Inductanc e, Self L11 Center lead 3.0 nH
Lead Inductanc e, Mutual L12 Any lead to any adjacent l ead 0.4 nH
Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF
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Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
9.0 Ordering Information
9.1 Device Ordering Codes
ORDERING CODE DEVICE
NUMBER FONT PACKAGE TYPE OPERATING
TEMPERATURE RANGE SHIPPING
CONFIGURATION
11274-001 FS6131 -01 16-pin (0.150”) SOIC
(Small Outl i ne Package) 0°C to 70°C (Commercial) Tape-and-Reel
11274-011 FS6131 -01 16-pin (0.150”) SOIC
(Small Outl i ne Package) 0°C to 70°C (Commercial) Tubes
11274-901 FS6131 -01i 16-pin (0.150”) S O I C
(Small Outl i ne Package) -40°C to 85°C (Industrial) Tape-and-Reel
11274-911 FS6131 -01i 16-pin (0.150”) S O I C
(Small Outl i ne Package) -40°C to 85°C (Industrial) Tubes
9.2 Demo Kit Ordering Codes
ORDERING CODE KIT FOR DEVICE NUMBER: DESCRIPTI ON
11274-201 FS6131-01
Kit includes:
• Populated board with exampl e device
• Interface Cable
• Programming Assistance PC Software
Purchase of I2C components of Amer ican Micr os ystem s, Inc., or one of its subl icens ed Ass ociat ed Com pa-
nies conveys a license under Philips I2C P aten t Ri ghts to use t hes e c omponents in a n I2C system , pr ov id ed
that the system conforms to the I2C Standard Specification as defined by Philips.
Copyright © 1998, 1999 American Microsystems, Inc.
Devices sold by AMI are covered b y the warranty and pat ent indem nific ation pro visions ap pearing in its T erms of Sale
only. AMI m akes no warrant y, express, s tatutory im plied or b y descript ion, r egarding the i nfor m ation set f orth here in or
regarding t he f r eed om of the desc r ibed de vices f r om patent inf r ingement. AMI makes no warranty of m erc hantabi l ity or
fitness for any purpos es. AMI reserves the right to d iscont inue produc tion and ch ange spec ific ations and prices at any
time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring ex-
tended tem perature range, u nusual environm enta l requirem ents, or h igh reliab ilit y applications , such as m ilitary, m edi-
cal life-s uppor t or lif e- s us tain i ng e qu ipment, are sp ec if ic ally not recom mended witho ut ad d it ion al pr oc ess ing by AMI for
such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: t
g
p
@
amis.com
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10.0 Demonstration Board and Softw are
A simple dem onstration board and W indows 3.1x /95/98-based s oftware is available fr om Americ an Micros ystem s that
illustrates the ca pabilities of the FS6131. The sof tware can operat e under Windows NT but c annot comm unicate with
the board.
The board s chem atic is shown below. Com ponents listed with an as terisk (*) are not r equir ed in an actual ap plicat ion,
and are us e d here to pr es erv e s ignal in tegrity wit h th e c ab li ng ass oc iate d with t he bo ard. A ca bled interface b etwe en a
computer parallel port (DB25 connector) and the board (J1) is provided. Components shown in dashed lines are op-
tional, depending on the application.
Contact your local sales representative for more information.
Figure 19: Board Schematic
FS6131
SCL
SDA
ADDR
VSS
XIN
XOUT
XTUNE
VDD
CLKN
CLKP
VDD
FBK
REF
VSS
EXTLF
LOCK/
IPRG
RP1
1k
R3* 100
R2* 100
R1* 100
R5
10
C2
2.2µF C4
0.1µF
Y1
27MHz
CLKN
CLKP
SCL
SDA
ADDR
+5V
5
4
1
2
3
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
LOCK
J1*
6
+5V
+5V
GND
C8
12pF C9
12pF
R17R8
R9
C7
C6
R19R18
R7 47
R15
R13
R12 R14
+5V
+5V +5V
R6 47
R4
10
C1
2.2µF C3
0.1µF
+5V
R16
C11
C10
REF
FBK
AMERICAN
MICROSYSTEMS, INC.
FS6131 DEMO BOARD
26
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FS6131-01FS6131-01
FS6131-01
Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
10.1 Demo Kit Contents
• Demonstration board
• Interface cable (DB25 to 6-pin connector)
• Data sheet
• Programming software
10.2 Requirements
• PC running MS Windows 3.1x or 95/98 with an ac-
cessible parallel (LPT1) port. Software also runs on
Windows NT in a calculation mode only.
• 2.0MB available space on hard drive C:
10.3 Board Setup and Software
Installation Instructions
1. Run the self-expanding exe file to unzip the com-
pressed demo files to a directory of your choice.
2. Run the setup.exe file to install the programming
software.
3. Connect a +5 Volt po wer supply to th e board: RED =
+5V, BLAC K = ground.
4. Remove all software keys from the computer parallel
port. Connect the supplied interface cable to the par-
allel port (DB25 connector) and to the demo board (6-
pin connector). Make sure the cable is facing away
from the board. Pin 1 is the red wire per Figure 23.
5. Connect the clock outputs to the target application
board with a twisted-pair cable.
10.4 Demo Program Operation
Run the fs6131.exe program. Note that the
parallel port can not be accessed if your m achine
is runn ing W indows NT. A warning message will
appear s tati ng: “This vers ion of the dem o pr ogram cannot
communicate with the FS6131 hardware when running
on a Windows NT operating system. Do you want to
continue anyway, using just the calculation features of
this program?” Clicking OK starts the program for calcu-
lation onl y.
The opening screen is shown in Figure 20.
Figure 20: Opening Screen
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10.4.1 Device Mode
The Device Mode block presets the demo program to
program the FS6131 ei ther as a f requenc y synthesi zer (a
stand alone clock generator) or as a line-locked or gen-
lock clock generator.
Frequency Synthesis: For use as a stand alone clock
generator. Note that the Reference Source is the on-chip
crystal oscillator, the expected crystal frequency is
27MHz, and the Voltage Tune in the Crystal Oscillator
(i.e. the VCXO) is disabled. The default output frequency
(CLK freq.) requested is 100MHz, with a maximum error
of 10ppm, or about 100Hz. The Output Stage defaults to
CMOS mode.
Line-Locked/Genlock: For use in a line lock or genlock
application. Note that the Reference Source is the REF
Pin, and that the expected reference frequency is 8kHz.
The def ault o utp ut frequenc y requeste d is a 100x multiple
of the reference frequency.
10.4.2 Example: Frequency Synthesizer Mode
By default the demo program assumes the FS6131 is
configured as a stand alone clock generator. Note that
the Reference Source defaults to the on-chip crystal os-
cillator, t he ex pected cr ystal fr equenc y is 27MH z, and the
Voltage Tune in the Crystal Oscillator block (i.e. the
VCXO) is disabled. The default output frequency (CLK
freq.) requested is 100MHz, with a maximum error of
10ppm, or about 100Hz. The Output Stage defaults to
CMOS mode. The Loop Filter block is set to internal,
and the Check Loop Stability switch is on.
As an exercise, click on Calculate Solutions. The pro-
gram takes into account all of the screen settings and
calculates all possible combinations of Reference, Feed-
back, and Post Divider values that will generate the out-
put frequency (100MHz) from the input frequency
(27MHz) within the desired tolerance (10ppm).
A box will momentarily appear: “Calculating Solutions:
Press c ancel to stop with the sol utions ca lculated so f ar.”
A number in the box will inc rem ent for ever y uniqu e solu-
tion tha t is found. T his exam ple will create s ix uniqu e so-
lutions, whic h are t hen disp la yed in a windo w in t he lo wer
right portion of the program screen.
The best PLL performance is obtained by running the
VCO at as high a speed as possible. T he last three solu-
tions show a VCO speed of 200MHz. Furthermore, good
PLL performance is obtained with the smallest dividers
possible, which means solution #4 should provide the
best results.
Figure 21: Frequency Synthesizer Screen
Click ing on Solution #4 high lights t he ro w, and cl ick ing on
Disp/Save Register Values provides a window with the
final values of k ey settings. A click on OK then d ispla ys a
second window containing register information per the
Register Map. If the solutions are to be saved to a file,
two form ats ar e available : a t ext f orm at for vie wing , and a
data format for loading into the FS6131.
Clicking on Load Solution into Hardware (if enabled)
sends the inform ation in an I2C format to the FS6131 via
the parallel port. Note: This option is not available under
the Windows NT operating system.
If your operating system can support parallel port com-
munication but the connection cable is not attached, an
error message is displayed: "The FS6131 Hardware was
not detecte d! "Mak e sure that it is c onnected to the L PT#
printer port and that it is properly connected to a +5Volt
power supply."
28
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
10.4.3 Example: Line Locked Mode
Selecting the Line-Locked/Genlock option in the Device
Mode block changes the program default settings. The
Reference Source changes to the REF Pin input, and a
block appears to permit entry of the REF in put frequency
in MH z. A Desired Multiple block allows entr y of the ref -
erence frequency multiplying factor used to generate the
output frequency.
Exercise: Change the Ref Pin Frequency to 0.0315MHz,
and alter the Desired Multiple to 800. Change the Loop
Filter bloc k to exter nal, but le ave the val ues for C1 and R
alone.
Click on Calculate Solutions. The program takes into
account all of the current screen settings and calculates
all possible combinations of Reference, Feedback, and
Post Divider values that will generate an output frequency
from the input frequency (31.5kHz) multiplied by the de-
sired multiple of 800.
A box will appear : “No so lutio ns were foun d! Do you want
to retry calculations with the Check Loop Stability option
turned off ?” Choose Yes.
Another box will momentarily appear: “Calculating Solu-
tions: Press cancel to stop with the solutions calculated
so far.” A number in the box will increment for every
unique solution that is found. This example will create
eight u nique so lutions , which are then d isplayed in a win-
dow in the lower right portion of the program screen.
For best results, try to keep the PostDiv value multiplied
by the FbkDiv value from getting larger than 5000 while
running t he VCO as m uch abo ve 70MH z as possib le. If a
tradeoff must be made, it is better to run the VCO faster
and allo w the divi der val ues to ge t large. So lution #4 pro-
vides a PostDiv value of 800 and a Fbk Div value of 4 for
a combined value of 3200. The VCO is running at about
100MHz.
Click on Solution #4 to highlight the row, then click on
Suggest in the Loop Filter box to have the program
choose loop filter values. Suggested values for an exter-
nal loop filter are 4700pF and 47kΩ.
Now reselect the Check Loop Stability box to turn this
feature on. Clicking on Calculate Solutions regenerates
the same solutions provided earlier, only this time the
new Loop Filter values were used.
Figure 22: Line-Locked Screen
Click ing on Solution #4 high lights t he ro w, and cl ick ing on
Disp/Save Register Values provides a window with the
final values of k ey settings. A click on OK then d ispla ys a
second window containing register information per the
Register Map. If the solutions are to be saved to a file,
two form ats are availa ble: a tex t format f or viewing and a
data format for loading into the FS6131.
Clicking on Load Solution into Hardware (if enabled)
sends the inform ation in an I2C format to the FS6131 via
the parallel port. Note that this option is disabled for the
Windows NT operating system.
If your operating system can support parallel port com-
munication but the connection cable is not attached, an
error message is displayed: "The FS6131 Hardware was
not detecte d! "Mak e sure that it is c onnected to the L PT#
printer port and that it is properly connected to a +5Volt
power supply."
Table 23: Cable Interface
Color J1 DB25 Signal
Red 1 2, 13 SCL
White 2 3, 12 SDA
Green 3 8 ADDR
Blue 4 5 -
Brown 5 4 -
Black 6 25 GND
29
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
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rammable Line Lock Clock Generator I C
Pro
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rammable Line Lock Clock Generator I CPro
g
rammable Line Lock Clock Generator I C
Pro
g
rammable Line Lock Clock Generator I C
Table 24: Sample Text Output
AMI - FS6131 Solution Text File
Line-Locked / Genlock Mode
Desired Multiple = 800
Source = .0315MHz Reference Pin
External Loop Filter C1 = 47pF R = 4700Ohms
Crystal Oscillator Voltage Tune Disabled
Output Stage = CMOS
Reference Divider = 1
Feedback Divider = 800
Post Divider = 4
Charge Pump (uA) = 0
EXTLF = 1
XLVTEN = 0
XCT = 7
CMOS = 1
Register 0 = 1H (1)
Register 1 = 40H (64)
Register 2 = 2H (2)
Register 3 = 20H (32)
Register 4 = 3H (3)
Register 5 = 24H (36)
Register 6 = 0H (0)
Register 7 = 17H (23)
Figure 23: Cable Connections
1
2
3
4
5
6
J1
DB-25
2
3
8
5
4
13
12
25
PIN PIN
RED
WHT
GRN
BLU
BRN
BLK
Figure 24: Board Silkscreen
Figure 25: Board Traces - Component Side
Figure 26: Board Traces - Solder Side
30
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I CProgrammabl e Line Loc k Clock Generator I C
Programmabl e Line Loc k Clock Generator I C
11.0 Applications Information
A signal reflection will occur at any point on a PC-board
trace where impedance mismatches exist. Reflections
cause several undesirable effects in high-speed applica-
tions, such as an increase in clock jitter and a rise in
electrom agnetic emissions from the board. Using a prop-
erly designed series termination on each high-speed line
can alleviate these problems by eliminating signal reflec-
tions.
11.1 PECL Output Mode
If a PECL interface is desired, the transmission line must
be terminate d using a T hévenin , or d ual, term inati on. T he
output stage can only sink current in the PECL mode,
and the amount of sink current is set by a programming
resistor on the LOCK/IPRG pin. Source current is pro-
vided by the pull-up resistor that is part of the Thévenin
termination.
Figure 27: Thévenin Termination (PECL)
R
p1
IPRG
CLKN
CLKP
{
from
PLL
R
n1
R
p2
R
n2
R
i
LOADz
L
z
L
z
O
PECL Mode Output
V
CC
V
CC
Thévenin termination uses two resistors per transm ission
line. The parallel resistance of the termination resistors
should be sized to equal the transmission line imped-
ance, taking into account the driver sink current, the de-
sired rise and f al l t imes, and th e VIH and VIL specif icat ions
of the load.
11.1.1 Example Calculation
In PECL m ode, the output dr iver does not sour ce cur rent,
so the VIH value is determined by the ratios of the termi-
nating resistors using the equation
21
1
pp
p
CCNMH RR
R
VV +
×=
where Rp1 is the pull-up resistor, Rp2 is the pull-down re-
sistor, and VNMH is the desired noise margin, and
NMHCCIH VVV −= .
The r esistor ratio m ust als o m atc h the li ne im pedance vi a
the equation
21
21
pp
pp
LRR
RR
z+
=
where zL is the line im pedanc e.
Combining these equations, and solving for Rp1 gives
÷
÷
ø
ö
ç
ç
è
æ
−
+= NMHCC
NMH
LLp VV V
zzR 1
If the lo ad ’s VIH(min) = VCC – 0.6, choose a VNMH = 0.45V. If
the line impedance is 75Ω, then Rp1 is about 82Ω. Sub-
stituting into the equation for line impedance and solving
for Rp2 gives a value of 880Ω (choose 910Ω).
To s olve fo r the lo ad ’s VIL, an out put sink c urrent m ust be
programmed via the IPRG pin. If the desired VIH = VCC –
1.6, choose VCC – 2.0 for some extra margin. A sink cur-
rent of 25m A throu gh the 82Ω resist or generates a 2.05V
drop. The sink current is programmed via the IPRG pin,
where the ratio of IPRG current to output sink current is
1:4. An IPRG programming resistor of 750Ω at VDD = 5V
generates 6.6mA, or about 27mA output sink current.
31
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
g
rammable Line Lock Clock Generator I C
Pro
g
rammable Line Lock Clock Generator I CPro
g
rammable Line Lock Clock Generator I C
Pro
g
rammable Line Lock Clock Generator I C
11.2 CMOS Output Mode
If a CMOS int erf ace is des ire d, a tr ansm iss ion line is typi-
cally terminated using a series termination. Series termi-
nation adds no dc loadi ng to the driver , and requir es less
power than other resistive termination methods. In addi-
tion, no extra impedance exists from the signal line to a
reference voltage, such as ground.
Figure 28: Series Termination (CMOS)
R
S
z
L
z
O
DRIVER RECEIVE
LINE
As sho wn in F igure 28, th e sum of the driver’s o utput im-
pedance (zO) and the series termination resistance (RS)
must equal the line impedance (zL). That is,
OLS zzR −= .
When the source impedance (zO+RS) is matched to the
line impedance, then by voltage division the incident
wave amplitude is one-half of the full signal amplitude.
2)( )( V
zRz Rz
VV
LSO
SO
i=
++ +
=
However, the full signal amplitude may take up to twice
as long as the propagation delay of the line to develop,
reducin g nois e im m unity dur ing the ha lf- am plitude peri od.
Note that the volta ge at the rece ive end m ust add u p to a
signal amplitude that meets the receiver switching
thresholds. The slew rate of the signal may be reduced
due to the additional RC delay of the load capacitance
and the line impedance. Also, note that the output driver
impedance will vary slightly with the output logic state
(high or low).
11.3 Serial Communications
Connection of devices to a standard-mode implementa-
tion of the I2C-bus is similar to that shown in Figure 29.
Selection of the pull-up resistors (RP) and the optional
series resistors (RS) on the SDA and SCL lines depends
on the supply voltage, the bus capacitance, and the
number of connected devices with their associated input
currents.
Control of the clock and data lines is done through open
drain/collector current-sink outputs, and thus requires
external pull-up resistors on both lines.
A guideline is
bus
r
PC
t
R×
<2,
where tr is the maximum rise time (minus some margin)
and Cbus is the total bus capacitance. Assuming an I2C
controller and 8 to 10 o ther devices on the bus, including
this one, results in values in the 5kΩ to 7kΩ range. Use of
a series resistor to provide protection against high volt-
age spikes on the bus will alter the values for RP.
Figure 29: Connections to the Serial Bus
R
P
SDA
SCL
Data In
Data Out
Clock Out
TRANSMITTER
Data In
Data Out
RECEIVER
Clock In
R
P
R
S
(optional)
R
S
(optional)
R
S
(optional)
R
S
(optional)
11.3.1 For More Information
More information on the I2C-bus can be found in the
document The I2C-bus And How To Use It (Including
Specifications), available from Philips Semiconductors at
http://www-us2.semiconductors.philips.com.
32
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmable Lin e Lock Clock Generator IC
Programmable Lin e Lock Clock Generator ICProgrammable Line Lock Clock Generator IC
Programmable Lin e Lock Clock Generator IC
12.0 Device Application:
Stand-Alone Clock Generation
The length of the reference and feedback dividers, their
granular it y, and the f lexib ility of the post D ivider m ake the
FS6131 the most flexible monolithic stand-alone PLL
clock generation device available. The effective block
diagram of the FS6131 when programmed for Stand-
Alone mode is shown in Figure 30.
The source of the Feedback Divider in the Stand-Alone
mode is the output of the VCO. By dividing the input ref-
erence frequency down by Reference Divider (NR), then
multiplying it up in the Main Loop through the Feedback
Divider (NF), and finally dividing the Main Loop output
frequenc y by the Post Di vider (NPx), we have the defining
relationship for this mode. The equation for the output
clock frequency (fCLK) can be written as
÷
÷
ø
ö
ç
ç
è
æ
÷
÷
ø
ö
ç
ç
è
æ
=PxR
F
REFCLK NN
N
ff 1, (Eqn.1)
where the reference source frequency (fREF) can be either
supplied by the VCXO or applied to the REF pin.
Great flexibility is permitted in the programming of the
FS6131 to achieve exact desired output frequencies
since three integers are involved in the computation.
12.1 Example Calculation
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
Suppose that the reference source frequency is
14.318MHz and the desired output frequency is 100MHz.
First, f actor the 1 4.31 8MHz r eferenc e fr equenc y (whic h is
four times the NTSC television color sub-carrier) into
prime numbers. The exact expression is
11 753
2
81.14318181 172
5×××
==
REF
f.
Figure 30: Block Diagram: Stand-Alone Clock Generation
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0]
POST2[1:0]
POST1[1:0]
REFDIV[11:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
Feedback
Divider
(N
F
)
FBKDIV[14:0]
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
R
LF
C
LF
R
IPRG
C
LP
33
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
g
rammable Line Loc k Clock Generator IC
Pro
g
rammable Line Loc k Clock Generator ICPro
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rammable Line Loc k Clock Generator IC
Pro
g
rammable Line Loc k Clock Generator IC
Next, express the output and input frequencies as a ratio
of fCLK to fREF, where fCLK has also been converted to a
product of prime numbers.
()
÷
÷
ø
ö
ç
ç
è
æ××× ×
==
11 7532
52
81.14318181
00.100000000
1725
88
REF
CLK
f
f
Simplifying the above equation yields
()
()
73 1152
2
13
×××
=
REF
CLK
f
f. (Eqn. 2)
Deciding how to apportion the denominator integers be-
tween the Reference Divider and the Post Divider is an
iterative process. To obtain the best performance, the
VCO should be operated at the highest frequency possi-
ble without exceeding its upper limit of 230MHz. (see
Table 16). The VCO frequency (fVCO) can be calculated
by
R
F
REFVCO N
N
ff ×= .
Recall that the Reference Divider can have a value be-
tween 1 and 4096, but the Post Divider is limited to val-
ues derived from
321 PPPPx NNNN ××=
where the values NP1, NP2, and NP3 are found in Table 8.
In this ex am ple, the s m allest in teger tha t can be rem oved
from the denominator of Eqn. 2 is three. Set the Post Di-
vider at NPx=3, and the ra tio of f CLK to fREF becom es (from
Eqn. 1)
()
()
3
1
73 1152 13 ×
×××
=
REF
CLK
f
f.
Unfortunate ly, a Post Divider m odulus of three r equires a
VCO frequency of 300MHz, which is greater than the al-
lowable fVCO noted in Table 16. For the best PLL per-
form ance, program the Post Divider modulus to al low the
VCO to operate at a nominal frequency that is at least
70MHz but less then 230MHz. Therefore, the Reference
Divider c annot be r educed bel ow the m odulus of 32×7 (or
63) as shown in Eqn. 2.
However, the VCO can still be operated at a frequency
higher than fCLK. Multiplying both the numerator and the
denominator by two does not alter the output frequency,
but it does increase the VCO frequency.
()
()
2
1
63
880
2
1
73 211521
2
13 ×=×
××××
=×= PxR
F
REF
CLK NN
N
f
f
(Eqn. 3)
As Eqn. 3 shows, t he VCO frequenc y can be doubled by
multiplying the Feedback Divider by two. Set the Post
Divider to two to return the output frequency to the de-
sired m odulus. These divider settings place the VCO fre-
quency at 200MHz.
12.2 Example Programming
To generate 100.000MHz from 14.318MHz, program the
following (refer to Figure 30):
• Set the Reference Divider input to select the VCXO
via REFDSRC=0
• Set the PFD input to select the Reference Divider
and the Feedback Divider via PDREF=0 and
PDFBK=0
• Set the Reference Divider (NR) to a modulus of 63 via
REFDIV[11:0]
• Set the Feedback Divider input to select the VCO via
FBKDSRC=1
• Set the Feedback Divider (NF) to a modulus of 880
via FBKDIV[14:0]
• Set NP1=2, NP2=1, and NP3=1 for a combined Post
Divider modulus of NPx=2 via POST1[1:0],
POST2[1:0], and POST3[1:0].
• Select the internal loop filter via EXTLF=0
• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
• Set VCOSPD=0 to select the VCO high speed range
34
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmable Lin e Lock Clock Generator IC
Programmable Lin e Lock Clock Generator ICProgrammable Line Lock Clock Generator IC
Programmable Lin e Lock Clock Generator IC
13.0 Device Application:
Line-Locked Clock Generation
Line-locked clock generation, as used here, refers to the
process of synthesizing a clock frequency that is some
integer multiple of the horizontal line frequency in a
graphics system. The FS6131 is easily configured to
perform that function, as shown in Figure 31.
A line r ef erenc e s ig na l (fHSYNC) is applied to the R EF i nput
for direct application to the Main Loop PFD. The Feed-
back Divider (NF) is programmed for the desired number
of output clocks per line.
The sourc e for the Feed back Divider is s elect ed to be the
output of the Post Divider (NPx) so that the edges of the
output clock maintain a consistent phase alignment with
the line refer ence signa l. The m odulus of the P ost Di vider
should be selected to maintain a VCO frequency that is
comfortably within the operating range noted in Table 16.
13.1 Example Calculation
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
Suppose that we wish to reconstruct the pixel clock from
a VGA source. This is a typical requirement of an LCD
projection panel application.
First, establish the total number of pixel clocks desired
between hori zonta l s ync (HSYN C) pu lses. T he num ber of
pixel clocks is known as the horizontal total, and the
Feedback Divider is programmed to that value. In this
example, choose the horizontal total to be 800.
Next, establish the frequency of the HSYNC pulses
(fHSYNC) on the line r ef er ence signal f or th e v id eo mode. In
this cas e, let fHSYNC=3 1.5kHz. The out put clock frequenc y
fCLK is calculated to be: MHz175.25800kHz5.31 =×=×= FHSYNCCLK Nff
Figure 31: Block Diagram: Line-Locked Clock Generation
Reference
HSYNC
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
R
LF
C
LF
R
IPRG
C
LP
35
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
g
rammable Line Loc k Clock Generator IC
Pro
g
rammable Line Loc k Clock Generator ICPro
g
rammable Line Loc k Clock Generator IC
Pro
g
rammable Line Loc k Clock Generator IC
However, the 31.5kHz line reference signal is too low in
frequency for the internal loop filter to be used. A series
combination of a 0.015µF capacitor and a 15kΩ resistor
from power (VDD) to the EXTLF pin provides an external
loop filter. A 100pF to 220pF cap acitor in p arallel with the
combination may improve the filter performance.
For the best PLL performance, program the Post Divider
modulus to allow the VCO to operate at a nominal fre-
quenc y that is at least 70MHz but les s then 2 30MH z. T he
VCO frequency (fVCO) can be calculated by
PxFHSYNCVCO NNff ××= .
Setting the Post Divider equal to four (NPx=4) is a rea-
sonable solution, although there are a number of values
that will work. Tr y to keep 5000<× PxF NN
to avoid divider values from becoming too large. These
settings place the VCO frequency at about 100MHz.
Calculate the ideal charge pump current (Ipump) as
VCOlflf
PxFHSYNC
pump ACR
NN
kHz
f
I2
2
15 ×=
where Rlf is the external loop filter series resistor, Clf is
the external loop filter series capacitor, and AVCO is the
VCO gain. The VCO gain is either:
AVCO=125MHz/V if the High Range is selected, or
AVCO=75MHz/V if the Low Range is selected.
See Table 16 for more information on the VCO range.
With fhsync=31.5kHz, Clf=0.015µF, Rlf=15kΩ, NF=800,
NPx=4, and AVCO=125MHz/V, the charge pump current is
39.3µA. A 220pF cap across the entire loop filter is also
helpful.
13.2 Example Programming
To generate 800 pixel clocks between HSYNC pulses
occurring on the line reference signal every 31.5kHz,
program the following (refer to Figure 31):
• Clear the OSCTYPE bit to 0
• Turn off the crystal oscillator via XLROM=7
• Set the PFD inputs to select the REF pin and the
Feedback Divider via PDREF=1 and PDFBK=0
• Set the Feedback Divider input to select the Post Di-
vider via FBKDSRC=0
• Set the Feedback Divider (NF) to a modulus of 800
(the desired number of pixel clocks per line) via
FBKDIV[14:0]
• Set NP1=4, NP2=1, and NP3=1 for a combined Post
Divider modulus of NPx=4 via POST 1[1:0],
POST2[1:0], and POST3[1:0].
• Select the external loop filter via EXTLF=1
• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
• Set VCOSPD=1 to select the VCO low speed range
• Set MLCP[1:0] to 3 to select the 32µA range
The output clock frequency fCLK is 25.175MHz, with an
internal VCO frequency of 100.8MHz. Note that the
Crystal Loop was unused in this application.
36
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmable Lin e Lock Clock Generator IC
Programmable Lin e Lock Clock Generator ICProgrammable Line Lock Clock Generator IC
Programmable Lin e Lock Clock Generator IC
14.0 Device Application: Genlocking
Genlocking refers to the process of synchronizing the
horizontal sync pulses (HSYNC) of a target graphics
system to the HSYNC of a source graphics system. In a
genlocked mode, the FS6131 increases (or decreases)
the freque ncy of the V CO unt il the F BK i npu t is f r eque ncy
matched and phase-aligned to the frequency applied to
the REF input. Since the feedback divider is within the
graphic s system and the graphics system is the sourc e of
the signal applied to the FBK input of the FS6131, the
graphics system is effectively synchronized to the REF
input as shown in Figure 32.
To configure the FS6131 for genlocking, the REF input
(pin 12) and the FBK input (pin 13) are switched directly
onto the feedback input of the PFD. The Reference and
Feedback dividers are not used.
The output clock frequency is: totalhorizontalff HSYNCCLK ×=
The only remaining task is to select a Post Divider
modulus (NPx) t hat al lows the VCO f reque nc y to be wit hin
its nominal range.
14.1 Example Calculation
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
The FS6131 is being used to genlock an LCD projection
panel syst em to a VGA card-g en erate d HSYNC. T he total
number of pixel clocks generated by the VGA card,
known as the horizontal total, are 800. Therefore, the
LCD panel graphics system that is clocked by the
FS6131 is set to divide the output clock frequency (fCLK)
by 800. T he input HS YNC reference f requency (fHSYNC) is
15kHz.
Figure 32: Block Diagram: Genlocking
Video Graphics System
Sy stem HSYNC Clock In
Reference
HSYNC
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Internal
Loop
Filter
R
LF
C
LF
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
FBKDSRC[1:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
CLK
)
(f
CLK
)
(f
VCO
)
R
IPRG
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
C
LP
37
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
g
rammable Line Loc k Clock Generator IC
Pro
g
rammable Line Loc k Clock Generator ICPro
g
rammable Line Loc k Clock Generator IC
Pro
g
rammable Line Loc k Clock Generator IC
The output clock frequency is calculated as
MHz0.12800kHz15 =×=
CLK
f.
For best performance, program the Post Divider (NPx)
modulus to allow the VCO to operate at a nominal fre-
quenc y that is at least 70MHz but les s then 2 30MH z. T he
VCO frequency (fVCO) can be calculated by
PxCLKVCO Nff =.
Selecting the Post Divider m odulus of NPx=6 is a reason-
able solution, although there are a number of values that
will work. Try to keep 5000<× PxF NN
to avoid d ivider v alues f rom becom ing too large . The set-
tings place the VCO frequency at about 72MHz.
Calculate the ideal charge pump current (Ipump) as
VCOlflf
PxFHSYNC
pump ACR
NN
kHz
f
I2
2
15 ×=
where Rlf is the external loop filter series resistor, Clf is
the external loop filter series capacitor, and AVCO is the
VCO gain. The VCO gain is either
AVCO=125MHz/V if the High Range is selected, or
AVCO=75MHz/V if the Low Range is selected.
See Table 16 for more information on the VCO range.
With fhsync= 15kHz, Clf=0.015µF, Rlf=15kΩ, NF=8 00, NPx=6,
and AVCO=125MHz/V, the charge pump current is 24µA.
A 220pF cap across the entire loop filter is also helpful.
14.2 Example Programming
To generate 800 pixel clocks between HSYNC pulses
occurring on the line reference signal every 15kHz, pro-
gram the following (refer to Figure 32):
• Clear the OSCTYPE bit to 0
• Turn off the crystal oscillator via XLROM=7
• Set the PFD inputs to select the REF and FBK pins
via PDREF=1 and PDFBK=1
• Set NP1=2, NP2=3, and NP3=1 for a combined Post
Divider modulus of NPx=6 via POST1[1:0],
POST2[1:0], and POST3[1:0].
• Select the external loop filter via EXTLF=1
• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
• Set VCOSPD=1 to select the VCO low speed range
• Set MLCP[1:0] to 3 to select the 32µA range
The output clock frequency fCLK is 12MHz, with an internal
VCO frequency of 72MHz. Note that the Crystal Loop
was unused in this application.
38
FS6131-01
FS6131-01FS6131-01
FS6131-01
Programmable Lin e Lock Clock Generator IC
Programmable Lin e Lock Clock Generator ICProgrammable Line Lock Clock Generator IC
Programmable Lin e Lock Clock Generator IC
15.0 Device Application:
Telecom Clock Regenerator
The FS6131 can be used as a clock regenerator as
shown in Figure 33. This mode uses the voltage-
controlled crystal oscillator (VCXO) in its own phase-
locked loop, referred to as the Crystal Loop. The VCXO
provides a "de-jittered" multiple of the reference fre-
quency at the REF pin (usually 8kHz in telecom applica-
tions) for use by the Main Loop. In essence, the Crystal
Loop “cleans up” the reference signal for the Main Loop.
The Control ROM for the VCXO D ivider is pr eloaded with
the most common ratios to permit locking of most stan-
dard telecommunications crystals to an 8kHz signal ap-
plied to th e REF pin. The de-jittered multiple of the refer-
ence frequency from the VCXO is then supplied to the
Reference Divider in the Main Loop. The Reference Di-
vider, along with the Feedback Divider, can be pro-
grammed to achieve the desired output clock frequency.
15.1 Example Calculation
A Visual BASIC program is available to completely pro-
gram the FS6131 based on the given parameters.
In this example, an 8kH z ref erence frequency is supplied
to the FS6131 and an output clock frequency of
51.84MH z is desire d .
First, select the frequenc y at which the VCX O will opera te
from Table 10. The table shows the external crystal fre-
quency options available to choose from, since the VCXO
runs at the crystal fr eque nc y. While the M ain Lo op c an be
programmed to work with any of the frequencies in the
table, the best performance will be achieved with the
highest frequency at the Main Loop PFD.
The f requency at the Main Loo p PFD (f MLpfd) is the VCXO
frequency (fVCXO) divided by the Main Loop Reference
Divider (NR).
R
VCXO
MLpfd N
f
f=
Figure 33: Block Diagram: Telecom Clock Regenerator
8kHz IN
(typical)
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
FBKDSRC[1:0]
R
LF
C
LF
R
IPRG
C
LP
39
FS6131-01
FS6131-01FS6131-01
FS6131-01
Pro
g
rammable Line Loc k Clock Generator IC
Pro
g
rammable Line Loc k Clock Generator ICPro
g
rammable Line Loc k Clock Generator IC
Pro
g
rammable Line Loc k Clock Generator IC
The goal is to choose the highest crystal frequency from
Table 10 that generates the smallest value of NR.
The equat io n es ta bl ishin g th e o utp ut f r eque nc y (f CLK) as a
function of the input VCXO frequency is
R
F
VCXO
CLK N
N
f
f=(Eqn. 1)
where NF is the Feedback Divider modulus.
Choose a few different crystal frequencies f rom Table 10
and factor both the input VCXO and output clock fre-
quencies into prime numbers. Look for the factors that
will give the smallest modulus for NR with the largest
FVCXO. The output and VCXO frequencies and the re-
duced factors from Eqn. 1 are in Table 25.
Table 25: Clock Regenerator Example
VCXO FREQUENCY
FROM Table 10
(fVCXO, MHz) VCXO
CLK
f
f
R
F
N
N
20.00 20000000
51840000 125
324
19.44 19440000
51840000 3
8
25.248 25248000
51840000 263
540
24.576 24576000
51840000 64
135
A 19.44MH z crystal provides the sm allest m odulus f or NR
(NR=3) with the highest crystal frequency.
Finally, choose a Post Divider (NPx) modulus that keeps
the VCO frequency in its most comfortable range. The
VCO frequency (fVCO) can be calculated by
PxCLKVCO Nff =
Selecting an overall modulus of NPx=3 sets the VCO fre-
quency at 155.52MHz when the loop is locked.
15.2 Example Programming
To generate a de-jittered output frequency of 51.84MHz
from an 8kHz reference, program the following (refer to
Figure 33):
• Program the VCXO Control ROM to 3 via
XLROM[2:0] to select an external 19.44MHz crystal
• Enable the VCXO fine tune via XLVTEN=1
• Enable the Crystal Loop PFD via XLPDEN=0 and
XLSWAP=0
• Set the Reference Divider input to select the VCXO
via REFDSRC
• Set the PFD input to select the Reference Divider
and the Feedback Divider via PDREF and PDFBK
• Set the Reference Divider (NR) to a modulus of 3 via
REFDIV[11:0]
• Set the Feedback Divider input to select the VCO via
FBKDSRC
• Set the Feedback Divider (NF) to a modulus of 8 via
FBKDIV[14:0]
• Set NP1=1, NP2=3, and NP3=1 for a combined Post
Divider modulus of NPx=3 via POST1[1:0],
POST2[1:0], and POST3[1:0].
• Select the internal loop filter via EXTLF
• Set VCOSPD=0 to select the VCO high speed range
Thes e settings provide the high est frequenc y at the Main
Loop Phase Frequenc y Detector of 6.48MHz. The use of
a 19.44MHz crystal requires that XLROM[2:0] be set to
three as shown in Table 10.
