100343 Low Power 8-Bit Latch General Description Features The 100343 contains eight D-type latches, individual inputs, (Dn), outputs (Qn), a common enable pin (E), and a latch enable pin (LE). A Q output follows its D input when both E and LE are LOW. When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to E or LE going HIGH. The 100343 outputs are designed to drive a 50X termination resistor to b2.0V. All inputs have 50 kX pull-down resistors. Y Y Y Y Y Low power operation 2000V ESD protection Voltage compensated operating range e b4.2V to b 5.7V Available to industrial grade temperature range Available to MIL-STD-883 Logic Symbol Pin Names D0 -D7 E LE Q0 -Q7 NC Description Data Inputs Enable Input Latch Enable Input Data Inputs No Connect TL/F/10250 - 1 Connection Diagrams 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak TL/F/10250 - 4 TL/F/10250 - 3 TL/F/10250-2 C1995 National Semiconductor Corporation TL/F/10250 RRD-B30M105/Printed in U. S. A. 100343 Low Power 8-Bit Latch July 1992 Logic Diagram TL/F/10250 - 5 Truth Table Inputs Outputs Dn E LE Qn L H X X L L H X L L X H L H Latched* Latched* *Retains data present before either LE or E went HIGH H e HIGH voltage level L e LOW voltage level X e Dont's care 2 Absolute Maximum Ratings Recommended Operating Conditions Above which the useful life may be impared (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65 C to a 150 C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) Case Temperature (TC) Commercial Industrial Military 0 C to a 85 C b 40 C to a 85 C b 55 C to a 125 C Supply Voltage (VEE) a 175 C a 150 C b 5.7V to b 4.2V b 7.0V to a 0.5V VEE to a 0.5V b 50 mA t 2000V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e 0 C to a 85 C (Note 3) Symbol Parameter Min Typ Max Units VOH Output HIGH Voltage b 1025 b 955 b 870 mV VOL Output LOW Voltage b 1830 b 1705 b 1620 mV VOHC Output HIGH Voltage b 1035 VOLC Output LOW Voltage VIH Input HIGH Voltage VIL IIL IIH Input HIGH Current IEE Power Supply Current mV Conditions VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V Loading with 50X to b2.0V b 1610 mV VIN e VIH (Min) or VIL (Max) b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs Input LOW Voltage b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs Input LOW Current 0.50 mA VIN e VIL (Min) mA VIN e VIH (Max) 240 b 95 b 97 b 55 b 55 mA Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V Note 3: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. DIP AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol TC e 0 C Parameter TC e a 25 C TC e a 85 C Min Max Min Max Min Max Units Conditions tPLH tPHL Propagation Delay Dn to Output 0.80 2.00 0.80 2.00 0.80 2.20 ns Figures 1, 2, 3 (Note 1) tPLH tPHL Propagation Delay LE, E to Output 1.40 2.90 1.40 2.90 1.60 3.10 ns Figures 1, 2, 3 (Note 1) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 3 ts Setup Time th Hold Time tpw(H) D0 - D7 1.0 1.0 1.1 ns Figures 1, 4 D0 - D7 0.1 0.1 0.1 ns Figures 1, 4 LE, E 2.00 2.00 2.00 ns Figures 1, 4 Pulse Width HIGH Note 1: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 3 Commercial Version (Continued) PCC and Cerpack AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol TC e 0 C Parameter TC e a 25 C TC e a 85 C Min Max Min Max Min Max Units Conditions tPLH tPHL Propagation Delay Dn to Output 0.80 1.80 0.80 1.80 0.80 2.00 ns Figures 1, 2, 3 (Note 2) tPLH tPHL Propagation Delay LE, E to Output 1.40 2.70 1.40 2.70 1.60 2.90 ns Figures 1, 2, 3 (Note 2) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 3 ts Setup Time th Hold Time tpw(H) Pulse Width HIGH tOSHL Maximum Skew Common Edge Output-to-Output Variation Data to Output Path 340 340 Maximum Skew Common Edge Output-to-Output Variation Data to Output Path 440 Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path Maximum Skew Pin (Signal) Transition Variation Data to Output Path tOSLH tOST tPS D0 - D7 0.90 0.90 1.00 ns Figures 1, 4 D0 - D7 0.0 0.0 0.0 ns Figures 1, 4 LE, E 2.00 2.00 2.00 ns Figures 1, 4 340 ps PCC Only (Note 1) 440 440 ps PCC Only (Note 1) 480 480 480 ps PCC Only (Note 1) 300 300 300 ps PCC Only (Note 1) Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. Note 2: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 4 Industrial Version PCC DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b40 C to a 85 C (Note 3) Symbol Parameter TC e b40 C Min TC e 0 C to a 85 C Max Min Units Conditions Max VOH Output HIGH Voltage b 1085 b 870 b 1025 b 870 mV VOL Output LOW Voltage b 1830 b 1575 b 1830 b 1620 mV VOHC Output HIGH Voltage b 1095 VOLC Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current IEE Power Supply Current b 1035 b 1565 mV b 1610 mV VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V VIN e VIH (Min) or VIL (Max) Loading with 50X to b2.0V b 1170 b 870 b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs b 1830 b 1480 b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs mA VIN e VIL (Min) 240 mA VIN e VIH (Max) b 55 b 55 mA 0.50 0.50 240 b 95 b 97 b 50 b 50 b 95 b 97 Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V Note 3: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. PCC AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b40 C TC e a 25 C TC e a 85 C Min Max Min Max Min Max Units tPLH tPHL Propagation Delay Dn to Output 0.80 1.80 0.80 1.80 0.80 2.00 ns Figures 1, 2, 3 (Note 1) tPLH tPHL Propagation Delay LE, E to Output 1.40 2.70 1.40 2.70 1.60 2.90 ns Figures 1, 2, 3 (Note 1) tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.40 2.50 0.45 1.90 0.45 1.90 ns ts Setup Time th Hold Time tpw(H) Figures 1, 3 D0 - D7 0.60 0.90 1.00 ns Figures 1, 4 D0 - D7 0.8 0.0 0.0 ns Figures 1,4 LE, E 2.40 2.00 2.00 ns Figures 1, 4 Pulse Width HIGH Note 1: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 5 Military Version DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b55 C to a 125 C Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage VOHC Output HIGH Voltage VOLC Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IEE Power Supply Current IIH Input HIGH Current Max Units TC b 1025 b 870 mV 0 C to a 125 C b 1085 b 870 mV b 55 C b 1830 b 1620 mV 0 C to a 125 C b 1830 b 1555 mV b 55 C Conditions Notes VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V 1, 2, 3 VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V 1, 2, 3 0 C to b 1035 mV b 1085 mV b 55 C b 1610 mV 0 C to a 125 C b 1555 mV b 55 C b 1165 b 870 mV b 55 C to a 125 C Guaranteed HIGH Signal for All Inputs b 1830 b 1475 mV b 55 C to a 125 C Guaranteed LOW Signal for All Inputs mA b 55 C to a 125 C VEE e b4.2V VIN e VIL (Min) 1, 2, 3 b 35 b 35 mA mA b 55 to a 125 C VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V 1, 2, 3 240 mA 340 mA b 55 C mA b 55 C to a 125 C Output LOW Voltage VIH IEE Min 0.50 b 100 b 105 a 125 C 0 C to a 125 C Power Supply Current b 100 b 105 b 35 b 35 VEE e b5.7V VIN e VIH (Max) Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at b 55 C, a 25 C, and a 125 C, Subgroups 1, 2, 3, 7, and 8. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b 55 C, a 25 C, and a 125 C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing VOH/VOL. 6 Military Version (Continued) AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b55 C TC e a 25 C TC e a 125 C Min Max Min Max Min Max Units Conditions Notes tPLH tPHL Propagation Delay Dn to Output 0.50 2.70 0.50 2.30 0.50 2.80 ns Figures 1, 2, 3 1, 2, 3, 5 tPLH tPHL Propagation Delay LE, E to Output 0.90 3.40 1.0 3.10 1.10 3.90 ns Figures 1, 2, 3 1, 2, 3, 5 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.40 2.50 0.40 2.40 0.40 2.70 ns Figures 1, 3 4 ts Setup Time th Hold Time tpw(H) Pulse Width HIGH D0 - D7 0.60 0.60 0.60 ns Figures 1, 4 4 D0 - D7 1.50 1.50 1.70 ns Figures 1, 4 4 LE, E 2.40 2.40 2.40 ns Figures 1, 4 4 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at a 25 C temperature only, Subgroup A9. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at a 25 C, Subgroup A9, and at a 125 C and b 55 C temperatures, Subgroups A10 and A11. Note 4: Not tested at a 25 C, a 125 C, and b 55 C temperature (design characterization data). Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 7 Test Circuitry TL/F/10250 - 6 FIGURE 1. AC Test Circuit Notes: VCC, VCCA e a 2V, VEE e b 2.5V L1 and L2 e equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0.1 mF from GND to VCC and VEE All unused outputs are loaded with 50X to GND CL e Fixture and stray capacitance s 3 pF Switching Waveforms TL/F/10250 - 7 FIGURE 2. Propagation Delays TL/F/10250-8 TL/F/10250 - 9 FIGURE 3. Propagation and Transition Times FIGURE 4. Setup, Hold and Pulse Width Times 8 Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100343 D Device Type (Basic) C QB Special Variation QB e Military grade device with environmental and burn-in processing Package Code D e Ceramic DIP F e Quad Cerpak P e Plastic DIP Q e Plastic Leaded Chip Carrier (PCC) Temperature Range C e Commercial (0 C to a 85 C) I e Industrial (b40 C to a 85 C) (PCC Only) M e Military (b55 C to a 125 C) 9 Physical Dimensions inches (millimeters) 24-Pin Ceramic Dual-In-Line Package (D) NS Package Number J24E 10 Physical Dimensions inches (millimeters) (Continued) 24-Lead Plastic Dual-In-Line Package (P) NS Package Number N24E 28-Pin Plastic Leaded Chip Carrier (Q) NS Package Number V28A 11 100343 Low Power 8-Bit Latch Physical Dimensions inches (millimeters) (Continued) Lit. Y114916 24-Lead Quad Cerpak (F) NS Package Number W24B LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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