100343FC - National Semiconductor

TL/F/10250

100343 Low Power 8-Bit Latch

July 1992

100343

Low Power 8-Bit Latch

General Description

The 100343 contains eight D-type latches, individual inputs,

(Dn), outputs (Qn), a common enable pin (E), and a latch

enable pin (LE). A Q output follows its D input when both E

and LE are LOW. When either E or LE (or both) are HIGH, a

latch stores the last valid data present on its D input prior to

Eor LE going HIGH.

The 100343 outputs are designed to drive a 50Xtermina-

tion resistor to b2.0V. All inputs have 50 kXpull-down re-

sistors.

Features

YLow power operation

Y2000V ESD protection

YVoltage compensated operating range eb

4.2V to

b5.7V

YAvailable to industrial grade temperature range

YAvailable to MIL-STD-883

Logic Symbol

TL/F/10250– 1

Pin Names Description

D0–D7Data Inputs

EEnable Input

LE Latch Enable Input

Q0–Q7Data Inputs

NC No Connect

Connection Diagrams

24-Pin DIP

TL/F/10250– 2

28-Pin PCC

TL/F/10250– 4

24-Pin Quad Cerpak

TL/F/10250– 3

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Logic Diagram

TL/F/10250– 5

Truth Table

Inputs Outputs

DnE LE Qn

LLL L

HLL H

X H X Latched*

X X H Latched*

*Retains data present before either LE or E went HIGH

HeHIGH voltage level

LeLOW voltage level

XeDont’s care

Absolute Maximum Ratings

Above which the useful life may be impared (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature (TSTG)b65§Ctoa

150§C

Maximum Junction Temperature (TJ)

Ceramic a175§C

Plastic a150§C

VEE Pin Potential to Ground Pin b7.0V to a0.5V

Input Voltage (DC) VEE to a0.5V

Output Current (DC Output HIGH) b50 mA

ESD (Note 2) t2000V

Note 1: Absolute maximum ratings are those values beyond which the de-

vice may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Recommended Operating

Conditions

Case Temperature (TC)

Commercial 0§Ctoa

85§C

Industrial b40§Ctoa

85§C

Military b55§Ctoa

125§C

Supply Voltage (VEE)b5.7V to b4.2V

Commercial Version

DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCe0§Ctoa

85§C (Note 3)

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage b1025 b955 b870 mV

or VIL (Min)

VIN eVIH (Max)

50Xto b2.0V

Loading with

VOL Output LOW Voltage b1830 b1705 b1620 mV

VOHC Output HIGH Voltage b1035 mV VIN eVIH (Min) Loading with

VOLC Output LOW Voltage b1610 mV or VIL (Max) 50Xto b2.0V

VIH Input HIGH Voltage b1165 b870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW Voltage b1830 b1475 mV Guaranteed LOW Signal for All Inputs

IIL Input LOW Current 0.50 mAV

IN eVIL (Min)

IIH Input HIGH Current 240 mAV

IN eVIH (Max)

IEE Power Supply Current Inputs Open

b95 b55 mA VEE eb

4.2V to b4.8V

b97 b55 VEE eb

4.2V to b5.7V

Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

DIP AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.80 2.00 0.80 2.00 0.80 2.20 ns

Figures 1, 2, 3

tPHL Dnto Output (Note 1)

tPLH Propagation Delay 1.40 2.90 1.40 2.90 1.60 3.10 ns

Figures 1, 2, 3

tPHL LE,Eto Output (Note 1)

tTLH Transition Time 0.45 2.00 0.45 2.00 0.45 2.00 ns

Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tsSetup Time

D0–D71.0 1.0 1.1 ns

Figures 1, 4

thHold Time

D0–D70.1 0.1 0.1 ns

Figures 1, 4

tpw(H) Pulse Width HIGH

LE,E 2.00 2.00 2.00 ns

Figures 1, 4

Note 1: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Commercial Version (Continued)

PCC and Cerpack AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.80 1.80 0.80 1.80 0.80 2.00 ns

Figures 1, 2, 3

tPHL Dnto Output (Note 2)

tPLH Propagation Delay 1.40 2.70 1.40 2.70 1.60 2.90 ns

Figures 1, 2, 3

tPHL LE,Eto Output (Note 2)

tTLH Transition Time 0.45 1.90 0.45 1.90 0.45 1.90 ns

Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tsSetup Time

D0–D70.90 0.90 1.00 ns

Figures 1, 4

thHold Time

D0–D70.0 0.0 0.0 ns

Figures 1, 4

tpw(H) Pulse Width HIGH

LE,E 2.00 2.00 2.00 ns

Figures 1, 4

tOSHL Maximum Skew Common Edge PCC Only

Output-to-Output Variation 340 340 340 ps (Note 1)

Data to Output Path

tOSLH Maximum Skew Common Edge PCC Only

Output-to-Output Variation 440 440 440 ps (Note 1)

Data to Output Path

tOST Maximum Skew Opposite Edge PCC Only

Output-to-Output Variation 480 480 480 ps (Note 1)

Data to Output Path

tPS Maximum Skew PCC Only

Pin (Signal) Transition Variation 300 300 300 ps (Note 1)

Data to Output Path

Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged

device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both

HL and LH (tOST). Parameters tOST and tPS guaranteed by design.

Note 2: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Industrial Version

PCC DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

40§Ctoa

85§C (Note 3)

Symbol Parameter TCeb

40§CT

Ctoa

85§CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage b1085 b870 b1025 b870 mV VIN eVIH (Max) Loading with

VOL Output LOW Voltage b1830 b1575 b1830 b1620 mV or VIL (Min) 50Xto b2.0V

VOHC Output HIGH Voltage b1095 b1035 mV VIN eVIH (Min) Loading with

VOLC Output LOW Voltage b1565 b1610 mV or VIL (Max) 50Xto b2.0V

VIH Input HIGH Voltage b1170 b870 b1165 b870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW Voltage b1830 b1480 b1830 b1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.50 0.50 mAV

IN eVIL (Min)

IIH Input HIGH Current 240 240 mAV

IN eVIH (Max)

IEE Power Supply Current Inputs Open

b95 b50 b95 b55 mA VEE eb

4.2V to b4.8V

b97 b50 b97 b55 VEE eb

4.2V to b5.7V

Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

PCC AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCeb

40§CT

25§CT

85§CUnits

Min Max Min Max Min Max

tPLH Propagation Delay 0.80 1.80 0.80 1.80 0.80 2.00 ns

Figures 1, 2, 3

tPHL Dnto Output (Note 1)

tPLH Propagation Delay 1.40 2.70 1.40 2.70 1.60 2.90 ns

Figures 1, 2, 3

tPHL LE,Eto Output (Note 1)

tTLH Transition Time 0.40 2.50 0.45 1.90 0.45 1.90 ns

Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tsSetup Time

D0–D70.60 0.90 1.00 ns

Figures 1, 4

thHold Time

D0–D70.8 0.0 0.0 ns

Figures 1,4

tpw(H) Pulse Width HIGH

LE,E 2.40 2.00 2.00 ns

Figures 1, 4

Note 1: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Military Version

DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

55§Ctoa

125§C

Symbol Parameter Min Max Units TCConditions Notes

VOH Output HIGH Voltage b1025 b870 mV 0§Cto

IN eVIH (Max)

or VIL (Min) 50Xto b2.0V

Loading with 1, 2, 3

a125§C

b1085 b870 mV b55§C

VOL Output LOW Voltage b1830 b1620 mV 0§Cto

125§C

b1830 b1555 mV b55§C

VOHC Output HIGH Voltage b1035 mV 0§Cto

or VIL (Min)

VIN eVIH (Max)

50Xto b2.0V

Loading with 1, 2, 3

a125§C

b1085 mV b55§C

VOLC Output LOW Voltage b1610 mV 0§Cto

125§C

b1555 mV b55§C

VIH Input HIGH Voltage b1165 b870 mV b55§C to Guaranteed HIGH Signal for All Inputs 1, 2, 3, 4

a125§C

VIL Input LOW Voltage b1830 b1475 mV b55§C to Guaranteed LOW Signal for All Inputs 1, 2, 3, 4

a125§C

IIL Input LOW Current 0.50 mAb55§Cto V

EE eb

4.2V 1, 2, 3

a125§CV

IN eVIL (Min)

IEE Power Supply Current b100 b35 mA b55 to VEE eb

4.2V to b4.8V 1, 2, 3

b105 b35 mA a125§CV

EE eb

4.2V to b5.7V

IIH Input HIGH Current 240 mA0§Cto

IN eVIH (Max)

VEE eb

5.7V 1, 2, 3

a125§C

340 mAb55§C

IEE Power Supply Current b55§Cto Inputs Open

b100 b35 mA a125§CVEE eb

4.2V to b4.8V 1, 2, 3

b105 b35 VEE eb

4.2V to b5.7V

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be

considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at b55§C, a25§C, and a125§C, Subgroups 1, 2, 3, 7, and 8.

Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b55§C, a25§C, and a125§C, Subgroups A1, 2, 3, 7, and 8.

Note 4: Guaranteed by applying specified input condition and testing VOH/VOL.

Military Version (Continued)

AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCeb

55§CT

25§CT

125§CUnits Conditions Notes

Min Max Min Max Min Max

tPLH Propagation Delay 0.50 2.70 0.50 2.30 0.50 2.80 ns

Figures 1, 2, 3

1, 2, 3, 5

tPHL Dnto Output

tPLH Propagation Delay 0.90 3.40 1.0 3.10 1.10 3.90 ns

Figures 1, 2, 3

1, 2, 3, 5

tPHL LE,Eto Output

tTLH Transition Time 0.40 2.50 0.40 2.40 0.40 2.70 ns

Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tsSetup Time

D0–D70.60 0.60 0.60 ns

Figures 1, 4

thHold Time

D0–D71.50 1.50 1.70 ns

Figures 1, 4

tpw(H) Pulse Width HIGH

LE,E 2.40 2.40 2.40 ns

Figures 1, 4

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately after power-up. This provides ‘‘cold start’’ specs which can be considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at a25§C temperature only, Subgroup A9.

Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at a25§C, Subgroup A9, and at a125§C and b55§C temperatures, Subgroups A10 and

A11.

Note 4: Not tested at a25§C, a125§C, and b55§C temperature (design characterization data).

Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

Test Circuitry

TL/F/10250– 6

Notes: FIGURE 1. AC Test Circuit

VCC,V

CCA ea

2V, VEE eb

2.5V

L1 and L2 eequal length 50Ximpedance lines

RTe50Xterminator internal to scope

Decoupling 0.1 mF from GND to VCC and VEE

All unused outputs are loaded with 50Xto GND

CLeFixture and stray capacitance s3pF

Switching Waveforms

TL/F/10250– 7

FIGURE 2. Propagation Delays

TL/F/10250– 8

FIGURE 3. Propagation and Transition Times TL/F/10250– 9

FIGURE 4. Setup, Hold and Pulse Width Times

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are

defined as follows:

100343 D C QB

Device Type (Basic) Special Variation

QB eMilitary grade device with

Package Code environmental and burn-in

DeCeramic DIP processing

FeQuad Cerpak

PePlastic DIP Temperature Range

QePlastic Leaded Chip Carrier (PCC) C eCommercial (0§Ctoa

85§C)

IeIndustrial (b40§Ctoa

85§C)

(PCC Only)

MeMilitary (b55§Ctoa

125§C)

Physical Dimensions inches (millimeters)

24-Pin Ceramic Dual-In-Line Package (D)

NS Package Number J24E

Physical Dimensions inches (millimeters) (Continued)

24-Lead Plastic Dual-In-Line Package (P)

NS Package Number N24E

28-Pin Plastic Leaded Chip Carrier (Q)

NS Package Number V28A

100343 Low Power 8-Bit Latch

Physical Dimensions inches (millimeters) (Continued) Lit. Ý114916

24-Lead Quad Cerpak (F)

NS Package Number W24B

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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