Order this document
by MC68332TS/D Rev. 2
© MOTOROLA INC., 1993, 1996
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MC68332
Technical Summar y
32-Bit Modular Microcontroller
1 Introduction
The MC68332, a highly-integrated 32-bit microcontroller, combines high-performance data manipula-
tion capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that
interface through a common intermodule bus (IMB). Standardization facilitates rapid development of
devices tailored for specific applications.
The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a time processor unit
(TPU), a queued serial module (QSM), and a 2-Kbyte static RAM module with TPU emulation capability
(TPURAM).
The MCU can either synthesize an internal clock signal from an external reference or use an external
clock input directly. Operation with a 32.768-kHz reference frequency is standard. The maximum sys-
tem clock speed is 20.97 MHz. System hardware and software allow changes in clock rate during op-
eration. Because MCU operation is fully static, register and memory contents are not affected by clock
rate changes.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The
CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this
capability.
MOTOROLA MC68332
2 MC68332TS/D
Table 1 Ordering Information
Package Type TPU Type Temperature Frequency
(MHz) Package
Order
Quantity
Order Number
132-Pin PQFP Motion Control –40 to +85
°
C 16 MHz 2 pc tray SPAKMC332GCFC16
36 pc tray MC68332GCFC16
20 MHz 2 pc tray SPAKMC332GCFC20
36 pc tray MC68332GCFC20
–40 to +105
°
C 16 MHz 2 pc tray SPAKMC332GVFC16
36 pc tray MC68332GVFC16
20 MHz 2 pc tray SPAKMC332GVFC20
36 pc tray MC68332GVFC20
–40 to +125
°
C 16 MHz 2 pc tray SPAKMC332GMFC16
36 pc tray MC68332GMFC16
20 MHz 2 pc tray SPAKMC332GMFC20
36 pc tray MC68332GMFC20
Standard –40 to +85
°
C 16 MHz 2 pc tray SPAKMC332CFC16
36 pc tray MC68332CFC16
20 MHz 2 pc tray SPAKMC332CFC20
36 pc tray MC68332CFC20
–40 to +105
°
C 16 MHz 2 pc tray SPAKMC332VFC16
36 pc tray MC68332VFC16
20 MHz 2 pc tray SPAKMC332VFC20
36 pc tray MC68332VFC20
–40 to +125
°
C 16 MHz 2 pc tray SPAKMC332MFC16
36 pc tray MC68332MFC16
20 MHz 2 pc tray SPAKMC332MFC20
36 pc tray MC68332MFC20
Std w/enhanced
PPWA –40 to +85
°
C 16 MHz 2 pc tray SPAKMC332ACFC16
36 pc tray MC68332ACFC16
20 MHz 2 pc tray SPAKMC332ACFC20
36 pc tray MC68332ACFC20
–40 to +105
°
C 16 MHz 2 pc tray SPAKMC332AVFC16
36 pc tray MC68332AVFC16
20 MHz 2 pc tray SPAKMC332AVFC20
36 pc tray MC68332AVFC20
–40 to +125
°
C 16 MHz 2 pc tray SPAKMC332AMFC16
36 pc tray MC68332AMFC16
20 MHz 2 pc tray SPAKMC332AMFC20
36 pc tray MC68332AMFC20
MC68332 MOTOROLA
MC68332TS/D 3
144-Pin QFP Motion Control –40 to +85
°
C 16 MHz 2 pc tray SPAKMC332GCFV16
44 pc tray MC68332GCFVV16
20 MHz 2 pc tray SPAKMC332GCFV20
44 pc tray MC68332GCFV20
–40 to +105
°
C 16 MHz 2 pc tray SPAKMC332GVFV16
44 pc tray MC68332GVFV16
20 MHz 2 pc tray SPAKMC332GVFV20
44 pc tray MC68332GVFV20
–40 to +125
°
C 16 MHz 2 pc tray SPAKMC332GMFV16
44 pc tray MC68332GMFV16
20 MHz 2 pc tray SPAKMC332GMFV20
44 pc tray MC68332GMFVV20
Standard –40 to +85
°
C 16 MHz 2 pc tray SPAKMC332CFV16
44 pc tray MC68332CFV16
20 MHz 2 pc tray SPAKMC332CFVV20
44 pc tray MC68332CFV20
–40 to +105
°
C 16 MHz 2 pc tray SPAKMC332VFV16
44 pc tray MC68332VFV16
20 MHz 2 pc tray SPAKMC332VFV20
44 pc tray MC68332VFV20
–40 to +125
°
C 16 MHz 2 pc tray SPAKMC332MFV16
44 pc tray MC68332MFV16
20 MHz 2 pc tray SPAKMC332MFV20
44 pc tray MC68332MFV20
Std w/enhanced
PPWA –40 to +85
°
C 16 MHz 2 pc tray SPAKMC332ACFV16
44 pc tray MC68332ACFV16
20 MHz 2 pc tray SPAKMC332ACFV20
44 pc tray MC68332ACFV20
–40 to +105
°
C 16 MHz 2 pc tray SPAKMC332AVFV16
44 pc tray MC68332AVFV16
20 MHz 2 pc tray SPAKMC332AVFC20
44 pc tray MC68332AVFV20
–40 to +125
°
C 16 MHz 2 pc tray SPAKMC332AMFV16
44 pc tray MC68332AMFV16
20 MHz 2 pc tray SPAKMC332AMFV20
44 pc tray MC68332AMFV20
Table 1 Ordering Information (Continued)
Package Type TPU Type Temperature Frequency
(MHz) Package
Order
Quantity
Order Number
Section Page
TABLE OF CONTENTS
MOTOROLA MC68332
4 MC68332TS/D
1 Introduction
1
1.1 Features ......................................................................................................................................5
1.2 Block Diagram .............................................................................................................................6
1.3 Pin Assignments ..........................................................................................................................7
1.4 Address Map ...............................................................................................................................9
1.5 Intermodule Bus ..........................................................................................................................9
2 Signal Descriptions
10
2.1 Pin Characteristics ....................................................................................................................10
2.2 MCU Power Connections ..........................................................................................................11
2.3 MCU Driver Types .....................................................................................................................11
2.4 Signal Characteristics ................................................................................................................12
2.5 Signal Function ..........................................................................................................................13
3 System Integration Module
15
3.1 Overview ...................................................................................................................................15
3.2 System Configuration and Protection ........................................................................................17
3.3 System Clock ............................................................................................................................23
3.4 External Bus Interface ...............................................................................................................26
3.5 Chip Selects ..............................................................................................................................29
3.6 General-Purpose Input/Output ..................................................................................................36
3.7 Resets .......................................................................................................................................38
3.8 Interrupts ...................................................................................................................................41
3.9 Factory Test Block .....................................................................................................................43
4 Central Processor Unit
44
4.1 Overview ...................................................................................................................................44
4.2 Programming Model ..................................................................................................................44
4.3 Status Register ..........................................................................................................................46
4.4 Data Types ................................................................................................................................46
4.5 Addressing Modes .....................................................................................................................46
4.6 Instruction Set Summary ...........................................................................................................47
4.7 Background Debugging Mode ...................................................................................................51
5 Time Processor Unit
52
5.1 MC68332 and MC68332A Time Functions ...............................................................................52
5.2 MC68332G Time Functions ......................................................................................................55
5.3 Programmer's Model .................................................................................................................57
5.4 Parameter RAM .........................................................................................................................58
5.5 TPU Registers ...........................................................................................................................58
6 Queued Serial Module
64
6.1 Overview ...................................................................................................................................64
6.2 Address Map .............................................................................................................................65
6.3 Pin Function ..............................................................................................................................66
6.4 QSM Registers ..........................................................................................................................66
6.5 QSPI Submodule .......................................................................................................................71
6.6 SCI Submodule .........................................................................................................................79
7 Standby RAM with TPU Emulation RAM
84
7.1 Overview ...................................................................................................................................84
7.2 TPURAM Register Block ...........................................................................................................84
7.3 TPURAM Registers ...................................................................................................................84
7.4 TPURAM Operation ..................................................................................................................85
8 Summary of Changes
86
MC68332 MOTOROLA
MC68332TS/D 5
1.1 Features
• Central Processing Unit (CPU32)
— 32-Bit Architecture
— Virtual Memory Implementation
— Table Lookup and Interpolate Instruction
— Improved Exception Handling for Controller Applications
— High-Level Language Support
— Background Debugging Mode
— Fully Static Operation
• System Integration Module (SIM)
— External Bus Support
— Programmable Chip-Select Outputs
— System Protection Logic
— Watchdog Timer, Clock Monitor, and Bus Monitor
— Two 8-Bit Dual Function Input/Output Ports
— One 7-Bit Dual Function Output Port
— Phase-Locked Loop (PLL) Clock System
• Time Processor Unit (TPU)
— Dedicated Microengine Operating Independently of CPU32
— 16 Independent, Programmable Channels and Pins
— Any Channel can Perform any Time Function
— Two Timer Count Registers with Programmable Prescalers
— Selectable Channel Priority Levels
• Queued Serial Module (QSM)
— Enhanced Serial Communication Interface
— Queued Serial Peripheral Interface
— One 8-Bit Dual Function Port
• Static RAM Module with TPU Emulation Capability (TPURAM)
— 2-Kbytes of Static RAM
— May be Used as Normal RAM or TPU Microcode Emulation RAM
MOTOROLA MC68332
6 MC68332TS/D
1.2 Block Diagram
Figure 1 MCU Block Diagram
332 BLOCK
QS5/PCS2
PQS7/TXD
PQS4/PCS1
PQS6/PCS3
CPU 32
QSM
IMB
TPU
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PORT QS
TXD
PCS2
SCK
MISO
MOSI
CONTROL
PCS1
PQS3/PCS0/SS PCS0/SS
RXD
PCS3
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
DSI
DSO
IPIPE
IFETCH
BKPT
IRQ[7:1]
ADDR[23:0]
CONTROL
PORT F PORT C
FC2
FC1
FC0
BG
BR
BGACK
MODCLK
ADDR[23:19]
CLOCK
EBI
CS[10:0]
BR/CS0
BG/CS1
BGACK/CS2
R/W
RESET
HALT
BERR
CLKOUT
XTAL
EXTAL
CHIP
SELECTS CSBOOT
ADDR[18:0]
DATA[15:0]DATA[15:0]
QUOT
TEST
FREEZE/QUOT
TSC
CONTROL
TSC
PC0/FC0/CS3
PC1/FC1/CS4
PC2/FC2/CS5
PC3/ADDR19/CS6
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
ADDR23/CS10
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CONTROL
PORT E
SIZ1 PE7/SIZ1
SIZ0 PE6/SIZ0
DSACK0 PE0/DSACK0
DSACK1 PE1/DSACK1
AVEC PE2/AVEC
PE3/RMC
DS PE5/DS
RMC PE4/AS
T2CLK T2CLK
TPUCH[15:0] TPUCH[15:0]
XFC
VDDSYN
2 KBYTES
RAM
VSTBY
CONTROL
AS
CONTROL
DSCLK
FREEZE
MC68332 MOTOROLA
MC68332TS/D 7
1.3 Pin Assignments
Figure 2 MC68332 132-Pin QFP Pin Assignments
332 132-PIN QFP
MC68332
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
VDD
VSS
VDD
PE1/DSACK1
PE0/DSACK0
PE2/AVEC
PE3/RMC
PE5/DS
CSBOOT
BGACK/CS2
BG/CS1
BR/CS0
VSTBY
51 17
117
16
15
14
13
12
11
10
9
8
7
6
5
4
3
131
130
129
128
127
126
125
124
123
122
121
120
119
118
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
PQS7/TXD
RXD
IPIPE/DSO
FREEZE/QUOT
XTAL
EXTAL
XFC
CLKOUT
PF0/MODCLK
PE7/SIZ1
PE6/SIZ0
TPUCH0
TPUCH1
TPUCH2
TPUCH3
TPUCH4
TPUCH5
TPUCH6
TPUCH7
TPUCH8
TPUCH9
TPUCH10
TPUCH11
TPUCH13
TPUCH14
TPUCH15
T2CLK
TPUCH12
VSS
VDD
VSS
PC0/FC0/CS3
PC1/FC1/CS4
PC2/FC2/CS5
PC3/ADDR19/CS6
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
ADDR23/CS10
AS
R/W
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
HALT
RESET
TSC
BKPT/DSCLK
IFETCH/DSI
2
1
132
VDDSYN
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VDD
VSS
VDD
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
MOTOROLA MC68332
8 MC68332TS/D
Figure 3 MC68332 144-Pin QFP Pin Assignments
332 144-PIN QFP
VSS
NC
FC0/CS3
FC1/CS4
FC2/CS5
ADDR19/CS6
ADDR20/CS7
ADDR21/CS8
ADDR22/CS9
ADDR23/CS10
VDD
T2CLK
TPUCH15
TPUCH14
TPUCH13
TPUCH12
NC
TPUCH11
TPUCH10
TPUCH9
TPUCH8
VDDE
VSSE
TPUCH7
TPUCH6
TPUCH5
TPUCH4
MC68332
NC
PE4/AS
PE6/SIZ0
PE7/SIZ1
R/W
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
HALT
RESET
CLKOUT
NC
XFC
EXTAL
VDD
XTAL
FREEZE/QUOT
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
RXD
PQS7/TXD
VSS
NC
TPUCH3
TPUCH2
TPUCH1
TPUCH0
NC
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
107
108
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
31
32
33
34
35
36
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
NC
DATA8
NC
DATA9
DATA10
NC
DATA11
VSS
DATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE5/DS
VDD
VSTBY
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
VDD
VSS
ADDR9
ADDR10
ADDR11
ADDR12
NC
NC
ADDR13
ADDR14
ADDR15
NC
ADDR16
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
143
144
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
37
65
68
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
66
67
69
70
71
72
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VSS
VDD
MC68332 MOTOROLA
MC68332TS/D 9
1.4 Address Map
The following figure is a map of the MCU internal addresses. The RAM array is positioned by the base
address registers in the associated RAM control block. Unimplemented blocks are mapped externally.
Figure 4 MCU Address Map
1.5 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of
modular microcontrollers. It contains circuitry to support exception processing, address space partition-
ing, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communi-
cate with one another and with external components through the IMB. The IMB in the MCU uses 24
address and 16 data lines.
332 ADDRESS MAP
SIM
RESERVED
QSM
$YFFC00
$YFFB40
$YFF000
2-KBYTE
TPURAM ARRAY
$YFFA00
TPURAM CONTROL
$YFFB00
RESERVED
$YFFA80
TPU
$YFFFFF
$YFFE00
MOTOROLA MC68332
10 MC68332TS/D
2 Signal Descriptions
2.1 Pin Characteristics
The following table shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All
inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin
function. Refer to the table, MCU Driver Types, for a description of output drivers. An entry in the dis-
crete I/O column of the MCU Pin Characteristics table indicates that a pin has an alternate I/O function.
The port designation is given when it applies. Refer to the MCU Block Diagram for information about
port organization.
Table 2 MCU Pin Characteristic
Pin
Mnemonic Output
Driver Input
Synchronized Input
Hysteresis Discrete
I/O Port
Designation
ADDR23/CS10/ECLK A Y N O —
ADDR[22:19]/CS[9:6] A Y N O PC[6:3]
ADDR[18:0] A Y N — —
AS B Y N I/O PE5
AVEC B Y N I/O PE2
BERR BY N — —
BG/CS1 B — — — —
BGACK/CS2 B Y N — —
BKPT/DSCLK — Y Y — —
BR/CS0 BY N ——
CLKOUT A — — — —
CSBOOT B — — — —
DATA[15:0]
1
Aw Y N — —
DS B Y N I/O PE4
DSACK1 B Y N I/O PE1
DSACK0 B Y N I/O PE0
DSI/IFETCH AY Y ——
DSO/IPIPE A— — ——
EXTAL
2
— — Special — —
FC[2:0]/CS[5:3] A Y N O PC[2:0]
FREEZE/QUOT A — — — —
HALT Bo Y N — —
IRQ[7:1] B Y Y I/O PF[7:1]
MISO Bo Y Y I/O PQS0
MODCLK
1
B Y N I/O PF0
MOSI Bo Y Y I/O PQS1
PCS0/SS Bo Y Y I/O PQS3
PCS[3:1] Bo Y Y I/O PQS[6:4]
R/W AY N — —
RESET Bo Y Y — —
RMC B Y N I/O PE3
RXD — N N — —
SCK Bo Y Y I/O PQS2
SIZ[1:0] B Y N I/O PE[7:6]
MC68332 MOTOROLA
MC68332TS/D 11
NOTES:
1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin.
2. EXTAL, XFC, and XTAL are clock reference connections.
2.2 MCU Power Connections
2.3 MCU Driver Types
T2CLK — Y Y — —
TPUCH[15:0] A Y Y — —
TSC — Y Y — —
TXD Bo Y Y I/O PQS7
XFC
2
— — — Special —
XTAL
2
— — — Special —
Table 3 MCU Power Connections
V
STBY
Standby RAM Power/Clock Synthesizer Power
V
DDSYN
Clock Synthesizer Power
V
SSE
/V
DDE
External Periphery Power (Source and Drain)
V
SSI
/V
DDI
Internal Module Power (Source and Drain)
Table 4 MCU Driver Types
Type I/O Description
A O Output-only signals that are always driven; no external pull-up required
Aw O Type A output with weak P-channel pull-up during reset
B O Three-state output that includes circuitry to pull up output before high impedance is
established, to ensure rapid rise time. An external holding resistor is required to maintain
logic level while the pin is in the high-impedance state.
Bo O Type B output that can be operated in an open-drain mode
Table 2 MCU Pin Characteristic (Continued)
Pin
Mnemonic Output
Driver Input
Synchronized Input
Hysteresis Discrete
I/O Port
Designation
MOTOROLA MC68332
12 MC68332TS/D
2.4 Signal Characteristics
Table 5 MCU Signal Characteristics
Signal Name MCU Module Signal Type Active State
ADDR[23:0] SIM Bus —
AS SIM Output 0
AVEC SIM Input 0
BERR SIM Input 0
BG SIM Output 0
BGACK SIM Input 0
BKPT CPU32 Input 0
BR SIM Input 0
CLKOUT SIM Output —
CS[10:0] SIM Output 0
CSBOOT SIM Output 0
DATA[15:0] SIM Bus —
DS SIM Output 0
DSACK[1:0] SIM Input 0
DSCLK CPU32 Input Serial Clock
DSI CPU32 Input (Serial Data)
DSO CPU32 Output (Serial Data)
EXTAL SIM Input —
FC[2:0] SIM Output —
FREEZE SIM Output 1
HALT SIM Input/Output 0
IFETCH CPU32 Output —
IPIPE CPU32 Output —
IRQ[7:1] SIM Input 0
MISO QSM Input/Output —
MODCLK SIM Input —
MOSI QSM Input/Output —
PC[6:0] SIM Output (Port)
PCS[3:0] QSM Input/Output —
PE[7:0] SIM Input/Output (Port)
PF[7:0] SIM Input/Output (Port)
PQS[7:0] QSM Input/Output (Port)
QUOT SIM Output —
RESET SIM Input/Output 0
RMC SIM Output 0
R/W SIM Output 1/0
RXD QSM Input —
SCK QSM Input/Output —
SIZ[1:0] SIM Output —
SS QSM Input 0
T2CLK TPU Input —
TPUCH[15:0] TPU Input/Output 1
MC68332 MOTOROLA
MC68332TS/D 13
2.5 Signal Function
TSC SIM Input —
TXD QSM Output —
XFC SIM Input —
XTAL SIM Output —
Table 6 MCU Signal Function
Signal Name Mnemonic Function
Address Bus ADDR[23:0] 24-bit address bus
Address Strobe AS Indicates that a valid address is on the address bus
Autovector AVEC Requests an automatic vector during interrupt acknowledge
Bus Error BERR Indicates that a bus error has occurred
Bus Grant BG Indicates that the MCU has relinquished the bus
Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership
Breakpoint BKPT Signals a hardware breakpoint to the CPU
Bus Request BR Indicates that an external device requires bus mastership
System Clockout CLKOUT System clock output
Chip Selects CS[10:0] Select external devices at programmed addresses
Boot Chip Select CSBOOT Chip select for external boot start-up ROM
Data Bus DATA[15:0] 16-bit data bus
Data Strobe DS During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle, indi-
cates that valid data is on the data bus.
Data and Size Acknowledge DSACK[1:0] Provide asynchronous data transfers and dynamic bus sizing
Development Serial In, Out,
Clock DSI, DSO,
DSCLK Serial I/O and clock for background debugging mode
Crystal Oscillator EXTAL, XTAL Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
Function Codes FC[2:0] Identify processor state and current address space
Freeze FREEZE Indicates that the CPU has entered background mode
Halt HALT Suspend external bus activity
Instruction Pipeline IFETCH
IPIPE Indicate instruction pipeline activity
Interrupt Request Level IRQ[7:1] Provides an interrupt priority level to the CPU
Master In Slave Out MISO Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Clock Mode Select MODCLK Selects the source and type of system clock
Master Out Slave In MOSI Serial output from QSPI in master mode;
serial input to QSPI in slave mode
Port C PC[6:0] SIM digital output port signals
Peripheral Chip Select PCS[3:0] QSPI peripheral chip selects
Port E PE[7:0] SIM digital I/O port signals
Port F PF[7:0] SIM digital I/O port signals
Port QS PQS[7:0] QSM digital I/O port signals
Table 5 MCU Signal Characteristics (Continued)
Signal Name MCU Module Signal Type Active State
MOTOROLA MC68332
14 MC68332TS/D
Quotient Out QUOT Provides the quotient bit of the polynomial divider
Reset RESET System reset
Read-Modify-Write Cycle RMC Indicates an indivisible read-modify-write instruction
Read/Write R/W Indicates the direction of data transfer on the bus
SCI Receive Data RXD Serial input to the SCI
QSPI Serial Clock SCK Clock output from QSPI in master mode;
clock input to QSPI in slave mode
Size SIZ[1:0] Indicates the number of bytes to be transferred during a bus cycle
Slave Select SS Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
TCR2 Clock T2CLK External clock source for TCR2 counter
TPU Channel Pins TPUCH[15:0] Bidirectional pins associated with TPU channels
Three-State Control TSC Places all output drivers in a high-impedance state
SCI Transmit Data TXD Serial output from the SCI
External Filter Capacitor XFC Connection for external phase-locked loop filter capacitor
Table 6 MCU Signal Function (Continued)
Signal Name Mnemonic Function
MC68332 MOTOROLA
MC68332TS/D 15
3 System Integration Module
The MCU system integration module (SIM) consists of five functional blocks that control system start-
up, initialization, configuration, and external bus.
Figure 5 SIM Block Diagram
3.1 Overview
The system configuration and protection block controls MCU configuration and operating mode. The
block also provides bus and software watchdog monitors.
The system clock generates clock signals used by the SIM, other IMB modules, and external devices.
In addition, a periodic interrupt generator supports execution of time-critical control routines.
The external bus interface handles the transfer of information between IMB modules and external ad-
dress space.
The chip-select block provides eleven general-purpose chip-select signals and a boot ROM chip select
signal. Both general-purpose and boot ROM chip-select signals have associated base address regis-
ters and option registers.
The system test block incorporates hardware necessary for testing the MCU. It is used to perform fac-
tory tests, and its use in normal applications is not supported.
The SIM control register address map occupies 128 bytes. Unused registers within the 128-byte ad-
dress space return zeros when read. The “Access” column in the SIM address map below indicates
which registers are accessible only at the supervisor privilege level and which can be assigned to either
the supervisor or user privilege level, according to the value of the SUPV bit in the SIMCR.
S(C)IM BLOCK
SYSTEM CONFIGURATION
AND PROTECTION
CLOCK SYNTHESIZER
CHIP SELECTS
EXTERNAL BUS INTERFACE
FACTORY TEST
CLKOUT
EXTAL
MODCLK
CHIP SELECTS
EXTERNAL BUS
RESET
TSC
FREEZE/QUOT
MOTOROLA MC68332
16 MC68332TS/D
Table 7 SIM Address Map
Access Address 15 8 7 0
S $YFFA00 SIM CONFIGURATION (SIMCR)
S $YFFA02 FACTORY TEST (SIMTR)
S $YFFA04 CLOCK SYNTHESIZER CONTROL (SYNCR)
S $YFFA06 NOT USED RESET STATUS REGISTER (RSR)
S $YFFA08 MODULE TEST E (SIMTRE)
S $YFFA0A NOT USED NOT USED
S $YFFA0C NOT USED NOT USED
S $YFFA0E NOT USED NOT USED
S/U $YFFA10 NOT USED PORT E DATA (PORTE0)
S/U $YFFA12 NOT USED PORT E DATA (PORTE1)
S/U $YFFA14 NOT USED PORT E DATA DIRECTION (DDRE)
S $YFFA16 NOT USED PORT E PIN ASSIGNMENT (PEPAR)
S/U $YFFA18 NOT USED PORT F DATA (PORTF0)
S/U $YFFA1A NOT USED PORT F DATA (PORTF1)
S/U $YFFA1C NOT USED PORT F DATA DIRECTION (DDRF)
S $YFFA1E NOT USED PORT F PIN ASSIGNMENT (PFPAR)
S $YFFA20 NOT USED SYSTEM PROTECTION CONTROL
(SYPCR)
S $YFFA22 PERIODIC INTERRUPT CONTROL (PICR)
S $YFFA24 PERIODIC INTERRUPT TIMING (PITR)
S $YFFA26 NOT USED SOFTWARE SERVICE (SWSR)
S $YFFA28 NOT USED NOT USED
S $YFFA2A NOT USED NOT USED
S $YFFA2C NOT USED NOT USED
S $YFFA2E NOT USED NOT USED
S $YFFA30 TEST MODULE MASTER SHIFT A (TSTMSRA)
S $YFFA32 TEST MODULE MASTER SHIFT B (TSTMSRB)
S $YFFA34 TEST MODULE SHIFT COUNT (TSTSC)
S $YFFA36 TEST MODULE REPETITION COUNTER (TSTRC)
S $YFFA38 TEST MODULE CONTROL (CREG)
S/U $YFFA3A TEST MODULE DISTRIBUTED REGISTER (DREG)
$YFFA3C NOT USED NOT USED
$YFFA3E NOT USED NOT USED
S/U $YFFA40 NOT USED PORT C DATA (PORTC)
$YFFA42 NOT USED NOT USED
S $YFFA44 CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
S $YFFA46 CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
S $YFFA48 CHIP-SELECT BASE BOOT (CSBARBT)
S $YFFA4A CHIP-SELECT OPTION BOOT (CSORBT)
S $YFFA4C CHIP-SELECT BASE 0 (CSBAR0)
S $YFFA4E CHIP-SELECT OPTION 0 (CSOR0)
S $YFFA50 CHIP-SELECT BASE 1 (CSBAR1)
S $YFFA52 CHIP-SELECT OPTION 1 (CSOR1)
S $YFFA54 CHIP-SELECT BASE 2 (CSBAR2)
MC68332 MOTOROLA
MC68332TS/D 17
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
3.2 System Configuration and Protection
This functional block provides configuration control for the entire MCU. It also performs interrupt arbi-
tration, bus monitoring, and system test functions. MCU system protection includes a bus monitor, a
HALT monitor, a spurious interrupt monitor, and a software watchdog timer. These functions have been
made integral to the microcontroller to reduce the number of external components in a complete control
system.
S $YFFA56 CHIP-SELECT OPTION 2 (CSOR2)
S $YFFA58 CHIP-SELECT BASE 3 (CSBAR3)
S $YFFA5A CHIP-SELECT OPTION 3 (CSOR3)
S $YFFA5C CHIP-SELECT BASE 4 (CSBAR4)
S $YFFA5E CHIP-SELECT OPTION 4 (CSOR4)
S $YFFA60 CHIP-SELECT BASE 5 (CSBAR5)
S $YFFA62 CHIP-SELECT OPTION 5 (CSOR5)
S $YFFA64 CHIP-SELECT BASE 6 (CSBAR6)
S $YFFA66 CHIP-SELECT OPTION 6 (CSOR6)
S $YFFA68 CHIP-SELECT BASE 7 (CSBAR7)
S $YFFA6A CHIP-SELECT OPTION 7 (CSOR7)
S $YFFA6C CHIP-SELECT BASE 8 (CSBAR8)
S $YFFA6E CHIP-SELECT OPTION 8 (CSOR8)
S $YFFA70 CHIP-SELECT BASE 9 (CSBAR9)
S $YFFA72 CHIP-SELECT OPTION 9 (CSOR9)
S $YFFA74 CHIP-SELECT BASE 10 (CSBAR10)
S $YFFA76 CHIP-SELECT OPTION 10 (CSOR10)
$YFFA78 NOT USED NOT USED
$YFFA7A NOT USED NOT USED
$YFFA7C NOT USED NOT USED
$YFFA7E NOT USED NOT USED
Table 7 SIM Address Map (Continued)
Access Address 15 8 7 0
MOTOROLA MC68332
18 MC68332TS/D
Figure 6 System Configuration and Protection Block
3.2.1 System Configuration
The SIM controls MCU configuration during normal operation and during internal testing.
The SIM configuration register controls system configuration. It can be read or written at any time, ex-
cept for the module mapping (MM) bit, which can be written only once.
SIMCR
—SIM Configuration Register
$YFFA00
15 14 13 12 11 10 9 8 7 6 5 4 3 0
EXOFF FRZSW FRZBM 0 SLVEN 0 SHEN SUPV MM 0 0 IARB
RESET:
0 000DATA1100011001111
SYS PROTECT BLOCK
MODULE CONFIGURATION
AND TEST
RESET STATUS
HALT MONITOR
BUS MONITOR
SPURIOUS INTERRUPT MONITOR
SOFTWARE WATCHDOG TIMER
PERIODIC INTERRUPT TIMER
PRESCALER
CLOCK
BERR
RESET REQUEST
RESET REQUEST
29
IRQ [7:1]
MC68332 MOTOROLA
MC68332TS/D 19
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters con-
tinue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are dis-
abled, preventing interrupts during software debug.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
This bit is a read-only status bit that reflects the state of DATA11 during reset.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. The table below shows whether show
cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,
external peripherals must not be enabled during show cycles.
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor or user data space.
0 = Registers with access controlled by the SUPV bit are accessible from either the user or super-
visor privilege level.
1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 –$7FFFFF.
1 = Internal modules are addressed from $FFF000 –$FFFFFF.
IARB[3:0] — Interrupt Arbitration Field
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a non-zero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU pro-
cesses a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU,
the SIM IARB field value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is
%0000, which prevents SIM interrupts from being discarded during initialization.
SHEN Action
00 Show cycles disabled, external arbitration enabled
01 Show cycles enabled, external arbitration disabled
10 Show cycles enabled, external arbitration enabled
11 Show cycles enabled, external arbitration enabled,
internal activity is halted by a bus grant
MOTOROLA MC68332
20 MC68332TS/D
3.2.2 System Protection Control Register
The system protection control register controls system monitor functions, software watchdog clock
prescaling, and bus monitor timing. This register can be written only once following power-on or reset,
but can be read at any time.
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following ta-
ble gives the ratio for each combination of SWP and SWT bits.
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the following table.
SYPCR
—System Protection Control Register
$YFFA21
15 87 6 543210
NOT USED SWE SWP SWT HME BME BMT
RESET:
1 MODCLK 0 0 0 0 0 0
SWP SWT Ratio
000
2
9
001
2
11
010
2
13
011
2
15
100
2
18
101
2
20
110
2
22
111
2
24
BMT Bus Monitor Time-out Period
00 64 System Clocks
01 32 System Clocks
10 16 System Clocks
11 8 System Clocks
MC68332 MOTOROLA
MC68332TS/D 21
3.2.3 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
3.2.4 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the HME bit in the SYPCR.
3.2.5 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-ac-
knowledge cycle.
3.2.6 Software Watchdog
The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that
a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watch-
dog times out and issues a reset. This register can be written at any time, but returns zeros when read.
Register shown with read value
Perform a software watchdog service sequence as follows:
a. Write $55 to SWSR.
b. Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
SWSR —Software Service Register $YFFA27
15 876543210
NOT USED 0 0 0 0 0 0 0 0
RESET:
00000000
MODCLK SWP
01
10