08/20/02
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ADVANCED ANALOG
HYBRID - HIGH RELIABILITY
RADIATION HARDENED DC/DC CONVERTER
ART28XXT SERIES
Description
nTotal Dose > 100KRad (Si), 2:1margin
nSEE hard to LET = 83 Mev.cm2 /mg
nDesigned to MIL-PRF-38534 for Class K
nDerated per MIL-STD-975 & MIL-STD-1547
nOutput Power Range 3 to 30 Watts
n19 to 50 Volt Input Range
nInput Undervoltage Lockout
nHigh Electrical Efficiency > 80%
nFull Performance from -55°C to +125°C
nContinuous Short Circuit Protection
n12.8 W / in3 Output Power Density
nTrue Hermetic Package
nExter nal Inhibit Port
nExternally Synchronizable
nFault Tolerant Design
n5V, ±12 or ±15 Volts Outputs Available
Features
ART
28V Input, Three Output
The ART Series of three output DC/DC converters are
designed specifically for use in the hostile radiation
environments characteristic of space and weapon sys-
tems. The extremely high level of radiation tolerance
inherent in the ART design is the culmination of exten-
sive research, thorough analysis and testing and of
careful component specification. Many of the best cir-
cuit design features characterizing the Advanced Ana-
log standard product line were adapted for incorpora-
tion into the ART topology. Capable of uniformly high
performance over long term exposures in radiation in-
tense environments, this series sets the standard for
distributed power systems demanding high perfor-
mance and reliability.
The ART converters are hermetically sealed in a rug-
ged, low profile package utilizing copper core pins to
minimize resistive DC losses. Long-term hermeticity is
assured through use of parallel seam welded lid at-
tachment along with Advanced Analog’s rugged ce-
ramic pin-to-package seal. Axial orentation of the leads
facilitates preferred bulkhead mounting to the principal
heat-dissipating surface.
Manufactured in a facility fully qualified to MIL-PRF-
38534, these converters are fabricated utilizing DSSC
qualified processes, and are fully compliant to Class H
while being fully processed to the requirements of Class
K. Complete PI & CI testing has been completed in-
cluding Group C life test. Variations in electrical, me-
chanical and screening specifications can be accom-
modated. Contact Advanced Analog for special require-
ments.
PD - 94529
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ART28XXT Series
For Notes to SPECIFICATIONS, refer to page 3
Input Voltage -0.5V to 80V Input Voltage Range 19V to 60V
Minimum Output Current 5% maximum rated 19V to 50V for full derating
current, any output to MIL-STD-975
Soldering Temperature 300°C for 10 seconds Output Power Range 3W to 30 W
Storage Temperature -65°C to +135°C Operating Temperature -55°C to +125°C
Absolute Maximum/Minimum Ratings Note1 Recommended Operating Conditions Note 2
SPECIFICATIONS
Electrical Performance -55°C < TCASE < +125°C, VIN=28V, CL=0 unless otherwise specified.
-55°C to +85°C for full
derating to MIL-STD-975
Parameter
Symbol
Conditions
Min
Max
Units
Outp ut vol tage accuracy
VOUT IOUT = 1.5Adc, TC = +25°C (main )
IOUT = ±250mAdc, TC = +25°C ART2812(dual)
IOUT = ±250mAdc, TC = +25°C ART2815(dual)
4.95
±11.50
±14.50
5.05
±12.50
±15.15
Vdc
Output power
Not e 5
P
OUT 19 Vdc< VIN < 50Vdc 3 30 W
Output current
Not e 5
IOUT (main)
19 Vdc< VIN < 50V dc
(dual)
150
75
3000
750
mAdc
Line regulation
Not e 3
VRLINE 150 mAdc < IOUT < 3000 mAdc (main)
19 Vdc< VIN < 50V dc
±75 mAdc < IOUT < ±750 mAdc (dual)
-15
-60
+15
+60
mV
Load r egulat ion
Not e 4
VRLOAD 150 mA dc < IOUT < 3000 mAdc (main)
19 Vdc< VIN < 50V dc
±75 mAdc < IOUT < ±750 mAdc (dual)
-180
-300
+180
+300
mV
Cros s r egulat i on
Note 8
VRCROSS (main)
19 Vdc< VIN < 50V dc
(dual)
-10
-500
+10
+500
mV
Tot al regu lation
VR All conditions of Line, Load, (main)
Cros s Reg ulat ion, Aging,
Temperature and Radiation ART2812(dual)
ART2815(dual)
4.8
±11.1
±13.9
5.2
±12.9
±16.0
V
Input c urrent
IIN IOUT = minimum rated , Pin 3 open
Pin 3 s horted to pin 2 ( disa bled)
250
8
mA
Out put ri ppl e v olta ge
Not e 6
V
RIP 19 Vdc< VIN < 50V dc
IOUT = 3000 mAdc (main), ±500 mA dc (dua l) 100 mVp.p
Input ripple current
Not e 6
I
RIP 19 Vdc< VIN < 50V dc
IOUT = 3000 mAdc (main), ±500 mA dc (dua l) 150 mAp.p
Switching frequency FS Sy c hr oniza t i on input ope n. ( pi n 6) 225 275 KHz
Efficiency Eff IOUT = 3000 mA dc (m ain), ±500 mA dc (dua l) 80 %
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ART28XXT Series
Electrical Performance (Continued)
1. Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently
degrade performance and affect reliability.
2. Device performance specified in El ectrical Performance table is guaranteed when operated within recommended limits. Oper ation outside
recommended limits is not specified.
3. Parameter measured from 28V to 19 V or to 50V while loads remain fixed.
4. Parameter measured from nominal to minimum or maximum load conditions while line remains fixed.
5. Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W.
6. Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth.
7. Load current is stepped for output under test while other outputs are fixed at half rated load.
8. Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum.
9. A capacitive load of any value from 0 to the specified max imum is permitted without comprise to DC performance. A capaciti ve load in excess of the
maximum limit may interfere with the proper operation of the converter’s short circuit protection, causing erratic behavior during turn on.
10. Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters s hall be guaranteed to the limits
specified in the table.
11. Load transient rate of change, di/dt ≤ 2 A/µSec.
12. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
13. Line transient rate of change, dv/dt ≤ 50 V/µSec.
14. Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the
input.
Notes to SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Max
Units
Enable Input
open circ uit voltage
dri ve cu rrent (si nk)
voltage range
3.0
-0.5
5.0
0.1
50.0
V
mA
V
Synchroni zation Input
frequency range
pulse high level
pulse low level
pulse rise time
pulse duty cycle
External clock signal on Sync. input (pin 4)
225
4.5
-0.5
40
20
310
10.0
0.25
80
KHz
V
V
V/µS
%
Power dissipation, load fault PD Short circuit, any output 7.5 W
Output response to step load
changes
Notes 7, 11
VTLD 10% Load to/from 50% load
50% Load to/from 100% load
-200
-200
200
200
mVPK
Recovery time from step load
changes
Notes 11, 12
TTLD 10% Load t o/from 50% load
50% Load t o/from 100% load
200
200
µS
Output response to step line
changes
Notes 10, 11
VTLN I
OUT = 3000 mAdc (main)
VIN = 19 V to/from 50 V
I
OUT = ±500 m Adc (dual)
-350
-1050
350
1050
mVPK
Recovery time from step line
changes
Notes 10, 11,13
TTLN I
OUT = 3000 mAdc (main)
VIN = 19 V to/from 50 V
I
OUT = ±500 m Adc (dual)
500
500
µS
Turn on overshoot
VOS (main)
IOUT = mini mum and full rated
(dual)
500
1500
mV
Turn on delay
Note 14
T
DLY I
OUT = mi ni mum and ful l rated 5 20 mS
Capacitive load
Notes 9, 10
CL (main)
No effect on DC performance
(dual)
500
100
µF
Isolation ISO 500V DC Input to Output or any pin to case
(except pin 12) 100
MΩ
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ART28XXT Series
Group A Tests VIN= 28Volts, CL =0 unless otherwise specified.
Notes to Group A Test Table
1. Parameter verified during dynamic load regulation tests.
2. Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.
3. Load current is stepped for output under test while other outputs are fixed at half rated load.
4. Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.
5. Load step transition time ≥ 10µS.
6. Recovery time is measured from the initiation of the transient to where V OUT has returned to within ±1% of its steady s tate value.
7. Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
8. Subgroups 1 and 4 are performed at +25ºC, subgroups 2 and 5 at -55ºC and subgroups 3 and 6 at +125ºC.
Test
Symbol
Conditi ons unless otherwise specified Gro up A
Subgroups
Min
Max
Units
Output voltage accuracy
VOUT IOUT = 1.5 Adc (main)
IOUT = ±250mAdc ART2812(dual)
IOUT = ±250mAdc ART2815(dual)
1, 2, 3
1, 2, 3
1, 2, 3
4.95
±11.70
±14.50
5.05
±12.30
±15.15
V
Output power
Note 1
P
OUT V
IN = 19 V, 28V , 50 V 1, 2, 3 3 30 W
Output current
Note 1
IOUT (main)
VIN 19 V , 28V, 50 V
(dual)
1, 2, 3
1, 2, 3
150
75
3000
500
mA
Output regulatio n
Note
4
VR IOUT = 150, 1500, 3000mAdc (main)
VIN = 19 V, 28V, 50 V
IOUT = ±75, ±310, ±625mAdc 2812(dual)
IOUT = ±75, ±250, ±500mAdc 2815(dual)
1, 2, 3
1, 2, 3
1, 2, 3
4.8
±11.1
±14.0
5.2
±12.9
±15.8
V
Input current
IIN IOUT = mi nimum rated, Pin 3 open
Pin 3 shorted to pin 2 (dis abled)
1, 2, 3
1, 2, 3
250
8
mA
Output ri pple
Note 2
V
RIP V
IN = 19 V, 28V , 50 V
IOUT = 3000mA main, ±500mA dual 1, 2, 3 100 mV P-P
Input ripple
Note 2
I
RIP V
IN = 19 V, 28V , 50 V
IOUT = 3000mA main, ±500mA dual 1, 2, 3 150 mA P-P
Switc hing frequency FS Synchroni zation pin (pi n 6) open 4, 5, 6 225 275 KHz
Efficiency Eff IOUT = 800mA main, ±500mA dual 1
2, 3 80
78 %
Power dissipati on,
load fault PD Short circ uit, any output 1, 2, 3 7.5 W
Output response to step
load changes
Notes 3,
5
VTL 10% Load t o/from 50% load
50% Load t o/f rom 100% load
4, 5, 6
4, 5, 6
-200
-200
200
200
mVPK
Recovery time from
step load changes
Notes 5, 6
TTL 10% Load t o/from 50% load
50% Load t o/f rom 100% load
4, 5, 6
4, 5, 6
200
200
µS
Turn on oversho ot
VOS (main)
IOUT = minimum and f ul l rated
(dual)
4, 5, 6
4, 5, 6
500
1500
mV
Turn on delay
Note 7
T
DLY I
OUT = mi nimum and full rated 4, 5, 6 5 20 mS
Isolat ion ISO 500VDC Input to output or any pin to case
(except pin 12) 1 100
MΩ
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ART28XXT Series
Radiation Performance
The radiation tolerance characteristics inherent in the
ART28XXT converter are the direct result of a carefully
planned ground-up design program with specific radiation
design goals. After identification of the general circuit to-
pology, a primary task of the design effort was selection of
appropriate elements from the list of devices for which
extensive radiation effects data was available. By impos-
ing sufficiently large margins on those electrical param-
eters subject to the degrading effects of radiation, design-
ers were able to select appropriate elements for incorpo-
ration into the circuit. Known radiation data was utilized for
input to PSPICE and RadSPICE in the generation of circuit
performance verification analyses. Thus, electrical per-
formance capability under all environmental conditions in-
cluding radiation was well understood before first applica-
tion of power to the inputs.
A principal design goal was a converter topology that, be-
cause of large design margins, had radiation performance
essentially independent of normal elemental lot radiation
Completion of first article fabrication, screening and stan-
dard environmental testing was followed by radiation test-
ing to confirm design goals. All design goals were met
handily and in most cases exceeded by large margin.
These test samples were built with elements that, with the
foregoing exceptions, were
not
screened for radiation char-
acteristics. Additional radiation tests on subsequent
ART28XXT manufacturing lots provide continued confir-
mation of the soundness of the design goals as well as
justification for the element selection criteria.
The following table specifies guaranteed minimum radia-
tion exposure levels tolerated while maintaining specifica-
tion limits.
performance variations. In the few instances where such
margins were not assured, element lots were selected
from which die were fabricated (and characterized) as
radiation hard devices so that realization of the design
goals could be assured.
Radiation Specification Tcase = 25°C
Test Conditions Min Typ Max Unit
Tota l Ioniz ing Dose
(2:1 Margin) MIL-STD -883, Met hod 1019. 4
Operati ng bias applie d during exp osure 100 500 KRads
(Si)
Dose Rate
Temporary Saturation
Survival
MIL-STD-883, Method 1021
1E8
1E11
Rads
(Si)/sec
Neutron Fluence MIL-STD-883, Method 1017.2 3E12 Neutron
/cm²
Heavy Ions
(Single event effects) BNL Tandem Van de Graaff Generator 83 MeV•
cm²/mg
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ART28XXT Series
ART28XXT Circuit Description
Figure I. ART Block Diagram
Circuit Description and Application Information
Sam
p
le
Hold
+Vout
Dual
Return
-Vout
Dual
+5
Return
Short
Circuit
Pulse Width
Modulator
Primar
y
Bias
& Reference
EMI
Filter
Under-Volta
g
e
Detector
+In
p
ut
Enable
S
y
nc
In
p
ut
Return
The ART28XXT series of converters have been designed
using a single ended forward switched mode converter
topology. (refer to Figure I.) Single ended topologies enjoy
some advantage in radiation hardened designs in that they
eliminate the possibility of simultaneous turn on of both
switching elements during a radiation induced upset; in
addition, single ended topologies are not subject to trans-
former saturation problems often associated with double
ended implementations.
The design incorporates an LC input filter to attenuate
input ripple current. A low overhead linear bias regulator is
used to provide bias voltage for the converter primary
control logic and a stable, well regulated reference for the
error amplifier. Output control is realized using a wide
band discrete pulse width modulator control circuit incor-
porating a unique non-linear ramp generator circuit. This
circuit helps stabilize loop gain over variations in line volt-
age for superior output transient response. Nominal con-
version frequency has been selected as 250 KHz to maxi-
mize efficiency and minimize magnetic element size.
Output voltages are sensed using a coupled inductor and
a patented magnetic feedback circuit. This circuit is rela-
tively insensitive to variations in temperature, aging, ra-
diation and manufacturing tolerances making it particu-
larly well suited to radiation hardened designs. The control
logic has been designed to use only radiation tolerant com-
ponents, and all current paths are limited with series re-
sistance to limit photo currents.
Other key circuit design features include short circuit pro-
tection, undervoltage lockout and an external synchroni-
zation port permitting operation at an externally set clock
rate.
The circuit topology used for regulating output voltages in
the ART28XXT series of converters was selected for a
number of reasons. Significant among these is the ability
to simultaneously provide adequate regulation to each
output voltage while maintaining modest circuit complexity.
These attributes were fundamental in retaining the high
reliability and insensitivity to radiation that characterizes
device performance. Use of this topology dictates that the
user maintain a minimum load on each output as specified
in the electrical tables. Attempts to operate any output
without a load will result in peak charging to a voltage level
well above the specified voltage regulation limits, poten-
tially in excess of ratings, and should be avoided. In most
practical applications, this lower bound on the load range
does not present a serious constraint. Output loads that
are lighter than the specified minimums will result in regu-
lation performance exceeding the limits presented in the
specification tables. Regulation curves illustrating repre-
sentative performance characteristics are shown in Fig-
ures VII, VIII and IX.
Operating Guidelines
Thermal Considerations
The ART series of converters is capable of providing rela-
tively high output power from a package of modest vol-
ume. The power density exhibited by these devices is
obtained by combining high circuit efficiency with effective
methods of heat removal from the die junctions. Good
design practices have effectively addressed this require-
ment inside the device. However when operating at maxi-
mum loads, significant heat generated at the die junctions
must be carried away by conduction from the base. To
maintain case temperature at or below the specified maxi-
mum of 125°C, this heat can be transferred by attachment
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ART28XXT Series
to an appropriate heat dissipater held in intimate contact
with the converter base-plate.
Effectiveness of this heat transfer is dependent on the
intimacy of the baseplate-heatsink interface. It is there-
fore suggested that a heat transferring medium possess-
ing good thermal conductivity is inserted between the
baseplate and heatsink. A material utilized at the factory
during testing and burn-in processes is sold under the
trade name of Sil-Pad4001. This particular product is an
insulator but electrically conductive versions are also avail-
able. Use of these materials assures optimum surface
contact with the heat dissipater by compensating for mi-
nor surface variations. While other available types of heat
conducting materials and thermal compounds provide simi-
lar effectiveness, these alternatives are often less conve-
nient and are frequently messy to use.
A conservative aid to estimating the total heat sink surface
area (AHEAT SINK) required to set the maximum case tem-
perature rise (∆T) above ambient temperature is given by
the following expression:
A HEAT SINK ≈
−
−
∆T
P80 594
085
143
.
..
∆T
PP
Eff
OUT
=
==−
Case temper ature ris e above a m bient
Device dissipation in Watts 11
where
As an example, assume that it is desired to maintain the
case temperature of an ART2815T at +65°C or less while
operating in an open area whose ambient temperature
does not exceed +35°C; then
∆T = 65 - 35 = 35°C
From the Specification Table, the worst case full load effi-
ciency for this device is 80%; therefore the maximum power
dissipation at full load is given by
()
P=• −
=• =
30 1
80 13002575
...W
and the required heat sink area is
A = 35
80 7.5 in
HEAT SINK 0.85
•
−=
−143 2
594 318
...
1Sil-P ad is a registered Tr ade Mark of Bergquist, Minneapolis, MN
Thus, a total heat sink surface area (including fins, if any)
of approximately 32 in2 in this example, would limit case
rise to 35°C above ambient. A flat aluminum plate, 0.25"
thick and of approximate dimension 4" by 4" (16 in2 per
side) would suffice for this application in a still air environ-
ment. Note that to meet the criteria, both sides of the plate
require unrestricted exposure to the ambient air.
Inhibiting Converter Output
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing an input referenced, TTL compatible,
logic signal to the enab le pin 3. This port is internally pulled
“high” so that when not used, an open connection on the
pin permits normal converter operation. When inhibited
outputs are desired, a logical “low” on this port will shut the
converter down. An open collector device capable of sink-
ing at least 100 µA connected to enable pin 3 will work well
in this application.
Figure II. Enable Input Equivalent Circuit
A benefit of utilization of the enable input is that following
initial charge of the input capacitor, subsequent turn-on
commands will induce no uncontrolled current inrush.
5K
2N2907A
150K
Enable
Input
Input
Return
150K
2N2222A
2N2222A
V
in
64K
186K
150K
5.6 V
Converter inhibit is initiated when
this transistor is turned off
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ART28XXT Series
Figure III. Synchronization Input Equivalent Circuit
5K
2N2907A
5K
47pf
Sync
Input
Input
Return
+10V
Protection against accidental short circuits on any output
is provided in the ART28XXT converters. This protection
is implemented by sensing primary switching current and,
when an over-current condition is detected, switching ac-
tion is terminated and a restart cycle is initiated. If the
short circuit condition has not been cleared by the time the
restart cycle has completed, another restart cycle is initi-
ated. The sequence will repeat until the shor t circuit con-
dition is cleared at which time the converter will resume
normal operation. The effect is that during a shor ted con-
dition, a series of narrow pulses are generated at approxi-
mately 5% duty cycle which periodically sample the state
of the load. Thus device power dissipation is greatly re-
duced during this mode of operation.
Output Short Circuit Protection
Parallel Operation
Although no special provision for forced current sharing
has been incorporated in the ART28XXT series, multiple
units may be operated in parallel for increased output power
applications. The 5 v olt outputs will typically share to within
approximately 10% of their full load capability and the dual
(±15 volt) outputs will typically share to within 50% of their
full load. Load sharing is a function of the individual imped-
ance of each output and the converter with the highest
nominal set voltage will furnish the predominant load cur-
rent.
A minimum voltage is required at the input of the converter
to initiate operation. This voltage is set to a nominal value
of 16.8 volts. To preclude the possibility of noise or other
variations at the input falsely initiating and halting con-
verter operation, a hysteresis of approximately 1.0 volts
is incor porated in this circuit. The converter is guaranteed
to operate at 19 Volts input under all specified conditions.
Input Undervoltage Protection
Input Filter
To attenuate input ripple current, the ART28XXT series
converters incor porate a single stage LC input filter. The
elements of this filter comprise the dominant input load
impedance characteristic, and therefore determine the
nature of the current inrush at turn-on. The input filter
circuit elements are as shown in Figure IV.
+ Input
Input
Return
3.6 µH
5.4 µfd
10
Ω
Figure IV. Input Filter Circuit
Synchronization
When using multiple converters, system requirements may
dictate operating several converters at a common sys-
tem frequency. To accommodate this requirement, the
ART28XXT type converter provides a synchronization
input port (pin 4). Circuit topology is as illustrated in Figure
III.
The sync input port permits synchronization of an ART
converter to any compatible external frequency source
operating in the band of 225 to 310 KHz. The synchroniza-
tion input is edge triggered with synchronization initiated
on the negative transition. This input signal should be a
negative going pulse referenced to the input return and
have a 20% to 80% duty cycle. Compatibility requires the
negative transition time to be less than 100 ns with a mini-
mum pulse amplitude of +4.25 volts referred to the input
return. In the event of failure of an external synchroniza-
tion source, the converter will revert to its own internally
set frequency. When external synchronization is not de-
sired, the sync in port may be left open (unconnected)
permitting the converter to operate at its’ own internally set
frequency.
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ART28XXT Series
Additional Filtering
Figure V. External Input EMI Filter
Although internal filtering is provided at both input and out-
put terminals, some applications may require additional
filtering in order to accommodate system requirements.
While the internal input filter of Figure IV. keeps input ripple
current below 100 mAp-p, an external filter may be applied
to further attenuate this ripple to a level below the CE03
limits imposed by MIL-STD-461B. Figure V. describes a
filter providing that attenuation.
This circuit shown in Figure V has been constructed on
copper clad board using the materials listed and tested in
the laboratory.
An external filter may also be added to the output where
circuit requirements dictate extremely low output ripple
noise. The output filter described by Figure VI has been
characterized with the ART2815T using the values shown
in the associated material list.
It is important to be aware that when filtering high fre-
quency noise, parasitic circuit elements can easily domi-
nate filter performance. Therefore, it is incumbent on the
designer to exercise care when preparing a circuit layout
for such devices. Wire runs and lengths should be mini-
mized, high frequency loops should be avoided and care-
ful attention paid to the construction details of magnetic
circuit elements. Tight magnetic coupling will improv e overall
magnetic performance and reduce stray magnetic fields.
+5 V
5V
Return
+15V
15V
Return
-15V
+5V Out
+5V
Return
+15V
Out
15V
Return
-15V
Out
C1
C2
C3
C4
C5
C6
C7
C8
L1
L2 L4
L3
L1
7 turns AWG21 bifilar on Mag Inc. core PN YJ-41305-TC or equivalent.
L2
7 turns AWG24 trifilar on Mag Inc. core PN YJ-41305-TC or equivalent.
L3
4 turns AWG21 on Mag Inc. core PN MPP55048 or equivalent.
L4
5 turns AWG21 bifilar on Mag Inc. core PN MPP55048 or equivalent.
C1-C5
2200pF type CKR ceramic capacitor.
C6
170µF, 15V M39006/22-0514 Tantalum.
C7, C8
25µF, 50V M39006/22-0568 Tantalum.
Figure VI. External Output Filter
Measurement techniques can impose a significant influ-
ence on results. All noise measurements should be mea-
sured with test leads as close to the device output pins as
physically possible. Probe ground leads should be kept to
a minimum length.
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ART28XXT Series
Performance Characteristics (T ypical @ 25°C)
50
55
60
65
70
75
80
85
0 5 10 15 20 25 30 35
Outp ut Po we r ( Watts)
Efficiency (%)
18V
28V
50V
Figure VII. Efficiency vs Output Power
for Three Line Voltages.
Figure VIII. 5 V Output Regulation Limits
Including all conditions of Line, Load and Cross Regulation.
4.7
4.8
4.9
5.0
5.1
5.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Out
p
ut Cur rent
(
Am
p
s
)
Output Voltag
e
Upper Limi t
Lower Limi t
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ART28XXT Series
Figure IX. ±15 V Regulation Curves
For Three conditions of Load on the 5 Volt Output.
Performance Characteristics (T ypical @ 25°C) (Continued)
Figure X. Cross Regulation Curves
5 Volt Output as a function of 15 Volt Load Current for Three 5 Volt Loads.
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
0 0.1 0.2 0.3 0.4 0.5 0.6
±1 5 Volt Load Cur r ent
Output Voltage
5V Loa d = 150mA
5V Loa d = 1.5A
5V Loa d = 3.0A
14.0
15.0
16.0
17.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Output Current (Each Output)
Output Voltage (Magnitude)
5V Load = 3.0A
5V Load = 1.5A
5V Load = 150 mA
12 www.irf.com
ART28XXT Series
ART28XXT Physical & Interface Characteristics
ART28XXT Case Outline
54321
8 9 10 11 12 13 14
2.400
1.400
2.700
0.150
3.25 Ref.
Max
6 x 0.200
= 1.200
1.675 2.200
0.300
0.263
Ø 0.136 - 6 Holes
0.375
1.950
0.138
0.500
Max
Mountin
g
Plane
0.040
Pin Dia.
0.050
Flan
g
e
0.275
0.240
Note: 1. Dimensions are in inche s .
2. Base Plate Mounting Plane Flatness 0.003 maximum.
3. Unless otherwise specified, tolerances are
∠ = ± 2°
. XX = ± .01
. XX X = ± .005
4. Device W eight - 120 grams maximum.
Pi n # Signal
1 + V input
2 Input return
3 Enable
4 Sync In
5 No connection
8 No connection
9 - 15 Vdc outp ut
10 15 Vd c outp ut retu rn
11 + 15 Vdc output
12 Chassis
13 + 5 Vd c output
14 5 Vdc output return
Pin Designation Part Numbering
ART 28 15 T / EM
Model
Input Voltage
28 = 28V
100 = 100V
Outputs
T = Triple
Output Voltages
15 = 5V, ± 15V
12 = 5V, ± 12V
Screening Level
No Su f f ix = Flight
/EM = Engineering
Radiation performance not specified for /EM screened device type.
Note:
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ART28XXT Series
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
ADVANCED ANALOG: 2270 Martin Av., Santa Clara, California 95050, Tel: (408) 727-0500
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 08/02
Standard Process Screening for ART28XXT Series
Standard Periodic & Conformance Inspections on ART28XXT Series
Requirement MIL-STD-883
Method /EM Limits Flight Limits
(Class K)
T em p era ture Ran ge -5 5° C to +1 25 °C -5 5° C to +1 25 °C
Element Evaluation N/A MIL-PRF-38534
Non-destructi v e Bond Pul l 2023 N/A 100%
Internal Visual 2017 ✓ ✓
Temperature Cycle 1010 ✓ Cond C
Constant Acceleration 2001, 500 g Con d A
PIND 2020 N/A Cond A
Burn-in
Interim Electrical @ 160 hrs 1015 160 hrs @ 125 °C 320 hrs @ 125°C
(2 × 160 hrs)
Final Elect rical ( Group A)
Read & Record Data MI L-PRF-38534
& Specifi cation -55, +25, +125°C -55, +25, +125°C
PDA (25°C, interim to fina l) N/A 2%
Radiographic Inspection 2012 N/A ✓
Seal, Fine & Gross 1014 ✓ Cond A, C
External Visual 2009 ✓ ✓
Inspection Application Quantity
Group A Par t of Sc r eening on Ea c h U nit 100%
Group B Eac h I nspect ion Lot *5 unit s
Group C Fi rst In s pec tion L ot or
Fol lowing C lass 1 Ch ange 10 Units
Group D In Line (Part of Element Evaluation)
* Group B quantity for Option 2 End of Line QCI. No Group B samples reuired for Option 1, In-line.
