MT41J128M16JT-187E:K - Micron Technology, Inc.

DDR3 SDRAM

MT41J512M4 – 64 Meg x 4 x 8 Banks

MT41J256M8 – 32 Meg x 8 x 8 Banks

MT41J128M16 – 16 Meg x 16 x 8 Banks

Features

•V

DD = VDDQ = 1.5V ±0.075V

• 1.5V center-terminated push/pull I/O

• Differential bidirectional data strobe

•8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS READ latency (CL)

• Posted CAS additive latency (AL)

• Programmable CAS WRITE latency (CWL) based on

tCK

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

•T

C of 0°C to 95°C

– 64ms, 8192 cycle refresh at 0°C to 85°C

– 32ms, 8192 cycle refresh at 85°C to 95°C

• Self refresh temperature (SRT)

• Write leveling

• Multipurpose register

• Output driver calibration

Options1Marking

• Configuration

– 512 Meg x 4 512M4

– 256 Meg x 8 256M8

– 128 Meg x 16 128M16

• FBGA package (Pb-free) – x4, x8

– 78-ball (8mm x 10.5mm) Rev. M, K DA

– 78-ball (9mm x 11.5mm) Rev. D HX

• FBGA package (Pb-free) – x16

– 96-ball (9mm x 14mm) Rev. D HA

– 96-ball (8mm x 14mm) Rev. K JT

• Timing – cycle time

– 938ps @ CL = 14 (DDR3-2133) -093

– 1.071ns @ CL = 13 (DDR3-1866) -107

– 1.25ns @ CL = 11 (DDR3-1600) -125

– 1.5ns @ CL = 9 (DDR3-1333) -15E

– 1.87ns @ CL = 7 (DDR3-1066) -187E

• Operating temperature

– Commercial (0°C ≤ TC ≤ +95°C) None

– Industrial (–40°C ≤ TC ≤ +95°C) IT

• Revision :D/:M/:K

Note: 1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on http://www.micron.com

for available offerings.

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)

-0931, 2, 3, 4 2133 14-14-14 13.09 13.09 13.09

-1071, 2, 3 1866 13-13-13 13.91 13.91 13.91

-1251, 2, 1600 11-11-11 13.75 13.75 13.75

-15E1, 1333 9-9-9 13.5 13.5 13.5

-187E 1066 7-7-7 13.1 13.1 13.1

Notes: 1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-125).

4. Backward compatible to 1866, CL = 13 (-107).

2Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16

Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks

Refresh count 8K 8K 8K

Row addressing 32K (A[14:0]) 32K (A[14:0]) 16K (A[13:0])

Bank addressing 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0])

Column addressing 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0])

Page size 1KB 1KB 2KB

Figure 1: DDR3 Part Numbers

Package

78-ball 9mm x 11.5mm FBGA

78-ball 8mm x 10.5mm FBGA

96-ball 9mm x 14mm FBGA

Example Part Number: MT41J256M8DA-125:K

96-ball 8mm x 14mm FBGA

Configuration

512 Meg x 4

256 Meg x 8

128 Meg x 16

512M4

256M8

128M16

Speed Grade

tCK = 1.071ns, CL = 13

tCK = 1.25ns, CL = 11

tCK = 1.5ns, CL = 9

tCK = 1.87ns, CL = 7

-107

-125

-15E

-187E

Configuration

MT41J Package Speed

Revision

tCK = 0.938ns, CL = 14-093

Revision

:D/:M/:K

Temperature

Commercial

Industrial temperature

None

Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the

part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:

http://www.micron.com.

2Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.

Contents

State Diagram ................................................................................................................................................ 11

Functional Description ................................................................................................................................... 12

Industrial Temperature ............................................................................................................................... 12

General Notes ............................................................................................................................................ 12

Functional Block Diagrams ............................................................................................................................. 14

Ball Assignments and Descriptions ................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 22

Electrical Specifications .................................................................................................................................. 26

Absolute Ratings ......................................................................................................................................... 26

Input/Output Capacitance .......................................................................................................................... 27

Thermal Characteristics .................................................................................................................................. 28

Electrical Specifications – IDD Specifications and Conditions ............................................................................ 30

Electrical Characteristics – IDD Specifications .................................................................................................. 41

Electrical Specifications – DC and AC .............................................................................................................. 44

DC Operating Conditions ........................................................................................................................... 44

Input Operating Conditions ........................................................................................................................ 44

AC Overshoot/Undershoot Specification ..................................................................................................... 47

Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 51

Slew Rate Definitions for Differential Input Signals ...................................................................................... 53

ODT Characteristics ....................................................................................................................................... 54

ODT Resistors ............................................................................................................................................ 55

ODT Sensitivity .......................................................................................................................................... 56

ODT Timing Definitions ............................................................................................................................. 56

Output Driver Impedance ............................................................................................................................... 60

34 Ohm Output Driver Impedance .............................................................................................................. 61

34 Ohm Driver ............................................................................................................................................ 62

34 Ohm Output Driver Sensitivity ................................................................................................................ 63

Alternative 40 Ohm Driver .......................................................................................................................... 64

40 Ohm Output Driver Sensitivity ................................................................................................................ 64

Output Characteristics and Operating Conditions ............................................................................................ 66

Reference Output Load ............................................................................................................................... 68

Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 69

Slew Rate Definitions for Differential Output Signals .................................................................................... 70

Speed Bin Tables ............................................................................................................................................ 71

Electrical Characteristics and AC Operating Conditions ................................................................................... 76

Command and Address Setup, Hold, and Derating ........................................................................................... 96

Data Setup, Hold, and Derating ...................................................................................................................... 104

Commands – Truth Tables ............................................................................................................................. 113

Commands ................................................................................................................................................... 116

DESELECT ................................................................................................................................................ 116

NO OPERATION ........................................................................................................................................ 116

ZQ CALIBRATION LONG ........................................................................................................................... 116

ZQ CALIBRATION SHORT .......................................................................................................................... 116

ACTIVATE ................................................................................................................................................. 116

READ ........................................................................................................................................................ 116

WRITE ...................................................................................................................................................... 117

PRECHARGE ............................................................................................................................................. 118

REFRESH .................................................................................................................................................. 118

SELF REFRESH .......................................................................................................................................... 119

DLL Disable Mode ..................................................................................................................................... 120

2Gb: x4, x8, x16 DDR3 SDRAM

Features

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2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

Input Clock Frequency Change ...................................................................................................................... 124

Write Leveling ............................................................................................................................................... 126

Write Leveling Procedure ........................................................................................................................... 128

Write Leveling Mode Exit Procedure ........................................................................................................... 130

Initialization ................................................................................................................................................. 131

Mode Registers .............................................................................................................................................. 133

Mode Register 0 (MR0) ................................................................................................................................... 134

Burst Length ............................................................................................................................................. 134

Burst Type ................................................................................................................................................. 135

DLL RESET ................................................................................................................................................ 136

Write Recovery .......................................................................................................................................... 136

Precharge Power-Down (Precharge PD) ...................................................................................................... 137

CAS Latency (CL) ....................................................................................................................................... 137

Mode Register 1 (MR1) ................................................................................................................................... 138

DLL ENABLE/DISABLE .............................................................................................................................. 138

Output Drive Strength ............................................................................................................................... 139

OUTPUT ENABLE/DISABLE ...................................................................................................................... 139

TDQS ENABLE .......................................................................................................................................... 139

On-Die Termination (ODT) ........................................................................................................................ 140

WRITE LEVELING ..................................................................................................................................... 140

Posted CAS Additive Latency (AL) ............................................................................................................... 140

Mode Register 2 (MR2) ................................................................................................................................... 142

CAS WRITE Latency (CWL) ........................................................................................................................ 142

AUTO SELF REFRESH (ASR) ....................................................................................................................... 143

SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 143

SRT versus ASR .......................................................................................................................................... 144

Dynamic On-Die Termination (ODT) ......................................................................................................... 144

Mode Register 3 (MR3) ................................................................................................................................... 145

MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 145

MPR Functional Description ...................................................................................................................... 146

MPR Address Definitions and Bursting Order .............................................................................................. 147

MPR Read Predefined Pattern .................................................................................................................... 152

MODE REGISTER SET (MRS) Command ........................................................................................................ 152

ZQ CALIBRATION Operation ......................................................................................................................... 153

ACTIVATE Operation ..................................................................................................................................... 154

READ Operation ............................................................................................................................................ 156

WRITE Operation .......................................................................................................................................... 167

DQ Input Timing ....................................................................................................................................... 175

PRECHARGE Operation ................................................................................................................................. 177

SELF REFRESH Operation .............................................................................................................................. 177

Extended Temperature Usage ........................................................................................................................ 179

Power-Down Mode ........................................................................................................................................ 180

RESET Operation ........................................................................................................................................... 188

On-Die Termination (ODT) ............................................................................................................................ 190

Functional Representation of ODT ............................................................................................................. 190

Nominal ODT ............................................................................................................................................ 190

Dynamic ODT ............................................................................................................................................... 192

Dynamic ODT Special Use Case ................................................................................................................. 192

Functional Description .............................................................................................................................. 192

Synchronous ODT Mode ................................................................................................................................ 198

ODT Latency and Posted ODT .................................................................................................................... 198

Timing Parameters .................................................................................................................................... 198

2Gb: x4, x8, x16 DDR3 SDRAM

Features

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2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.

ODT Off During READs .............................................................................................................................. 201

Asynchronous ODT Mode .............................................................................................................................. 203

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 205

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 207

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 209

2Gb: x4, x8, x16 DDR3 SDRAM

Features

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2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Figures

Figure 1: DDR3 Part Numbers .......................................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................. 11

Figure 3: 512 Meg x 4 Functional Block Diagram ............................................................................................. 14

Figure 4: 256 Meg x 8 Functional Block Diagram ............................................................................................. 15

Figure 5: 128 Meg x 16 Functional Block Diagram ........................................................................................... 15

Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16

Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17

Figure 8: 78-Ball FBGA – x4, x8 (DA) ............................................................................................................... 22

Figure 9: 78-Ball FBGA – x4, x8 (HX) ............................................................................................................... 23

Figure 10: 96-Ball FBGA – x16 (HA) ................................................................................................................. 24

Figure 11: 96-Ball FBGA – x16 (JT) .................................................................................................................. 25

Figure 12: Thermal Measurement Point ......................................................................................................... 29

Figure 13: Input Signal .................................................................................................................................. 46

Figure 14: Overshoot ..................................................................................................................................... 47

Figure 15: Undershoot ................................................................................................................................... 47

Figure 16: VIX for Differential Signals .............................................................................................................. 49

Figure 17: Single-Ended Requirements for Differential Signals ........................................................................ 49

Figure 18: Definition of Differential AC-Swing and tDVAC ............................................................................... 50

Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 52

Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 53

Figure 21: ODT Levels and I-V Characteristics ................................................................................................ 54

Figure 22: ODT Timing Reference Load .......................................................................................................... 57

Figure 23: tAON and tAOF Definitions ............................................................................................................ 58

Figure 24: tAONPD and tAOFPD Definitions ................................................................................................... 58

Figure 25: tADC Definition ............................................................................................................................. 59

Figure 26: Output Driver ................................................................................................................................ 60

Figure 27: DQ Output Signal .......................................................................................................................... 67

Figure 28: Differential Output Signal .............................................................................................................. 68

Figure 29: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 68

Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 69

Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 70

Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 100

Figure 33: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 101

Figure 34: Tangent Line for tIS (Command and Address – Clock) .................................................................... 102

Figure 35: Tangent Line for tIH (Command and Address – Clock) .................................................................... 103

Figure 36: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 109

Figure 37: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 110

Figure 38: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 111

Figure 39: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 112

Figure 40: Refresh Mode ............................................................................................................................... 119

Figure 41: DLL Enable Mode to DLL Disable Mode ........................................................................................ 121

Figure 42: DLL Disable Mode to DLL Enable Mode ........................................................................................ 122

Figure 43: DLL Disable tDQSCK .................................................................................................................... 123

Figure 44: Change Frequency During Precharge Power-Down ........................................................................ 125

Figure 45: Write Leveling Concept ................................................................................................................. 126

Figure 46: Write Leveling Sequence ............................................................................................................... 129

Figure 47: Write Leveling Exit Procedure ....................................................................................................... 130

Figure 48: Initialization Sequence ................................................................................................................. 132

Figure 49: MRS to MRS Command Timing (tMRD) ......................................................................................... 133

Figure 50: MRS to nonMRS Command Timing (tMOD) .................................................................................. 134

2Gb: x4, x8, x16 DDR3 SDRAM

Features

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Figure 51: Mode Register 0 (MR0) Definitions ................................................................................................ 135

Figure 52: READ Latency .............................................................................................................................. 137

Figure 53: Mode Register 1 (MR1) Definition ................................................................................................. 138

Figure 54: READ Latency (AL = 5, CL = 6) ....................................................................................................... 141

Figure 55: Mode Register 2 (MR2) Definition ................................................................................................. 142

Figure 56: CAS WRITE Latency ...................................................................................................................... 143

Figure 57: Mode Register 3 (MR3) Definition ................................................................................................. 145

Figure 58: MPR Block Diagram ...................................................................................................................... 146

Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 148

Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 149

Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 150

Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 151

Figure 63: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 153

Figure 64: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 154

Figure 65: Example: tFAW ............................................................................................................................. 155

Figure 66: READ Latency .............................................................................................................................. 156

Figure 67: Consecutive READ Bursts (BL8) .................................................................................................... 158

Figure 68: Consecutive READ Bursts (BC4) .................................................................................................... 158

Figure 69: Nonconsecutive READ Bursts ....................................................................................................... 159

Figure 70: READ (BL8) to WRITE (BL8) .......................................................................................................... 159

Figure 71: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 160

Figure 72: READ to PRECHARGE (BL8) .......................................................................................................... 160

Figure 73: READ to PRECHARGE (BC4) ......................................................................................................... 161

Figure 74: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 161

Figure 75: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 161

Figure 76: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 163

Figure 77: Data Strobe Timing – READs ......................................................................................................... 164

Figure 78: Method for Calculating tLZ and tHZ ............................................................................................... 165

Figure 79: tRPRE Timing ............................................................................................................................... 165

Figure 80: tRPST Timing ............................................................................................................................... 166

Figure 81: tWPRE Timing .............................................................................................................................. 168

Figure 82: tWPST Timing .............................................................................................................................. 168

Figure 83: WRITE Burst ................................................................................................................................ 169

Figure 84: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 170

Figure 85: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 170

Figure 86: Nonconsecutive WRITE to WRITE ................................................................................................. 171

Figure 87: WRITE (BL8) to READ (BL8) .......................................................................................................... 171

Figure 88: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 172

Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 173

Figure 90: WRITE (BL8) to PRECHARGE ........................................................................................................ 174

Figure 91: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 174

Figure 92: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 175

Figure 93: Data Input Timing ........................................................................................................................ 176

Figure 94: Self Refresh Entry/Exit Timing ...................................................................................................... 178

Figure 95: Active Power-Down Entry and Exit ................................................................................................ 182

Figure 96: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 183

Figure 97: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 183

Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 184

Figure 99: Power-Down Entry After WRITE .................................................................................................... 184

Figure 100: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 185

Figure 101: REFRESH to Power-Down Entry .................................................................................................. 185

Figure 102: ACTIVATE to Power-Down Entry ................................................................................................. 186

2Gb: x4, x8, x16 DDR3 SDRAM

Features

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Figure 103: PRECHARGE to Power-Down Entry ............................................................................................. 186

Figure 104: MRS Command to Power-Down Entry ......................................................................................... 187

Figure 105: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 187

Figure 106: RESET Sequence ......................................................................................................................... 189

Figure 107: On-Die Termination ................................................................................................................... 190

Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 195

Figure 109: Dynamic ODT: Without WRITE Command .................................................................................. 195

Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 196

Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 197

Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 197

Figure 113: Synchronous ODT ...................................................................................................................... 199

Figure 114: Synchronous ODT (BC4) ............................................................................................................. 200

Figure 115: ODT During READs .................................................................................................................... 202

Figure 116: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 204

Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 206

Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 208

Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 210

Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 210

2Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 1

Table 2: Addressing ......................................................................................................................................... 2

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 18

Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 20

Table 5: Absolute Maximum Ratings .............................................................................................................. 26

Table 6: DDR3 Input/Output Capacitance ...................................................................................................... 27

Table 7: Thermal Characteristics .................................................................................................................... 28

Table 8: Timing Parameters Used for IDD Measurements – Clock Units ............................................................ 30

Table 9: IDD0 Measurement Loop ................................................................................................................... 31

Table 10: IDD1 Measurement Loop .................................................................................................................. 32

Table 11: IDD Measurement Conditions for Power-Down Currents ................................................................... 33

Table 12: IDD2N and IDD3N Measurement Loop ................................................................................................ 34

Table 13: IDD2NT Measurement Loop .............................................................................................................. 34

Table 14: IDD4R Measurement Loop ................................................................................................................ 35

Table 15: IDD4W Measurement Loop ............................................................................................................... 36

Table 16: IDD5B Measurement Loop ................................................................................................................ 37

Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 .................................................................... 38

Table 18: IDD7 Measurement Loop .................................................................................................................. 39

Table 19: IDD Maximum Limits – Die Rev D ..................................................................................................... 41

Table 20: IDD Maximum Limits – Die Rev M .................................................................................................... 42

Table 21: IDD Maximum Limits – Die Rev K ..................................................................................................... 43

Table 22: DC Electrical Characteristics and Operating Conditions ................................................................... 44

Table 23: DC Electrical Characteristics and Input Conditions .......................................................................... 44

Table 24: Input Switching Conditions ............................................................................................................. 45

Table 25: Control and Address Pins ................................................................................................................ 47

Table 26: Clock, Data, Strobe, and Mask Pins .................................................................................................. 47

Table 27: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .................................................. 48

Table 28: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS# ............................................... 50

Table 29: Single-Ended Input Slew Rate Definition .......................................................................................... 51

Table 30: Differential Input Slew Rate Definition ............................................................................................. 53

Table 31: On-Die Termination DC Electrical Characteristics ............................................................................ 54

Table 32: RTT Effective Impedances ................................................................................................................ 55

Table 33: ODT Sensitivity Definition .............................................................................................................. 56

Table 34: ODT Temperature and Voltage Sensitivity ........................................................................................ 56

Table 35: ODT Timing Definitions .................................................................................................................. 57

Table 36: Reference Settings for ODT Timing Measurements ........................................................................... 57

Table 37: 34 Ohm Driver Impedance Characteristics ....................................................................................... 61

Table 38: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ....................................................... 62

Table 39: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V ................................................................ 62

Table 40: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V ............................................................. 62

Table 41: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V ............................................................. 63

Table 42: 34 Ohm Output Driver Sensitivity Definition .................................................................................... 63

Table 43: 34 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 63

Table 44: 40 Ohm Driver Impedance Characteristics ....................................................................................... 64

Table 45: 40 Ohm Output Driver Sensitivity Definition .................................................................................... 64

Table 46: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 65

Table 47: Single-Ended Output Driver Characteristics ..................................................................................... 66

Table 48: Differential Output Driver Characteristics ........................................................................................ 67

Table 49: Single-Ended Output Slew Rate Definition ....................................................................................... 69

Table 50: Differential Output Slew Rate Definition .......................................................................................... 70

2Gb: x4, x8, x16 DDR3 SDRAM

Features

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2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 51: DDR3-1066 Speed Bins ................................................................................................................... 71

Table 52: DDR3-1333 Speed Bins ................................................................................................................... 72

Table 53: DDR3-1600 Speed Bins ................................................................................................................... 73

Table 54: DDR3-1866 Speed Bins ................................................................................................................... 74

Table 55: DDR3-2133 Speed Bins ................................................................................................................... 75

Table 56: Electrical Characteristics and AC Operating Conditions .................................................................... 76

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 86

Table 58: Command and Address Setup and Hold Values Referenced – AC/DC-Based ...................................... 96

Table 59: Derating Values for tIS/tIH – AC175/DC100-Based ............................................................................ 97

Table 60: Derating Values for tIS/tIH – AC150/DC100-Based ............................................................................ 97

Table 61: Derating Values for tIS/tIH – AC135/DC100-Based ............................................................................ 98

Table 62: Derating Values for tIS/tIH – AC125/DC100-Based ............................................................................ 98

Table 63: Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition ............................... 99

Table 64: DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ......................... 104

Table 65: Derating Values for tDS/tDH – AC175/DC100-Based ........................................................................ 105

Table 66: Derating Values for tDS/tDH – AC150/DC100-Based ........................................................................ 105

Table 67: Derating Values for tDS/tDH – AC135/DC100-Based at 1V/ns ........................................................... 106

Table 68: Derating Values for tDS/tDH – AC135/DC100-Based at 2V/ns ........................................................... 107

Table 69: Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition ......................... 108

Table 70: Truth Table – Command ................................................................................................................. 113

Table 71: Truth Table – CKE .......................................................................................................................... 115

Table 72: READ Command Summary ............................................................................................................ 117

Table 73: WRITE Command Summary .......................................................................................................... 117

Table 74: READ Electrical Characteristics, DLL Disable Mode ......................................................................... 123

Table 75: Write Leveling Matrix ..................................................................................................................... 127

Table 76: Burst Order .................................................................................................................................... 136

Table 77: MPR Functional Description of MR3 Bits ........................................................................................ 146

Table 78: MPR Readouts and Burst Order Bit Mapping ................................................................................... 147

Table 79: Self Refresh Temperature and Auto Self Refresh Description ............................................................ 179

Table 80: Self Refresh Mode Summary ........................................................................................................... 179

Table 81: Command to Power-Down Entry Parameters .................................................................................. 180

Table 82: Power-Down Modes ....................................................................................................................... 181

Table 83: Truth Table – ODT (Nominal) ......................................................................................................... 191

Table 84: ODT Parameters ............................................................................................................................ 191

Table 85: Write Leveling with Dynamic ODT Special Case .............................................................................. 192

Table 86: Dynamic ODT Specific Parameters ................................................................................................. 193

Table 87: Mode Registers for RTT,nom ............................................................................................................. 193

Table 88: Mode Registers for RTT(WR) ............................................................................................................. 194

Table 89: Timing Diagrams for Dynamic ODT ................................................................................................ 194

Table 90: Synchronous ODT Parameters ........................................................................................................ 199

Table 91: Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 204

Table 92: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................... 206

2Gb: x4, x8, x16 DDR3 SDRAM

Features

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State Diagram

Figure 2: Simplified State Diagram

SRX = Self refresh exit

WRITE = WR, WRS4, WRS8

WRITE AP = WRAP, WRAPS4, WRAPS8

ZQCL = ZQ LONG CALIBRATION

ZQCS = ZQ SHORT CALIBRATION

Bank

active

ReadingWriting

Activating

Refreshing

Self

refresh

Idle

Active

power-

down

calibration

From any

state

Power

applied Reset

procedure

Power

Initial-

ization

MRS, MPR,

write

leveling

Precharge

power-

down

Writing Reading

Automatic

sequence

Command

sequence

Precharging

READ

READ READ

READ AP

PRE, PREA

PRE, PREA PRE, PREA

WRITE

CKE L CKE L

CKE L

WRITE

WRITE AP

PDE

PDX

SRX

SRE

REF

MRS

ACT

RESET

ZQCL

ZQCL/ZQCS

ACT = ACTIVATE

MPR = Multipurpose register

MRS = Mode register set

PDE = Power-down entry

PDX = Power-down exit

PRE = PRECHARGE

PREA = PRECHARGE ALL

READ = RD, RDS4, RDS8

READ AP = RDAP, RDAPS4, RDAPS8

REF = REFRESH

RESET = START RESET PROCEDURE

SRE = Self refresh entry

2Gb: x4, x8, x16 DDR3 SDRAM

State Diagram

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Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.

The double data rate architecture is an 8n-prefetch architecture with an interface de-

signed to transfer two data words per clock cycle at the I/O pins. A single read or write

operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-

cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-

half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data

for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the

data strobes.

The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK

going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com-

mand, and address signals are registered at every positive edge of CK. Input data is reg-

istered on the first rising edge of DQS after the WRITE preamble, and output data is ref-

erenced on the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se-

lected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVATE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVATE command are used to select the bank and row to be accessed. The ad-

dress bits registered coincident with the READ or WRITE commands are used to select

the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM

allows for concurrent operation, thereby providing high bandwidth by hiding row pre-

charge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed

–40°C or 95°C. JEDEC specifications require the refresh rate to double when TC exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,

ODT resistance and the input/output impedance must be derated when TC is < 0°C or

>95°C.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation).

• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be

interpreted as any and all DQ collectively, unless specifically stated otherwise.

• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as

DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.

2Gb: x4, x8, x16 DDR3 SDRAM

Functional Description

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.

• Complete functionality may be described throughout the document; any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

• Any specific requirement takes precedence over a general statement.

• Any functionality not specifically stated is considered undefined, illegal, and not sup-

ported, and can result in unknown operation.

• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,

x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,

x8).

• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a

single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer

to the Dynamic ODT Special Use Case section.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1kΩ* resistor.

– Connect UDQS# to VDD via 1kΩ* resistor.

– Connect UDM to VDD via 1kΩ* resistor.

– Connect DQ[15:8] individually to either VSS, VDD, or VREF via 1kΩ resistors,* or float

DQ[15:8].

*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.

2Gb: x4, x8, x16 DDR3 SDRAM

Functional Description

PDF: 09005aef826aaadc

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Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally

configured as an 8-bank DRAM.

Figure 3: 512 Meg x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

Address

256

(x32)

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(32,768 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To pullup/pulldown

networks

READ

drivers DQ[3:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

CK,CK#

DQS, DQS#

ODT

control

ZQ CAL

WE#

RZQ

CK, CK#

RAS#

CAS#

CS#

ODT

CKE

RESET#

CK,CK#

DLL

DQ[3:0]

(1 . . . 4)

(1, 2)

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

BC4

BC4 (burst chop)

BC4

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

A12

VSSQ

OTF

2Gb: x4, x8, x16 DDR3 SDRAM

Functional Block Diagrams

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Figure 4: 256 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

Memory

array

(32,768 x 128 x 64)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

Read

drivers DQ[7:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

DM/TDQS

(shared pin)

TDQS#

CK, CK#

DQS/DQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

SW1 SW2

VDDQ/2

RTT(WR)

RTT,nom

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

BC4 (burst chop)

BC4

Write

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128

x64)

ODT

control

Address

A12

VSSQ

OTF

Figure 5: 128 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

SW1 SW2

VDDQ/2

BC4

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

SW1 SW2

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

VSSQ A12

OTF

VDDQ/2

RTT,nom RTT(WR)

RTT(WR)

RTT,nom

2Gb: x4, x8, x16 DDR3 SDRAM

Functional Block Diagrams

PDF: 09005aef826aaadc

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Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 (Top View)

1234 67895

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

VDD

VSSQ

DQ2

NF, DQ6

VDDQ

VSS

VDD

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

VDD

NF, DQ7

CK#

A10/AP

A12/BC#

A11

A14

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

VSSQ

DQ3

VSS

NF, DQ5

VSS

VDD

VREFCA

BA1

Notes: 1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

2Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 7: 96-Ball FBGA – x16 (Top View)

1234 67895

VDDQ

VSSQ

VDDQ

VSSQ

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

DQ13

VDD

DQ11

VDDQ

VSSQ

DQ2

DQ6

VDDQ

VSS

VDD

CS#

BA0

RESET#

DQ15

VSS

DQ9

UDM

DQ0

LDQS

LDQS#

DQ4

RAS#

CAS#

WE#

BA2

A13

DQ12

UDQS#

UDQS

DQ8

LDM

DQ1

VDD

DQ7

CK#

A10/AP

A12/BC#

A11

VDDQ

DQ14

DQ10

VSSQ

DQ3

VSS

DQ5

VSS

VDD

VREFCA

BA1

VSS

VSSQ

VDDQ

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

Note: 1. Ball descriptions listed in Table 4 (page 20).

2Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[14:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 113).

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to VREFCA.

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-

pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE

LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks

idle), or active power-down (row active in any bank). CKE is synchronous for power-

down entry and exit and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during

POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF

REFRESH. CKE is referenced to VREFCA.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to VREFCA.

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.

Although the DM ball is input-only, the DM loading is designed to match that of the

DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on

the x8.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is

ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to VREFCA.

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and

DC LOW ≤ 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous.

2Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aaadc

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Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol Type Description

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are

referenced to VREFDQ.

DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are

referenced to VREFDQ.

DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data.

TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is

enabled, DM is disabled, and the TDQS and TDQS# balls provide termination

resistance.

VDD Supply Power supply: 1.5V ±0.075V.

VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

VREFCA Supply Reference voltage for control, command, and address: VREFCA must be

maintained at all times (including self refresh) for proper device operation.

VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self

refresh) for proper device operation.

VSS Supply Ground.

VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

ZQ Reference External reference ball for output drive calibration: This ball is tied to external

240Ω resistor RZQ, which is tied to VSSQ.

NC – No connect: These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

NF – No function: When configured as a x4 device, these balls are NF. When configured

as a x8 device, these balls are defined as TDQS#, DQ[7:4].

2Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A13, A12/BC#, A11,

A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank (A10

LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also pro-

vide the op-code during a LOAD MODE command. Address inputs are referenced to

VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ

and WRITE commands to determine whether burst chop (on-the-fly) will be performed

(HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 113).

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,

or PRECHARGE command is being applied. BA[2:0] define which mode

are referenced to VREFCA.

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of CK#.

Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-

pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW

provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or

active power-down (row active in any bank). CKE is synchronous for

power-down entry and exit and for self refresh entry. CKE is asynchronous for self re-

fresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during

POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF RE-

FRESH. CKE is referenced to VREFCA.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the com-

mand decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to VREFCA.

LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte

input data is masked when LDM is sampled HIGH along with the input data during a

write access. Although the LDM ball is input-only, the LDM loading is designed to

match that of the DQ and DQS balls. LDM is referenced to VREFDQ.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#,

UDQS, UDQS#, LDM, and UDM. The ODT input is ignored if disabled via the LOAD

MODE command. ODT is referenced to VREFCA.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to VREFCA.

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC

LOW ≤ 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous.

2Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)

Symbol Type Description

UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte

input data is masked when UDM is sampled HIGH along with that input data during a

WRITE access. Although the UDM ball is input-only, the UDM loading is designed to

match that of the DQ and DQS balls. UDM is referenced to VREFDQ.

DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration.

DQ[7:0] are referenced to VREFDQ.

DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration.

DQ[15:8] are referenced to VREFDQ.

LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input

with write data. Center-aligned to write data.

UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input

with write data. DQS is center-aligned to write data.

VDD Supply Power supply: 1.5V ±0.075V.

VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity.

VREFCA Supply Reference voltage for control, command, and address: VREFCA must be main-

tained at all times (including self refresh) for proper device operation.

VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self

refresh) for proper device operation.

VSS Supply Ground.

VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

ZQ Reference External reference ball for output drive calibration: This ball is tied to external

240Ω resistor RZQ, which is tied to VSSQ.

NC – No connect: These balls should be left unconnected (the ball has no connection to the

DRAM or to other balls).

2Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

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Package Dimensions

Figure 8: 78-Ball FBGA – x4, x8 (DA)

Ball A1 ID

1.2 MAX

0.25 MIN

8 ±0.1

Ball A1 ID

78X Ø0.45

Dimensions

apply to solder

balls post-reflow

on Ø0.35 SMD

ball pads.

0.8 TYP

9.6 CTR 10.5 ±0.1

0.8 ±0.05

0.155

1.8 CTR

Nonconductive overmold

0.12 A A

Seating

Plane

6.4 CTR

9 8 7 3 2 1

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

2Gb: x4, x8, x16 DDR3 SDRAM

Package Dimensions

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Figure 9: 78-Ball FBGA – x4, x8 (HX)

0.8 TYP

9.6 CTR

11.5 ±0.1

0.8 TYP

6.4 CTR

9 ±0.1

Ball A1 ID

123789

78X Ø0.45

Dimensions

apply to solder

balls post-reflow

on Ø0.35 SMD

ball pads.

A 0.12 A

Seating plane

1.1 ±0.1

0.25 MIN

1.8 CTR

Nonconductive

overmold

0.155

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

2Gb: x4, x8, x16 DDR3 SDRAM

Package Dimensions

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Figure 10: 96-Ball FBGA – x16 (HA)

Ball A1 Index

Dimensions

apply to solder

balls post-reflow

on Ø0.35 SMD

ball pads.

14 ±0.1

0.8 TYP

1.1 ±0.1

12 CTR

Ball A1 Index

(covered by SR)

0.8 TYP

9 ±0.1

0.25 MIN6.4 CTR

96X Ø0.45

9 8 7 3 2 1

A 0.12 A

Seating plane

1.8 CTR

Nonconductive

overmold

0.155

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

2Gb: x4, x8, x16 DDR3 SDRAM

Package Dimensions

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Figure 11: 96-Ball FBGA – x16 (JT)

Seating plane

0.12 A

123789

Ball A1 ID Ball A1 ID

0.25 MIN

1.1 ±0.1

0.8 TYP

6.4 CTR

8 ±0.1

0.8 TYP

12 CTR

14 ±0.1

96X Ø0.45

Dimensions apply

to solder balls post-

reflow on Ø0.35

SMD ball pads.

0.155

1.8 CTR

Nonconductive

overmold

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

2Gb: x4, x8, x16 DDR3 SDRAM

Package Dimensions

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Electrical Specifications

Absolute Ratings

Stresses greater than those listed in Table 5 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other

conditions outside those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for extended periods

may adversely affect reliability.

Table 5: Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

VDD VDD supply voltage relative to VSS –0.4 1.975 V 1

VDDQ VDD supply voltage relative to VSSQ –0.4 1.975 V

VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V

TCOperating case temperature - Commercial 0 95 °C 2, 3

Operating case temperature - Industrial –40 95 °C 2, 3

Operating case temperature - Automotive –40 105 °C 2, 3

TSTG Storage temperature –55 150 °C

Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be

greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be ≤300mV.

2. MAX operating case temperature. TC is measured in the center of the package.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-

ing operation.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications

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Input/Output Capacitance

Table 6: DDR3 Input/Output Capacitance

Note 1 applies to the entire table

Capacitance

Parameters Symbol

800 1066 1333 1600 1866 2133

Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max

CK and CK# CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF

ΔC: CK to CK# CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF

Single-end I/O:

DQ, DM

CIO 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF 2

Differential I/O:

DQS, DQS#,

TDQS, TDQS#

CIO 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF 3

ΔC: DQS to

DQS#, TDQS,

TDQS#

CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 0 0.15 pF 3

ΔC: DQ to DQS CDIO –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 pF 4

Inputs (CTRL,

CMD, ADDR)

CI0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF 5

ΔC: CTRL to CK CDI_CTRL –0.5 0.3 –0.5 0.3 –0.4 0.2 –0.4 0.2 –0.4 0.2 –0.4 0.2 pF 6

ΔC: CMD_ADDR

to CK

CDI_CMD_

ADDR

–0.5 0.5 –0.5 0.5 –0.4 0.4 –0.4 0.4 –0.4 0.4 –0.4 0.4 pF 7

ZQ pin capaci-

tance

CZQ – 3.0 – 3.0 – 3.0 – 3.0 – 3.0 – 3.0 pF

Reset pin capaci-

tance

CRE – 3.0 – 3.0 – 3.0 – 3.0 – 3.0 – 3.0 pF

Notes: 1. VDD = 1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5 ×

VDDQ, VOUT = 0.1V (peak-to-peak).

2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.

3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.

4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).

5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =

A[n:0], BA[2:0].

6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).

7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications

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Thermal Characteristics

Table 7: Thermal Characteristics

Parameter/Condition Value Unit Symbol Notes

Operating case temperature –

Commercial

0 to +85 °C TC1, 2, 3

0 to +95 °C TC1, 2, 3, 4

Operating case temperature –

Industrial

–40 to +85 °C TC1, 2, 3

–40 to +95 °C TC1, 2, 3, 4

Operating case temperature –

Automotive

–40 to +85 °C TC1, 2, 3

–40 to +105 °C TC1, 2, 3, 4

Junction-to-case

(TOP)

96-ball (JT) 6.5 °C/W ΘJC 5

96-ball (HA) 3.9

78-ball (DA) M, K 6.5

78-ball (HX) 3.9

Notes: 1. Maximum operating case temperature. TC is measured in the center of the package.

2. A thermal solution must be designed to ensure the DRAM device does not exceed TC

MAX during operation.

3. Device functionality is not guaranteed if the DRAM device exceeds TC MAX during oper-

ation.

4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs

interval refresh rate. The use of SRT or ASR (if available) must be enabled.

5. Thermal resistance data is based on a number of samples from multiple lots and should

be viewed as a typical number.

2Gb: x4, x8, x16 DDR3 SDRAM

Thermal Characteristics

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Figure 12: Thermal Measurement Point

/

:

7FWHVWSRLQW

2Gb: x4, x8, x16 DDR3 SDRAM

Thermal Characteristics

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Electrical Specifications – IDD Specifications and Conditions

Within the following IDD measurement tables, the following definitions and conditions

are used, unless stated otherwise:

• LOW: VIN ≤ V IL(AC)max; HIGH: VIN ≥ V IH(AC)min.

• Midlevel: Inputs are VREF = VDD/2.

•R

ON set to RZQ/7 (34Ω

•R

TT,nom set to RZQ/6 (40Ω

•R

TT(WR) set to RZQ/2 (120Ω

•Q

OFF is enabled in MR1.

• ODT is enabled in MR1 (RTT,nom) and MR2 (RTT(WR)).

• TDQS is disabled in MR1.

• External DQ/DQS/DM load resistor is 25Ω to VDDQ/2.

• Burst lengths are BL8 fixed.

• AL equals 0 (except in IDD7).

•I

DD specifications are tested after the device is properly initialized.

• Input slew rate is specified by AC parametric test conditions.

• Optional ASR is disabled.

• Read burst type uses nibble sequential (MR0[3] = 0).

• Loop patterns must be executed at least once before current measurements begin.

Table 8: Timing Parameters Used for IDD Measurements – Clock Units

IDD

Parameter

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133

Unit

-25E -25 -187E -187 -15E -15 -125E -125 -107 -093

5-5-5 6-6-6 7-7-7 8-8-8 9-9-9 10-10-10 10-10-10 11-11-11 13-13-13 14-14-14

tCK (MIN) IDD 2.5 1.875 1.5 1.25 1.071 0.938 ns

CL IDD 56789 10 10 11 13 14 CK

tRCD (MIN) IDD 5 6 7 8 9 10 10 11 13 14 CK

tRC (MIN) IDD 20 21 27 28 33 34 38 39 45 50 CK

tRAS (MIN) IDD 15 15 20 20 24 24 28 28 32 36 CK

tRP (MIN) 5 6 7 8 9 10 10 11 13 14 CK

tFAW x4, x8 16 16 20 20 20 20 24 24 26 27 CK

x16 20 20 27 27 30 30 32 32 33 38 CK

tRRD

IDD

x4, x8 4 4 4 4 4 4 5 5 5 6 CK

x16 4 4 6 6 5 5 6 6 6 7 CK

tRFC 1Gb 44 44 59 59 74 74 88 88 103 118 CK

2Gb 64 64 86 86 107 107 128 128 150 172 CK

4Gb 104 104 139 139 174 174 208 208 243 279 CK

8Gb 140 140 187 187 234 234 280 280 328 375 CK

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 9: IDD0 Measurement Loop

CK, CK#

CKE

Sub-

Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

Toggling

Static HIGH

0 ACT 00110000000 –

1 D 10000000000 –

2 D 10000000000 –

3 D# 11110000000 –

4 D# 11110000000 –

Repeat cycles 1 through 4 until nRAS - 1; truncate if needed

nRAS PRE 00100000000 –

Repeat cycles 1 through 4 until nRC - 1; truncate if needed

nRC ACT 001100000F0 –

nRC + 1 D 100000000F0 –

nRC + 2 D 100000000F0 –

nRC + 3 D# 111100000F0 –

nRC + 4 D# 111100000F0 –

Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1; truncate if needed

nRC + nRAS PRE 001000000F0 –

Repeat cycles nRC + 1 through nRC + 4 until 2 × RC - 1; truncate if needed

1 2 × nRC Repeat sub-loop 0, use BA[2:0] = 1

2 4 × nRC Repeat sub-loop 0, use BA[2:0] = 2

3 6 × nRC Repeat sub-loop 0, use BA[2:0] = 3

4 8 × nRC Repeat sub-loop 0, use BA[2:0] = 4

5 10 × nRC Repeat sub-loop 0, use BA[2:0] = 5

6 12 × nRC Repeat sub-loop 0, use BA[2:0] = 6

7 14 × nRC Repeat sub-loop 0, use BA[2:0] = 7

Notes: 1. DQ, DQS, DQS# are midlevel.

2. DM is LOW.

3. Only selected bank (single) active.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 10: IDD1 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data2

Toggling

Static HIGH

0 ACT 00110000000 –

1 D 10000000000 –

2 D 10000000000 –

3 D# 11110000000 –

4 D# 11110000000 –

Repeat cycles 1 through 4 until nRCD - 1; truncate if needed

nRCD RD 0 1 0 1 0 0 0 0 0 0 0 00000000

Repeat cycles 1 through 4 until nRAS - 1; truncate if needed

nRAS PRE 00100000000 –

Repeat cycles 1 through 4 until nRC - 1; truncate if needed

nRC ACT 001100000F0 –

nRC + 1 D 100000000F0 –

nRC + 2 D 100000000F0 –

nRC + 3 D# 111100000F0 –

nRC + 4 D# 111100000F0 –

Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1; truncate if needed

nRC + nRCD RD 0 1 0 1 0 0 0 0 0 F 0 00110011

Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1; truncate if needed

nRC + nRAS PRE 001000000F0 –

Repeat cycle nRC + 1 through nRC + 4 until 2 × nRC - 1; truncate if needed

1 2 × nRC Repeat sub-loop 0, use BA[2:0] = 1

2 4 × nRC Repeat sub-loop 0, use BA[2:0] = 2

3 6 × nRC Repeat sub-loop 0, use BA[2:0] = 3

4 8 × nRC Repeat sub-loop 0, use BA[2:0] = 4

5 10 × nRC Repeat sub-loop 0, use BA[2:0] = 5

6 12 × nRC Repeat sub-loop 0, use BA[2:0] = 6

7 14 × nRC Repeat sub-loop 0, use BA[2:0] = 7

Notes: 1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.

2. DM is LOW.

3. Burst sequence is driven on each DQ signal by the RD command.

4. Only selected bank (single) active.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 11: IDD Measurement Conditions for Power-Down Currents

Name

IDD2P0 Precharge

Power-Down

Current (Slow Exit)1

IDD2P1 Precharge

Power-Down

Current (Fast Exit)1

IDD2Q Precharge

Quiet

Standby Current

IDD3P Active

Power-Down

Current

Timing pattern N/A N/A N/A N/A

CKE LOW LOW HIGH LOW

External clock Toggling Toggling Toggling Toggling

tCK tCK (MIN) IDD tCK (MIN) IDD tCK (MIN) IDD tCK (MIN) IDD

tRC N/A N/A N/A N/A

tRAS N/A N/A N/A N/A

tRCD N/A N/A N/A N/A

tRRD N/A N/A N/A N/A

tRC N/A N/A N/A N/A

CL N/A N/A N/A N/A

AL N/A N/A N/A N/A

CS# HIGH HIGH HIGH HIGH

Command inputs LOW LOW LOW LOW

Row/column addr LOW LOW LOW LOW

Bank addresses LOW LOW LOW LOW

DM LOW LOW LOW LOW

Data I/O Midlevel Midlevel Midlevel Midlevel

Output buffer DQ, DQS Enabled Enabled Enabled Enabled

ODT2Enabled, off Enabled, off Enabled, off Enabled, off

Burst length 8 8 8 8

Active banks None None None All

Idle banks All All All None

Special notes N/A N/A N/A N/A

Notes: 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast

exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).

2. “Enabled, off” means the MR bits are enabled, but the signal is LOW.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 12: IDD2N and IDD3N Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

Toggling

Static HIGH

0 D 10000000000 –

1 D 10000000000 –

2 D# 111100000F0 –

3 D# 111100000F0 –

1 4–7 Repeat sub-loop 0, use BA[2:0] = 1

2 8–11 Repeat sub-loop 0, use BA[2:0] = 2

3 12–15 Repeat sub-loop 0, use BA[2:0] = 3

4 16–19 Repeat sub-loop 0, use BA[2:0] = 4

5 20–23 Repeat sub-loop 0, use BA[2:0] = 5

6 24–27 Repeat sub-loop 0, use BA[2:0] = 6

7 28–31 Repeat sub-loop 0, use BA[2:0] = 7

Notes: 1. DQ, DQS, DQS# are midlevel.

2. DM is LOW.

3. All banks closed during IDD2N; all banks open during IDD3N.

Table 13: IDD2NT Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

Toggling

Static HIGH

0 D 10000000000 –

1 D 10000000000 –

2 D# 111100000F0 –

3 D# 111100000F0 –

1 4–7 Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0

2 8–11 Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1

3 12–15 Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1

4 16–19 Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0

5 20–23 Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0

6 24–27 Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1

7 28–31 Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1

Notes: 1. DQ, DQS, DQS# are midlevel.

2. DM is LOW.

3. All banks closed.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 14: IDD4R Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static HIGH

0 RD 0 1 0 1 0 0 0 0 0 0 0 00000000

1 D 10000000000 –

2 D# 11110000000 –

3 D# 11110000000 –

4 RD 0 1 0 1 0 0 0 0 0 F 0 00110011

5 D 100000000F0 –

6 D# 111100000F0 –

7 D# 111100000F0 –

1 8–15 Repeat sub-loop 0, use BA[2:0] = 1

2 16–23 Repeat sub-loop 0, use BA[2:0] = 2

3 24–31 Repeat sub-loop 0, use BA[2:0] = 3

4 32–39 Repeat sub-loop 0, use BA[2:0] = 4

5 40–47 Repeat sub-loop 0, use BA[2:0] = 5

6 48–55 Repeat sub-loop 0, use BA[2:0] = 6

7 56–63 Repeat sub-loop 0, use BA[2:0] = 7

Notes: 1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.

2. DM is LOW.

3. Burst sequence is driven on each DQ signal by the RD command.

4. All banks open.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 15: IDD4W Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static HIGH

0 WR 0 1 0 0 1 0 0 0 0 0 0 00000000

1 D 10001000000 –

2 D# 11111000000 –

3 D# 11111000000 –

4 WR 0 1 0 0 1 0 0 0 0 F 0 00110011

5 D 100010000F0 –

6 D# 111110000F0 –

7 D# 111110000F0 –

1 8–15 Repeat sub-loop 0, use BA[2:0] = 1

2 16–23 Repeat sub-loop 0, use BA[2:0] = 2

3 24–31 Repeat sub-loop 0, use BA[2:0] = 3

4 32–39 Repeat sub-loop 0, use BA[2:0] = 4

5 40–47 Repeat sub-loop 0, use BA[2:0] = 5

6 48–55 Repeat sub-loop 0, use BA[2:0] = 6

7 56–63 Repeat sub-loop 0, use BA[2:0] = 7

Notes: 1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.

2. DM is LOW.

3. Burst sequence is driven on each DQ signal by the WR command.

4. All banks open.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 16: IDD5B Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

Toggling

Static HIGH

0 0 REF 00010000000 –

1 D 10000000000 –

2 D 10000000000 –

3 D# 111100000F0 –

4 D# 111100000F0 –

1b 5–8 Repeat sub-loop 1a, use BA[2:0] = 1

1c 9–12 Repeat sub-loop 1a, use BA[2:0] = 2

1d 13–16 Repeat sub-loop 1a, use BA[2:0] = 3

1e 17–20 Repeat sub-loop 1a, use BA[2:0] = 4

1f 21–24 Repeat sub-loop 1a, use BA[2:0] = 5

1g 25–28 Repeat sub-loop 1a, use BA[2:0] = 6

1h 29–32 Repeat sub-loop 1a, use BA[2:0] = 7

2 33–nRFC - 1 Repeat sub-loop 1a through 1h until nRFC - 1; truncate if needed

Notes: 1. DQ, DQS, DQS# are midlevel.

2. DM is LOW.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8

IDD Test

IDD6: Self Refresh Current

Normal Temperature Range

TC = 0°C to +85°C

IDD6ET: Self Refresh Current

Extended Temperature Range

TC = 0°C to +95°C IDD8: Reset2

CKE LOW LOW Midlevel

External clock Off, CK and CK# = LOW Off, CK and CK# = LOW Midlevel

tCK N/A N/A N/A

tRC N/A N/A N/A

tRAS N/A N/A N/A

tRCD N/A N/A N/A

tRRD N/A N/A N/A

tRC N/A N/A N/A

CL N/A N/A N/A

AL N/A N/A N/A

CS# Midlevel Midlevel Midlevel

Command inputs Midlevel Midlevel Midlevel

Row/column addresses Midlevel Midlevel Midlevel

Bank addresses Midlevel Midlevel Midlevel

Data I/O Midlevel Midlevel Midlevel

Output buffer DQ, DQS Enabled Enabled Midlevel

ODT1Enabled, midlevel Enabled, midlevel Midlevel

Burst length N/A N/A N/A

Active banks N/A N/A None

Idle banks N/A N/A All

SRT Disabled (normal) Enabled (extended) N/A

ASR Disabled Disabled N/A

Notes: 1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel.

2. During a cold boot RESET (initialization), current reading is valid after power is stable

and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current

reading is valid after RESET has been LOW for 200ns + tRFC.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 18: IDD7 Measurement Loop

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static HIGH

0 ACT00110000000 –

1 RDA0101000100000000000

2 D10000000000 –

3 Repeat cycle 2 until nRRD - 1

nRRD ACT001101000F0 –

nRRD + 1 RDA 010101010F000110011

nRRD + 2 D 100001000F0 –

nRRD + 3 Repeat cycle nRRD + 2 until 2 × nRRD - 1

2 2 × nRRD Repeat sub-loop 0, use BA[2:0] = 2

3 3 × nRRD Repeat sub-loop 1, use BA[2:0] = 3

44 × nRRD D 100003000F0 –

4 × nRRD + 1 Repeat cycle 4 × nRRD until nFAW - 1, if needed

5nFAW Repeat sub-loop 0, use BA[2:0] = 4

6nFAW + nRRD Repeat sub-loop 1, use BA[2:0] = 5

7nFAW + 2 × nRRD Repeat sub-loop 0, use BA[2:0] = 6

8nFAW + 3 × nRRD Repeat sub-loop 1, use BA[2:0] = 7

9nFAW + 4 × nRRD D 100007000F0 –

nFAW + 4 × nRRD + 1 Repeat cycle nFAW + 4 × nRRD until 2 × nFAW - 1, if needed

2 × nFAW ACT001100000F0 –

2 × nFAW + 1 RDA010100010F000110011

2 × nFAW + 2 D 100000000F0 –

2 × nFAW + 3 Repeat cycle 2 × nFAW + 2 until 2 × nFAW + nRRD - 1

2 × nFAW + nRRD ACT00110100000 –

2 × nFAW + nRRD + 1 RDA 0 101010100000000000

2 × nFAW + nRRD + 2 D 1 0 000100000 –

2 × nFAW + nRRD + 3 Repeat cycle 2 × nFAW + nRRD + 2 until 2 × nFAW + 2 × nRRD - 1

12 2 × nFAW + 2 × nRRD Repeat sub-loop 10, use BA[2:0] = 2

13 2 × nFAW + 3 × nRRD Repeat sub-loop 11, use BA[2:0] = 3

14 2 × nFAW + 4 × nRRD D 10000300000 –

2 × nFAW + 4 × nRRD + 1 Repeat cycle 2 × nFAW + 4 × nRRD until 3 × nFAW - 1, if needed

15 3 × nFAW Repeat sub-loop 10, use BA[2:0] = 4

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Table 18: IDD7 Measurement Loop (Continued)

CK, CK#

CKE

Sub-Loop

Cycle

Number

Command

CS#

RAS#

CAS#

WE#

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static HIGH

16 3 × nFAW + nRRD Repeat sub-loop 11, use BA[2:0] = 5

17 3 × nFAW + 2 × nRRD Repeat sub-loop 10, use BA[2:0] = 6

18 3 × nFAW + 3 × nRRD Repeat sub-loop 11, use BA[2:0] = 7

19 3 × nFAW + 4 × nRRD D 10000700000 –

3 × nFAW + 4 × nRRD + 1 Repeat cycle 3 × nFAW + 4 × nRRD until 4 × nFAW - 1, if needed

Notes: 1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.

2. DM is LOW.

3. Burst sequence is driven on each DQ signal by the RD command.

4. AL = CL-1.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – IDD Specifications and Conditions

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Electrical Characteristics – IDD Specifications

IDD values are for full operating range of voltage and temperature unless otherwise no-

ted.

Table 19: IDD Maximum Limits – Die Rev D

Speed Bin

DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit NotesIDD Width

IDD0 x4 75 85 95 105 mA 1, 2

x8 75 85 95 105 mA

x16 90 100 110 120 mA

IDD1 x4 95 100 105 110 mA 1, 2

x8 95 100 105 110 mA

x16 125 130 135 140 mA

IDD2P0 (Slow) All 12 12 12 12 mA 1, 2

IDD2P1 (Fast) x4, x8 25 30 35 40 mA 1, 2

x16 30 35 40 45 mA

IDD2Q All 30 35 40 45 mA 1, 2

IDD2N All 32 37 42 47 mA 1, 2

IDD2NT x4, x8 40 45 50 55 mA 1, 2

x16 55 60 65 70 mA

IDD3P x4, x8 30 35 40 45 mA 1, 2

x16 35 40 45 50 mA

IDD3N All 35 40 45 50 mA 1, 2

IDD4R x4 125 145 165 185 mA 1, 2

x8 140 160 180 200 mA

x16 200 245 270 295 mA

IDD4W x4 135 155 170 190 mA 1, 2

x8 145 165 185 205 mA

x16 210 255 280 315 mA

IDD5B All 190 200 215 220 mA 1, 2

IDD6 All 12 12 12 12 mA 1, 2, 3

IDD6ET All 15 15 15 15 mA 2, 4

IDD7 x4 335 385 435 485 mA 1, 2

x8 335 385 435 485 mA

x16 375 425 475 525 mA

IDD8 All IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA 1, 2

Notes: 1. TC = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase IDDx by up to an additional 2mA.

3. Restricted to TC MAX = 85°C.

4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics – IDD Specifications

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5. The IDD values must be derated (increased) on IT-option devices when operated outside

the range 0°C ≤ TC ≤ +85°C:

5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must

be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%.

5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B

must be derated by 2%; and IDD2Px must be derated by 30%.

Table 20: IDD Maximum Limits – Die Rev M

Speed Bin

DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit NotesIDD Width

IDD0 All 60 65 70 75 mA 1, 2

IDD1 All 70 75 80 85 mA 1, 2

IDD2P0 (Slow) All 12 12 12 12 mA 1, 2

IDD2P1 (Fast) All 27 32 37 42 mA 1, 2

IDD2Q All 30 35 40 45 mA 1, 2

IDD2N All 33 38 43 48 mA 1, 2

IDD2NT All 35 40 45 50 mA 1, 2

IDD3P All 40 45 50 55 mA 1, 2

IDD3N All 45 50 55 60 mA 1, 2

IDD4R x4 115 126 141 156 mA 1, 2

x8 130 141 156 171 mA

IDD4W x4 100 115 130 145 mA 1, 2

x8 115 130 145 160 mA

IDD5B All 185 190 195 200 mA 1, 2

IDD6 All 12 12 12 12 mA 1, 2, 3

IDD6ET All 15 15 15 15 mA 2, 4

IDD7 All 210 225 240 255 mA 1, 2

IDD8 All IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA 1, 2

Notes: 1. TC = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase IDDx by up to an additional 2mA.

3. Restricted to TC MAX = 85°C.

4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.

5. The IDD values must be derated (increased) on IT-option devices when operated outside

the range 0°C ≤ TC ≤ +85°C:

5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must

be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%.

5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B

must be derated by 2%; and IDD2Px must be derated by 30%.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics – IDD Specifications

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Table 21: IDD Maximum Limits – Die Rev K

Speed Bin

DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit NotesIDD

Widt

IDD0 x4, x8 39 41 42 43 46 mA 1, 2

x16 46 48 49 51 55 mA

IDD1 x4 46 50 52 55 57 mA 1, 2

x8 50 54 56 58 60 mA

x16 62 67 69 72 75 mA

IDD2P0

(Slow)

All 12 12 12 12 12 mA 1, 2

IDD2P1 (Fast) All 15 15 15 15 15 mA 1, 2

IDD2Q All 22 22 22 22 22 mA 1, 2

IDD2N All 23 23 23 23 23 mA 1, 2

IDD2NT x4,x8 29 32 34 36 40 mA 1, 2

x16 33 36 37 39 43 mA

IDD3P All 22 22 22 22 22 mA 1, 2

IDD3N x4,x8 31 33 35 37 40 mA 1, 2

x16 33 36 37 39 43 mA

IDD4R x4 70 84 96 106 120 mA 1, 2

x8 74 88 100 110 125 mA

x16 95 115 135 155 180 mA

IDD4W x4 75 87 99 110 122 mA 1, 2

x8 79 91 103 114 126 mA

x16 107 127 146 164 184 mA

IDD5B All 179 181 182 184 190 mA 1, 2

IDD6 All 12 12 12 12 12 mA 1, 2, 3

IDD6ET All 15 15 15 15 15 mA 2, 4

IDD7 x4, x8 128 157 163 171 190 mA 1, 2

x16 159 179 202 226 248 mA

IDD8 All IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA 1, 2

Notes: 1. TC = 85°C; SRT and ASR are disabled.

2. Enabling ASR could increase IDDx by up to an additional 2mA.

3. Restricted to TC MAX = 85°C.

4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.

5. The IDD values must be derated (increased) on IT-option devices when operated outside

the range 0°C ≤ TC ≤ +85°C:

5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must

be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%.

5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B

must be derated by 2%; and IDD2Px must be derated by 30%.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics – IDD Specifications

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Electrical Specifications – DC and AC

DC Operating Conditions

Table 22: DC Electrical Characteristics and Operating Conditions

All voltages are referenced to VSS

Parameter/Condition Symbol Min Nom Max Unit Notes

Supply voltage VDD 1.425 1.5 1.575 V 1, 2

I/O supply voltage VDDQ 1.425 1.5 1.575 V 1, 2

Input leakage current

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V

(All other pins not under test = 0V)

II–2 – 2 μA

VREF supply leakage current

VREFDQ = VDD/2 or VREFCA = VDD/2

(All other pins not under test = 0V)

IVREF –1 – 1 μA 4

Notes: 1. VDD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ.

2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the

DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC

timing parameters.

3. VREF (see Table 23).

4. The minimum limit requirement is for testing purposes. The leakage current on the VREF

pin should be minimal.

Input Operating Conditions

Table 23: DC Electrical Characteristics and Input Conditions

All voltages are referenced to VSS

Parameter/Condition Symbol Min Nom Max Unit Notes

VIN low; DC/commands/address busses VIL VSS n/a See Table 24 V

VIN high; DC/commands/address busses VIH See Table 24 n/a VDD V

Input reference voltage command/address bus VREFCA(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 1, 2

I/O reference voltage DQ bus VREFDQ(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 2, 3

I/O reference voltage DQ bus in SELF REFRESH VREFDQ(SR) VSS 0.5 × VDD VDD V4

Command/address termination voltage

(system level, not direct DRAM input)

VTT – 0.5 × VDDQ –V5

Notes: 1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC

level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed

±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not ex-

ceed ±2% of VREFCA(DC).

2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifi-

cations if the DRAM induces additional AC noise greater than 20 MHz in frequency.

3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC

level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed

±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not ex-

ceed ±2% of VREFDQ(DC).

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH,

within restrictions outlined in the SELF REFRESH section.

5. VTT is not applied directly to the device. VTT is a system supply for signal termination re-

sistors. Minimum and maximum values are system-dependent.

Table 24: Input Switching Conditions

Parameter/Condition Symbol

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

DDR3-2133 Unit

Command and Address

Input high AC voltage: Logic 1 @ 175mV VIH(AC175)min 175 175 – mV

Input high AC voltage: Logic 1 @ 150mV VIH(AC150)min 150 150 – mV

Input high AC voltage: Logic 1 @ 135 mV VIH(AC135)min – – 135 mV

Input high AC voltage: Logic 1 @ 125 mV VIH(AC125)min – – 125 mV

Input high DC voltage: Logic 1 @ 100 mV VIH(DC100)min 100 100 100 mV

Input low DC voltage: Logic 0 @ –100mV VIL(DC100)max –100 –100 –100 mV

Input low AC voltage: Logic 0 @ –125mV VIL(AC125)max – – –125 mV

Input low AC voltage: Logic 0 @ –135mV VIL(AC135)max – – –135 mV

Input low AC voltage: Logic 0 @ –150mV VIL(AC150)max –150 –150 – mV

Input low AC voltage: Logic 0 @ –175mV VIL(AC175)max –175 –175 – mV

DQ and DM

Input high AC voltage: Logic 1 VIH(AC175)min 175 – – mV

Input high AC voltage: Logic 1 VIH(AC150)min 150 150 – mV

Input high AC voltage: Logic 1 VIH(AC135)min – – 135 mV

Input high DC voltage: Logic 1 VIH(DC100)min 100 100 100 mV

Input low DC voltage: Logic 0 VIL(DC100)max –100 –100 –100 mV

Input low AC voltage: Logic 0 VIL(AC135)max – – –135 mV

Input low AC voltage: Logic 0 VIL(AC150)max –150 –150 – mV

Input low AC voltage: Logic 0 VIL(AC175)max –175 – – mV

Notes: 1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All

slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ

and DM inputs.

2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC).

3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC).

4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is

900mV (peak-to-peak).

5. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is

used, the associated setup time for that AC level must also be used. Additionally, one

VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and

VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/

command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min

with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min

with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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Figure 13: Input Signal

0.575V

0.0V

0.650V

0.720V

0.735V

0.750V

0.765V

0.780V

0.850V

0.925V

VIL(AC)

VIL(DC)

VREF - AC noise

VREF - DC error

VREF + DC error

VREF + AC noise

VIH(DC)

VIH(AC)

1.50V

1.90V

–0.40V

VDDQ

VDDQ + 0.4V narrow

pulse width

VSS - 0.4V narrow

pulse width

VSS

0.575V

0.650V

0.720V

0.735V

0.750V

0.765V

0.780V

0.850V

0.925V

Minimum VIL and VIH levels

VIH(DC)

VIH(AC)

VIL(AC)

VIL(DC)

VIL and VIH levels with ringback

Note: 1. Numbers in diagrams reflect nominal values.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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AC Overshoot/Undershoot Specification

Table 25: Control and Address Pins

Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133

Maximum peak amplitude al-

lowed for overshoot area

(see Figure 14)

0.4V 0.4V 0.4V 0.4V 0.4V 0.4V

Maximum peak amplitude al-

lowed for undershoot area

(see Figure 15)

0.4V 0.4V 0.4V 0.4V 0.4V 0.4V

Maximum overshoot area above

VDD (see Figure 14)

0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns 0.25 Vns

Maximum undershoot area be-

low VSS (see Figure 15)

0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns 0.25 Vns

Table 26: Clock, Data, Strobe, and Mask Pins

Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133

Maximum peak amplitude al-

lowed for overshoot area

(see Figure 14)

0.4V 0.4V 0.4V 0.4V 0.4V 0.4V

Maximum peak amplitude al-

lowed for undershoot area

(see Figure 15)

0.4V 0.4V 0.4V 0.4V 0.4V 0.4V

Maximum overshoot area above

VDD/VDDQ (see Figure 14)

0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns 0.10 Vns

Maximum undershoot area be-

low VSS/VSSQ (see Figure 15)

0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns 0.10 Vns

Figure 14: Overshoot

Maximum amplitude

Overshoot area

VDD/VDDQ

Time (ns)

Volts (V)

Figure 15: Undershoot

Maximum amplitude

Undershoot area

VSS/VSSQ

Time (ns)

Volts (V)

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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Table 27: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)

Parameter/Condition Symbol Min Max Unit Notes

Differential input voltage logic high - slew VIH,diff 200 n/a mV 4

Differential input voltage logic low - slew VIL,diff n/a –200 mV 4

Differential input voltage logic high VIH,diff(AC) 2 × (VIH(AC) - VREF)V

DD/VDDQ mV 5

Differential input voltage logic low VIL,diff(AC) VSS/VSSQ 2 × (VIL(AC)-VREF)mV 6

Differential input crossing voltage relative

to VDD/2 for DQS, DQS#; CK, CK#

VIX VREF(DC) - 150 VREF(DC) + 150 mV 4, 7

Differential input crossing voltage relative

to VDD/2 for CK, CK#

VIX (175) VREF(DC) - 175 VREF(DC) + 175 mV 4, 7, 8

Single-ended high level for strobes VSEH VDDQ/2 + 175 VDDQ mV 5

Single-ended high level for CK, CK# VDD/2 + 175 VDD mV 5

Single-ended low level for strobes VSEL VSSQ VDDQ/2 - 175 mV 6

Single-ended low level for CK, CK# VSS VDD/2 - 175 mV 6

Notes: 1. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.

2. Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe.

3. Differential input slew rate = 2 V/ns

4. Defines slew rate reference points, relative to input crossing voltages.

5. Minimum DC limit is relative to single-ended signals; overshoot specifications are appli-

cable.

6. Maximum DC limit is relative to single-ended signals; undershoot specifications are ap-

plicable.

7. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,

and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which

differential input signals must cross.

8. The VIX extended range (±175mV) is allowed only for the clock; this VIX extended range

is only allowed when the following conditions are met: The single-ended input signals

are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and

the differential slew rate of CK, CK# is greater than 3 V/ns.

9. VIX must provide 25mV (single-ended) of the voltages separation.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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Figure 16: VIX for Differential Signals

CK, DQS

VDD/2, VDDQ/2VDD/2, VDDQ/2

VIX

CK#, DQS#

VDD, VDDQ

CK, DQS

VDD, VDDQ

VSS, VSSQ

CK#, DQS#

VSS, VSSQ

VIX

Figure 17: Single-Ended Requirements for Differential Signals

VSS or VSSQ

VDD or VDDQ

VSEL,max

VSEH,min

VSEH

VSEL

CK or DQS

VDD/2 or VDDQ/2

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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Figure 18: Definition of Differential AC-Swing and tDVAC

VIH,diff(AC)min

0.0

VIL,diff,max

tDVAC

VIH,diff,min

VIL,diff(AC)max

Half cycle tDVAC

CK - CK#

DQS - DQS#

Table 28: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS -

DQS#

Slew Rate (V/ns)

tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)|

350mV 300mV

>4.0 75 175

4.0 57 170

3.0 50 167

2.0 38 163

1.9 34 162

1.6 29 161

1.4 22 159

1.2 13 155

1.0 0 150

<1.0 0 150

Note: 1. Below VIL(AC)

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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Slew Rate Definitions for Single-Ended Input Signals

Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate be-

tween the last crossing of VREF and the first crossing of VIH(AC)min. Setup (tIS and tDS)

nominal slew rate for a falling signal is defined as the slew rate between the last crossing

of VREF and the first crossing of VIL(AC)max.

Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate be-

tween the last crossing of VIL(DC)max and the first crossing of VREF. Hold (tIH and tDH)

nominal slew rate for a falling signal is defined as the slew rate between the last crossing

of VIH(DC)min and the first crossing of VREF (see Figure 19 (page 52)).

Table 29: Single-Ended Input Slew Rate Definition

Input Slew Rates

(Linear Signals) Measured

CalculationInput Edge From To

Setup Rising VREF VIH(AC)min VIH(AC)min - VREF

ǻTRSse

Falling VREF VIL(AC)max VREF - VIL(AC)max

ǻTFSse

Hold Rising VIL(DC)max VREF VREF - VIL(DC)max

ǻTFHse

Falling VIH(DC)min VREF VIH(DC)min - VREF

ǻTRSHse

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals

ǻTRSse

ǻTFSse

ǻTRHse

ǻTFHse

VREFDQ or

VREFCA

VIH(AC)min

VIH(DC)min

VIL(AC)max

VIL(DC)max

VREFDQ or

VREFCA

VIH(AC)min

VIH(DC)min

VIL(AC)max

VIL(DC)max

Setup

Hold

Single-ended input voltage (DQ, CMD, ADDR)

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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Slew Rate Definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and meas-

ured, as shown in Table 30 and Figure 20. The nominal slew rate for a rising signal is

defined as the slew rate between VIL,diff,max and VIH,diff,min. The nominal slew rate for a

falling signal is defined as the slew rate between VIH,diff,min and VIL,diff,max.

Table 30: Differential Input Slew Rate Definition

Differential Input

Slew Rates

(Linear Signals) Measured

CalculationInput Edge From To

CK and

DQS

reference

Rising VIL,diff,max VIH,diff,min VIH,diff,min - VIL,diff,max

ǻTRdiff

Falling VIH,diff,min VIL,diff,max VIH,diff,min - VIL,diff,max

ǻTFdiff

Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#

ǻTRdiff

ǻTFdiff

VIH,diff,min

VIL,diff,max

Differential input voltage (DQS, DQS#; CK, CK#)

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications – DC and AC

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ODT Characteristics

The ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the

DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values

and a functional representation are listed in Table 31 and Table 32 (page 55). The indi-

vidual pull-up and pull-down resistors (RTT(PU) and RTT(PD)) are defined as follows:

•RTT(PU) = (VDDQ - VOUT)/|IOUT|, under the condition that RTT(PD) is turned off

•RTT(PD) = (VOUT)/|IOUT|, under the condition that RTT(PU) is turned off

Figure 21: ODT Levels and I-V Characteristics

RTT(PU)

RTT(PD)

ODT

Chip in termination mode

VDDQ

VSSQ

IOUT = IPD - IPU

IPU

IPD

IOUT

VOUT

other

circuitry

such as

RCV, . . .

Table 31: On-Die Termination DC Electrical Characteristics

Parameter/Condition Symbol Min Nom Max Unit Notes

RTT effective impedance RTT(EFF) See Table 32 (page 55) 1, 2

Deviation of VM with respect to

VDDQ/2

ΔVM –5 5 % 1, 2, 3

Notes: 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a

stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to ODT Sensitivity

(page 56) if either the temperature or voltage changes after calibration.

2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current

I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]:

RTT = VIH(AC) - VIL(AC)

I(VIH(AC)) - I(VIL(AC))

3. Measure voltage (VM) at the tested pin with no load:

ǻVM = – 1

2 × VM

VDDQ

× 100

4. For IT and AT devices, the minimum values are derated by 6% when the device operates

between –40°C and 0°C (TC).

2Gb: x4, x8, x16 DDR3 SDRAM

ODT Characteristics

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ODT Resistors

Table 32 (page 55) provides an overview of the ODT DC electrical characteristics. The

values provided are not specification requirements; however, they can be used as design

guidelines to indicate what RTT is targeted to provide:

•R

TT Ω is made up of RTT120(PD240) and RTT120(PU240)

•R

TT Ω is made up of RTT60(PD120) and RTT60(PU120)

•R

TT Ω is made up of RTT40(PD80) and RTT40(PU80)

•R

TT Ω is made up of RTT30(PD60) and RTT30(PU60)

•R

TT Ω is made up of RTT20(PD40) and RTT20(PU40)

Table 32: RTT Effective Impedances

MR1

[9, 6, 2] RTT Resistor VOUT Min Nom Max Unit

0, 1, 0 ΩRTT120(PD240) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/1

0.5 × VDDQ 0.9 1.0 1.1 RZQ/1

0.8 × VDDQ 0.9 1.0 1.4 RZQ/1

RTT120(PU240) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/1

0.5 × VDDQ 0.9 1.0 1.1 RZQ/1

0.8 × VDDQ 0.6 1.0 1.1 RZQ/1

ΩVIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2

0, 0, 1 ΩRTT60(PD120) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/2

0.5 × VDDQ 0.9 1.0 1.1 RZQ/2

0.8 × VDDQ 0.9 1.0 1.4 RZQ/2

RTT60(PU120) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/2

0.5 × VDDQ 0.9 1.0 1.1 RZQ/2

0.8 × VDDQ 0.6 1.0 1.1 RZQ/2

ΩVIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4

0, 1, 1 ΩRTT40(PD80) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/3

0.5 × VDDQ 0.9 1.0 1.1 RZQ/3

0.8 × VDDQ 0.9 1.0 1.4 RZQ/3

RTT40(PU80) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/3

0.5 × VDDQ 0.9 1.0 1.1 RZQ/3

0.8 × VDDQ 0.6 1.0 1.1 RZQ/3

ΩVIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6

1, 0, 1 ΩRTT30(PD60) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/4

0.5 × VDDQ 0.9 1.0 1.1 RZQ/4

0.8 × VDDQ 0.9 1.0 1.4 RZQ/4

RTT30(PU60) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/4

0.5 × VDDQ 0.9 1.0 1.1 RZQ/4

0.8 × VDDQ 0.6 1.0 1.1 RZQ/4

ΩVIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8

2Gb: x4, x8, x16 DDR3 SDRAM

ODT Characteristics

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Table 32: RTT Effective Impedances (Continued)

MR1

[9, 6, 2] RTT Resistor VOUT Min Nom Max Unit

1, 0, 0 ΩRTT20(PD40) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/6

0.5 × VDDQ 0.9 1.0 1.1 RZQ/6

0.8 × VDDQ 0.9 1.0 1.4 RZQ/6

RTT20(PU40) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/6

0.5 × VDDQ 0.9 1.0 1.1 RZQ/6

0.8 × VDDQ 0.6 1.0 1.1 RZQ/6

ΩVIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12

Note: 1. Values assume an RZQ of 240Ω r

ODT Sensitivity

If either the temperature or voltage changes after I/O calibration, then the tolerance

limits listed in Table 31 (page 54) and Table 32 can be expected to widen according to

Table 33 and Table 34 (page 56).

Table 33: ODT Sensitivity Definition

Symbol Min Max Unit

RTT 0.9 - dRTTdT × |DT| - dRTTdV × |DV| 1.6 + dRTTdT × |DT| + dRTTdV × |DV| RZQ/(2, 4, 6, 8, 12)

Note: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration) and VDD = VDDQ.

Table 34: ODT Temperature and Voltage Sensitivity

Change Min Max Unit

dRTTdT 0 1.5 %/°C

dRTTdV 0 0.15 %/mV

Note: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration) and VDD = VDDQ.

ODT Timing Definitions

ODT loading differs from that used in AC timing measurements. The reference load for

ODT timings is shown in Figure 22. Two parameters define when ODT turns on or off

synchronously, two define when ODT turns on or off asynchronously, and another de-

fines when ODT turns on or off dynamically. Table 35 outlines and provides definition

and measurement references settings for each parameter (see Table 36 (page 57)).

ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to

turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance

begins to turn off.

2Gb: x4, x8, x16 DDR3 SDRAM

ODT Characteristics

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Figure 22: ODT Timing Reference Load

Timing reference point

DQ, DM

DQS, DQS#

TDQS, TDQS#

DUT

REF

= V

SSQ

DDQ

RZQ = 240ȍ

SSQ

= 25ȍ

CK, CK#

Table 35: ODT Timing Definitions

Symbol Begin Point Definition End Point Definition Figure

tAON Rising edge of CK - CK# defined by the end

point of ODTLon

Extrapolated point at VSSQ Figure 23 (page 58)

tAOF Rising edge of CK - CK# defined by the end

point of ODTLoff

Extrapolated point at VRTT,nom Figure 23 (page 58)

tAONPD Rising edge of CK - CK# with ODT first being

registered HIGH

Extrapolated point at VSSQ Figure 24 (page 58)

tAOFPD Rising edge of CK - CK# with ODT first being

registered LOW

Extrapolated point at VRTT,nom Figure 24 (page 58)

tADC Rising edge of CK - CK# defined by the end

point of ODTLcnw, ODTLcwn4, or ODTLcwn8

Extrapolated points at VRTT(WR) and

VRTT,nom

Figure 25 (page 59)

Table 36: Reference Settings for ODT Timing Measurements

Measured Parameter RTT,nom Setting RTT(WR) Setting VSW1 VSW2

tAON RZQ/4 (60Ωn/a 50mV 100mV

RZQ/12 (20Ωn/a 100mV 200mV

tAOF RZQ/4 (60Ωn/a 50mV 100mV

RZQ/12 (20Ωn/a 100mV 200mV

tAONPD RZQ/4 (60Ωn/a 50mV 100mV

RZQ/12 (20Ωn/a 100mV 200mV

tAOFPD RZQ/4 (60Ωn/a 50mV 100mV

RZQ/12 (20Ωn/a 100mV 200mV

tADC RZQ/12 (20ΩRZQ/2 (120Ω200mV 300mV

Note: 1. Assume an RZQ of 240Ω (±1%) and that proper ZQ calibration has been performed at a

stable temperature and voltage (VDDQ = VDD, VSSQ = VSS).

2Gb: x4, x8, x16 DDR3 SDRAM

ODT Characteristics

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Figure 23: tAON and tAOF Definitions

CK#

tAON

VSSQ

DQ, DM

DQS, DQS#

TDQS, TDQS#

Begin point: Rising edge of CK - CK#

defined by the end point of ODTLon

VSW1

End point: Extrapolated point at VSSQ

TSW1

TSW2

CK#

VDDQ/2

tAOF

Begin point: Rising edge of CK - CK#

defined by the end point of ODTLoff

End point: Extrapolated point at VRTT,nom

VRTT,nom

VSSQ

tAON tAOF

VSW2 VSW2

VSW1

TSW1

Figure 24: tAONPD and tAOFPD Definitions

CK#

tAONPD

VSSQ

DQ, DM

DQS, DQS#

TDQS, TDQS#

Begin point: Rising edge of CK - CK#

with ODT first registered high

VSW1

End point: Extrapolated point at VSSQ

TSW2

CK#

VDDQ/2

tAOFPD

Begin point: Rising edge of CK - CK#

with ODT first registered low

End point: Extrapolated point at VRTT,nom

VRTT,nom

VSSQ

tAONPD tAOFPD

TSW1

TSW2

TSW1

VSW2 VSW2

VSW1

2Gb: x4, x8, x16 DDR3 SDRAM

ODT Characteristics

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Figure 25: tADC Definition

CK#

tADC

DQ, DM

DQS, DQS#

TDQS, TDQS#

End point:

Extrapolated

point at VRTT,nom

TSW21

tADC

End point: Extrapolated point at VRTT(WR)

VDDQ/2

VSSQ

VRTT,nom

VRTT(WR)

VRTT,nom

Begin point: Rising edge of CK - CK#

defined by the end point of ODTLcnw

Begin point: Rising edge of CK - CK# defined by

the end point of ODTLcwn4 or ODTLcwn8

TSW11

VSW1

VSW2

TSW12

TSW22

2Gb: x4, x8, x16 DDR3 SDRAM

ODT Characteristics

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Output Driver Impedance

The output driver impedance is selected by MR1[5,1] during initialization. The selected

value is able to maintain the tight tolerances specified if proper ZQ calibration is per-

formed. Output specifications refer to the default output driver unless specifically sta-

ted otherwise. A functional representation of the output buffer is shown below. The out-

put driver impedance RON is defined by the value of the external reference resistor RZQ

as follows:

•RON,x = RZQ/y (with RZQ = 240Ω rx Ω or 40Ω with y = 7 or 6, respectively)

The individual pull-up and pull-down resistors RON(PU) and RON(PD) are defined as fol-

lows:

•RON(PU) = (VDDQ - VOUT)/|IOUT|, when RON(PD) is turned off

•RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off

Figure 26: Output Driver

RON(PU)

RON(PD)

Output driver

other

circuitry

such as

RCV, . . .

Chip in drive mode

VDDQ

VSSQ

IPU

IPD

IOUT

VOUT

2Gb: x4, x8, x16 DDR3 SDRAM

Output Driver Impedance

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34 Ohm Output Driver Impedance

The 34Ω driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings

and specifications listed herein apply to the 34Ω driver only. Its impedance RON is de-

fined by the value of the external reference resistor RZQ as follows: RON34 = RZQ/7 (with

nominal RZQ = 240Ω ±1%) and is actually 34.3Ω r

Table 37: 34 Ohm Driver Impedance Characteristics

MR1[5,1] RON Resistor VOUT Min Nom Max Unit Notes

0,1 ΩRON34(PD) 0.2/VDDQ 0.6 1.0 1.1 RZQ/7

0.5/VDDQ 0.9 1.0 1.1 RZQ/7

0.8/VDDQ 0.9 1.0 1.4 RZQ/7

RON34(PU) 0.2/VDDQ 0.9 1.0 1.4 RZQ/7

0.5/VDDQ 0.9 1.0 1.1 RZQ/7

0.8/VDDQ 0.6 1.0 1.1 RZQ/7

Pull-up/pull-down mismatch (MMPUPD) 0.5/VDDQ –10% n/a 10 % 2

Notes: 1. Tolerance limits assume RZQ of 240Ω ±1% and are applicable after proper ZQ calibra-

tion has been performed at a stable temperature and voltage: VDDQ = VDD; VSSQ = VSS).

Refer to 34 Ohm Output Driver Sensitivity (page 63) if either the temperature or the

voltage changes after calibration.

2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Meas-

ure both RON(PU) and RON(PD) at 0.5 × VDDQ:

MMPUPD = × 100

RON(PU) - RON(PD)

RON,nom

3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the de-

vice operates between –40°C and 0°C (TC).

2Gb: x4, x8, x16 DDR3 SDRAM

Output Driver Impedance

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34 Ohm Driver

The 34Ω driver’s current range has been calculated and summarized in Table 39

(page 62) VDD = 1.5V, Table 40 (page 62) for VDD = 1.57V, and Table 41 (page 63) for

VDD = 1.42V. The individual pull-up and pull-down resistors RON34(PD) and RON34(PU) are

defined as follows:

•RON34(PD) = (VOUT)/|IOUT|; RON34(PU) is turned off

•RON34(PU) = (VDDQ - VOUT)/|IOUT|; RON34(PD) is turned off

Table 38: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations

RON Min Nom Max Unit

RZQ = 240Ω r 237.6 240 242.4 Ω

RZQ/7 = (240Ω r 33.9 34.3 34.6 Ω

MR1[5,1] RON Resistor VOUT Min Nom Max Unit

0, 1 ΩRON34(PD) 0.2 × VDDQ 20.4 34.3 38.1 Ω

0.5 × VDDQ 30.5 34.3 38.1 Ω

0.8 × VDDQ 30.5 34.3 48.5 Ω

RON34(PU) 0.2 × VDDQ 30.5 34.3 48.5 Ω

0.5 × VDDQ 30.5 34.3 38.1 Ω

0.8 × VDDQ 20.4 34.3 38.1 Ω

Table 39: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V

MR1[5,1] RON Resistor VOUT Max Nom Min Unit

0, 1 ΩRON34(PD) IOL @ 0.2 × VDDQ 14.7 8.8 7.9 mA

IOL @ 0.5 × VDDQ 24.6 21.9 19.7 mA

IOL @ 0.8 × VDDQ 39.3 35.0 24.8 mA

RON34(PU) IOH @ 0.2 × VDDQ 39.3 35.0 24.8 mA

IOH @ 0.5 × VDDQ 24.6 21.9 19.7 mA

IOH @ 0.8 × VDDQ 14.7 8.8 7.9 mA

Table 40: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V

MR1[5,1] RON Resistor VOUT Max Nom Min Unit

0, 1 ΩRON34(PD) IOL @ 0.2 × VDDQ 15.5 9.2 8.3 mA

IOL @ 0.5 × VDDQ 25.8 23 20.7 mA

IOL @ 0.8 × VDDQ 41.2 36.8 26 mA

RON34(PU) IOH @ 0.2 × VDDQ 41.2 36.8 26 mA

IOH @ 0.5 × VDDQ 25.8 23 20.7 mA

IOH @ 0.8 × VDDQ 15.5 9.2 8.3 mA

2Gb: x4, x8, x16 DDR3 SDRAM

Output Driver Impedance

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Table 41: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V

MR1[5,1] RON Resistor VOUT Max Nom Min Unit

0, 1 ΩRON34(PD) IOL @ 0.2 × VDDQ 14.0 8.3 7.5 mA

IOL @ 0.5 × VDDQ 23.3 20.8 18.7 mA

IOL @ 0.8 × VDDQ 37.3 33.3 23.5 mA

RON34(PU) IOH @ 0.2 × VDDQ 37.3 33.3 23.5 mA

IOH @ 0.5 × VDDQ 23.3 20.8 18.7 mA

IOH @ 0.8 × VDDQ 14.0 8.3 7.5 mA

34 Ohm Output Driver Sensitivity

If either the temperature or the voltage changes after ZQ calibration, then the tolerance

limits listed in Table 37 (page 61) can be expected to widen according to Table 42 and

Table 43 (page 63).

Table 42: 34 Ohm Output Driver Sensitivity Definition

Symbol Min Max Unit

RON(PD) @ 0.2 × VDDQ 0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV| 1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV| RZQ/7

RON(PD) @ 0.5 × VDDQ 0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/7

RON(PD) @ 0.8 × VDDQ 0.9 - dRONdTH × |ΔT| - dRONdVH × |ΔV| 1.4 + dRONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/7

RON(PU) @ 0.2 × VDDQ 0.9 - dRONdTL × |ΔT| - dRONdVL × |ΔV| 1.4 + dRONdTL × |ΔT| + dRONdVL × |ΔV| RZQ/7

RON(PU) @ 0.5 × VDDQ 0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/7

RON(PU) @ 0.8 × VDDQ 0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV| 1.1 + dRONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/7

Note: 1. ΔT = T - T(@CALIBRATION)ΔV = VDDQ - VDDQ(@CALIBRATION); and VDD = VDDQ.

Table 43: 34 Ohm Output Driver Voltage and Temperature Sensitivity

Change Min Max Unit

dRONdTM 0 1.5 %/°C

dRONdVM 0 0.13 %/mV

dRONdTL 0 1.5 %/°C

dRONdVL 0 0.13 %/mV

dRONdTH 0 1.5 %/°C

dRONdVH 0 0.13 %/mV

2Gb: x4, x8, x16 DDR3 SDRAM

Output Driver Impedance

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Alternative 40 Ohm Driver

Table 44: 40 Ohm Driver Impedance Characteristics

MR1[5,1] RON Resistor VOUT Min Nom Max Unit

0,0 ΩRON40(PD) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/6

0.5 × VDDQ 0.9 1.0 1.1 RZQ/6

0.8 × VDDQ 0.9 1.0 1.4 RZQ/6

RON40(PU) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/6

0.5 × VDDQ 0.9 1.0 1.1 RZQ/6

0.8 × VDDQ 0.6 1.0 1.1 RZQ/6

Pull-up/pull-down mismatch (MMPUPD) 0.5 × VDDQ –10% n/a 10 %

Notes: 1. Tolerance limits assume RZQ of 240Ω ±1% and are applicable after proper ZQ calibra-

tion has been performed at a stable temperature and voltage (VDDQ = VDD; VSSQ = VSS).

Refer to 40 Ohm Output Driver Sensitivity (page 64) if either the temperature or the

voltage changes after calibration.

2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Meas-

ure both RON(PU) and RON(PD) at 0.5 × VDDQ:

MMPUPD = × 100

RON(PU) - RON(PD)

RON,nom

3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the de-

vice operates between –40°C and 0°C (TC).

40 Ohm Output Driver Sensitivity

If either the temperature or the voltage changes after I/O calibration, then the tolerance

limits listed in Table 44 can be expected to widen according to Table 45 and Table 46

(page 65).

Table 45: 40 Ohm Output Driver Sensitivity Definition

Symbol Min Max Unit

RON(PD) @ 0.2 × VDDQ 0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV| 1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV| RZQ/6

RON(PD) @ 0.5 × VDDQ 0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/6

RON(PD) @ 0.8 × VDDQ 0.9 - dRONdTH × |ΔT| - dRONdVH × |ΔV| 1.4 + dRONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/6

RON(PU) @ 0.2 × VDDQ 0.9 - dRONdTL × |ΔT| - dRONdVL × |ΔV| 1.4 + dRONdTL × |ΔT| + dRONdVL × |ΔV| RZQ/6

RON(PU) @ 0.5 × VDDQ 0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/6

RON(PU) @ 0.8 × VDDQ 0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV| 1.1 + dRONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/6

Note: 1. ΔT = T - T(@CALIBRATION)ΔV = VDDQ - VDDQ(@CALIBRATION); and VDD = VDDQ.

2Gb: x4, x8, x16 DDR3 SDRAM

Output Driver Impedance

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Table 46: 40 Ohm Output Driver Voltage and Temperature Sensitivity

Change Min Max Unit

dRONdTM 0 1.5 %/°C

dRONdVM 0 0.15 %/mV

dRONdTL 0 1.5 %/°C

dRONdVL 0 0.15 %/mV

dRONdTH 0 1.5 %/°C

dRONdVH 0 0.15 %/mV

2Gb: x4, x8, x16 DDR3 SDRAM

Output Driver Impedance

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Output Characteristics and Operating Conditions

The DRAM uses both single-ended and differential output drivers. The single-ended

output driver is summarized below, while the differential output driver is summarized

in Table 48 (page 67).

Table 47: Single-Ended Output Driver Characteristics

All voltages are referenced to VSS

Parameter/Condition Symbol Min Max Unit Notes

Output leakage current: DQ are disabled;

0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH

IOZ –5 5 μA 1

Output slew rate: Single-ended; For rising and falling edges,

measure between VOL(AC) = VREF - 0.1 × VDDQ and VOH(AC) =

VREF + 0.1 × VDDQ

SRQse 2.5 6 V/ns 1, 2, 3, 4

Single-ended DC high-level output voltage VOH(DC) 0.8 × VDDQ V 1, 2, 5

Single-ended DC mid-point level output voltage VOM(DC) 0.5 × VDDQ V 1, 2, 5

Single-ended DC low-level output voltage VOL(DC) 0.2 × VDDQ V 1, 2, 5

Single-ended AC high-level output voltage VOH(AC) VTT + 0.1 × VDDQ V 1, 2, 3, 6

Single-ended AC low-level output voltage VOL(AC) VTT - 0.1 × VDDQ V 1, 2, 3, 6

Delta RON between pull-up and pull-down for DQ/DQS MMPUPD –10 10 % 1, 7

Test load for AC timing and output slew rates Output to VTT (VDDQ/2) via 25Ω resistor 3

Notes: 1. RZQ of 240Ω ±1% with RZQ/7 enabled (default 34Ω driver) and is applicable after prop-

er ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD;

VSSQ = VSS).

2. VTT = VDDQ/2.

3. See Figure 29 (page 68) for the test load configuration.

4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from

HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are

either all static or all switching in the opposite direction. For all other DQ signal switch-

ing combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.

5. See Table 37 (page 61) for IV curve linearity. Do not use AC test load.

6. See Table 49 (page 69) for output slew rate.

7. See Table 37 (page 61) for additional information.

8. See Figure 27 (page 67) for an example of a single-ended output signal.

2Gb: x4, x8, x16 DDR3 SDRAM

Output Characteristics and Operating Conditions

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Table 48: Differential Output Driver Characteristics

All voltages are referenced to VSS

Parameter/Condition Symbol Min Max Unit Notes

Output leakage current: DQ are disabled;

0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH

IOZ –5 5 μA 1

Output slew rate: Differential; For rising and falling

edges, measure between VOL,diff(AC) = –0.2 × VDDQ and

VOH,diff(AC) = +0.2 × VDDQ

SRQdiff 5 12 V/ns 1

Output differential cross-point voltage VOX(AC) VREF - 150 VREF + 150 mV 1, 2, 3

Differential high-level output voltage VOH,diff(AC) +0.2 × VDDQ V 1, 4

Differential low-level output voltage VOL,diff(AC) –0.2 × VDDQ V 1, 4

Delta Ron between pull-up and pull-down for DQ/DQS MMPUPD –10 10 % 1, 5

Test load for AC timing and output slew rates Output to VTT (VDDQ/2) via 25Ω resistor 3

Notes: 1. RZQ of 240Ω ±1% with RZQ/7 enabled (default 34Ω driver) and is applicable after prop-

er ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD;

VSSQ = VSS).

2. VREF = VDDQ/2; slew rate @ 5 V/ns, interpolate for faster slew rate.

3. See Figure 29 (page 68) for the test load configuration.

4. See Table 50 (page 70) for the output slew rate.

5. See Table 37 (page 61) for additional information.

6. See Figure 28 (page 68) for an example of a differential output signal.

Figure 27: DQ Output Signal

VOH(AC)

MIN output

MAX output

VOL(AC)

2Gb: x4, x8, x16 DDR3 SDRAM

Output Characteristics and Operating Conditions

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Figure 28: Differential Output Signal

VOH

MIN output

MAX output

VOL

VOX(AC)max

VOX(AC)min

Reference Output Load

Figure 29 represents the effective reference load of 25Ω used in defining the relevant de-

vice AC timing parameters (except ODT reference timing) as well as the output slew rate

measurements. It is not intended to be a precise representation of a particular system

environment or a depiction of the actual load presented by a production tester. System

designers should use IBIS or other simulation tools to correlate the timing reference

load to a system environment.

Figure 29: Reference Output Load for AC Timing and Output Slew Rate

Timing reference point

DQS

DQS#

DUT

VREF

= V

DDQ

RZQ = 240ȍ

= 25ȍ

2Gb: x4, x8, x16 DDR3 SDRAM

Output Characteristics and Operating Conditions

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Slew Rate Definitions for Single-Ended Output Signals

The single-ended output driver is summarized in Table 47 (page 66). With the reference

load for timing measurements, the output slew rate for falling and rising edges is de-

fined and measured between VOL(AC) and VOH(AC) for single-ended signals.

Table 49: Single-Ended Output Slew Rate Definition

Single-Ended Output Slew

Rates (Linear Signals) Measured

CalculationOutput Edge From To

DQ Rising VOL(AC) VOH(AC) VOH(AC) - VOL(AC)

ǻTRse

Falling VOH(AC) VOL(AC) VOH(AC) - VOL(AC)

ǻTFse

Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals

VOH(AC)

VOL(AC)

VTT

ǻTFse

ǻTRse

2Gb: x4, x8, x16 DDR3 SDRAM

Output Characteristics and Operating Conditions

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Slew Rate Definitions for Differential Output Signals

The differential output driver is summarized in Table 48 (page 67). With the reference

load for timing measurements, the output slew rate for falling and rising edges is de-

fined and measured between VOL(AC) and VOH(AC) for differential signals.

Table 50: Differential Output Slew Rate Definition

Differential Output Slew

Rates (Linear Signals) Measured

CalculationOutput Edge From To

DQS, DQS# Rising VOL,diff(AC) VOH,diff(AC) VOH,diff(AC) - VOL,diff(AC)

ǻTRdiff

Falling VOH,diff(AC) VOL,diff(AC) VOH,diff(AC) - VOL,diff(AC)

ǻTFdiff

Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS#

ǻTRdiff

ǻTFdiff

VOH,diff(AC)

VOL,diff(AC)

2Gb: x4, x8, x16 DDR3 SDRAM

Output Characteristics and Operating Conditions

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Speed Bin Tables

Table 51: DDR3-1066 Speed Bins

DDR3-1066 Speed Bin -187E -187

Unit Notes

CL-tRCD-tRP 7-7-7 8-8-8

Parameter Symbol Min Max Min Max

Internal READ command to first data tAA 13.125 – 15 – ns

ACTIVATE to internal READ or WRITE delay

time

tRCD 13.125 – 15 – ns

PRECHARGE command period tRP 13.125 – 15 – ns

ACTIVATE-to-ACTIVATE or REFRESH command

period

tRC 50.625 – 52.5 – ns

ACTIVATE-to-PRECHARGE command period tRAS 37.5 9 x tREFI 37.5 9 x tREFI ns 1

CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 3.0 3.3 ns 2

CWL = 6 tCK (AVG) Reserved Reserved ns 3

CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 2.5 3.3 ns 2

CWL = 6 tCK (AVG) Reserved Reserved ns 3

CL = 7 CWL = 5 tCK (AVG) Reserved Reserved ns 3

CWL = 6 tCK (AVG) 1.875 <2.5 Reserved ns 2, 3

CL = 8 CWL = 5 tCK (AVG) Reserved Reserved ns 3

CWL = 6 tCK (AVG) 1.875 <2.5 1.875 <2.5 ns 2

Supported CL settings 5, 6, 7, 8 5, 6, 8 CK

Supported CWL settings 5, 6 5, 6 CK

Notes: 1. tREFI depends on TOPER.

2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,

both CL and CWL requirement settings need to be fulfilled.

3. Reserved settings are not allowed.

2Gb: x4, x8, x16 DDR3 SDRAM

Speed Bin Tables

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Table 52: DDR3-1333 Speed Bins

DDR3-1333 Speed Bin -15E1-152

Unit Notes

CL-tRCD-tRP 9-9-9 10-10-10

Parameter Symbol Min Max Min Max

Internal READ command to first data tAA 13.5 – 15 – ns

ACTIVATE to internal READ or WRITE delay

time

tRCD 13.5 – 15 – ns

PRECHARGE command period tRP 13.5 – 15 – ns

ACTIVATE-to-ACTIVATE or REFRESH command

period

tRC 49.5 – 51 – ns

ACTIVATE-to-PRECHARGE command period tRAS 36 9 x tREFI 36 9 x tREFI ns 3

CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 3.0 3.3 ns 4

CWL = 6, 7 tCK (AVG) Reserved Reserved ns 5

CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 2.5 3.3 ns 4

CWL = 6 tCK (AVG) Reserved Reserved ns 5

CWL = 7 tCK (AVG) Reserved Reserved ns 5

CL = 7 CWL = 5 tCK (AVG) Reserved Reserved ns 5

CWL = 6 tCK (AVG) 1.875 <2.5 Reserved ns 4, 5

CWL = 7 tCK (AVG) Reserved Reserved ns 5

CL = 8 CWL = 5 tCK (AVG) Reserved Reserved ns 5

CWL = 6 tCK (AVG) 1.875 <2.5 1.875 <2.5 ns 4

CWL = 7 tCK (AVG) Reserved Reserved ns 5

CL = 9 CWL = 5, 6 tCK (AVG) Reserved Reserved ns 5

CWL = 7 tCK (AVG) 1.5 <1.875 Reserved ns 4, 5

CL = 10 CWL = 5, 6 tCK (AVG) Reserved Reserved ns 5

CWL = 7 tCK (AVG) 1.5 <1.875 1.5 <1.875 ns 4

Supported CL settings 5, 6, 7, 8, 9, 10 5, 6, 8, 10 CK

Supported CWL settings 5, 6, 7 5, 6, 7 CK

Notes: 1. The -15E speed grade is backward compatible with 1066, CL = 7 (-187E).

2. The -15 speed grade is backward compatible with 1066, CL = 8 (-187).

3. tREFI depends on TOPER.

4. The CL and CWL settings result in tCK requirements. When making a selection of tCK,

both CL and CWL requirement settings need to be fulfilled.

5. Reserved settings are not allowed.

2Gb: x4, x8, x16 DDR3 SDRAM

Speed Bin Tables

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Table 53: DDR3-1600 Speed Bins

DDR3-1600 Speed Bin -1251

Unit Notes

CL-tRCD-tRP 11-11-11

Parameter Symbol Min Max

Internal READ command to first data tAA 13.75 – ns

ACTIVATE to internal READ or WRITE delay time tRCD 13.75 – ns

PRECHARGE command period tRP 13.75 – ns

ACTIVATE-to-ACTIVATE or REFRESH command period tRC 48.75 – ns

ACTIVATE-to-PRECHARGE command period tRAS 35 9 x tREFI ns 2

CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 3

CWL = 6, 7, 8 tCK (AVG) Reserved ns 4

CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 3

CWL = 6 tCK (AVG) Reserved ns 4

CWL = 7, 8 tCK (AVG) Reserved ns 4

CL = 7 CWL = 5 tCK (AVG) Reserved ns 4

CWL = 6 tCK (AVG) 1.875 <2.5 ns 3

CWL = 7 tCK (AVG) Reserved ns 4

CWL = 8 tCK (AVG) Reserved ns 4

CL = 8 CWL = 5 tCK (AVG) Reserved ns 4

CWL = 6 tCK (AVG) 1.875 <2.5 ns 3

CWL = 7 tCK (AVG) Reserved ns 4

CWL = 8 tCK (AVG) Reserved ns 4

CL = 9 CWL = 5, 6 tCK (AVG) Reserved ns 4

CWL = 7 tCK (AVG) 1.5 <1.875 ns 3

CWL = 8 tCK (AVG) Reserved ns 4

CL = 10 CWL = 5, 6 tCK (AVG) Reserved ns 4

CWL = 7 tCK (AVG) 1.5 <1.875 ns 3

CWL = 8 tCK (AVG) Reserved ns 4

CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 4

CWL = 8 tCK (AVG) 1.25 <1.5 ns 3

Supported CL settings 5, 6, 7, 8, 9, 10, 11 CK

Supported CWL settings 5, 6, 7, 8 CK

Notes: 1. The -125 speed grade is backward compatible with 1333, CL = 9 (-15E) and 1066, CL = 7

(-187E).

2. tREFI depends on TOPER.

3. The CL and CWL settings result in tCK requirements. When making a selection of tCK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

2Gb: x4, x8, x16 DDR3 SDRAM

Speed Bin Tables

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Table 54: DDR3-1866 Speed Bins

DDR3-1866 Speed Bin -1071

Unit Notes

CL-tRCD-tRP 13-13-13

Parameter Symbol Min Max

Internal READ command to first data tAA 13.91 20

ACTIVATE to internal READ or WRITE delay time tRCD 13.91 – ns

PRECHARGE command period tRP 13.91 – ns

ACTIVATE-to-ACTIVATE or REFRESH command period tRC 47.91 – ns

ACTIVATE-to-PRECHARGE command period tRAS 34 9 x tREFI ns 2

CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 3

CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4

CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 3

CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4

CL = 7 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 4

CWL = 6 tCK (AVG) 1.875 <2.5 ns 3

CL = 8 CWL = 5, 8, 9 tCK (AVG) Reserved ns 4

CWL = 6 tCK (AVG) 1.875 <2.5 ns 3

CWL = 7 tCK (AVG) Reserved ns 4

CL = 9 CWL = 5, 6, 8, 9 tCK (AVG) Reserved ns 4

CWL = 7 tCK (AVG) 1.5 <1.875 ns 3

CL = 10 CWL = 5, 6, 9 tCK (AVG) Reserved ns 4

CWL = 7 tCK (AVG) 1.5 <1.875 ns 3

CWL = 8 tCK (AVG) Reserved ns 4

CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 4

CWL = 8 tCK (AVG) 1.25 <1.5 ns 3

CWL = 9 tCK (AVG) Reserved ns 4

CL = 12 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4

CWL = 9 tCK (AVG) Reserved ns 4

CL = 13 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4

CWL = 9 tCK (AVG) 1.071 <1.25 ns 3

Supported CL settings 5, 6, 7, 8, 9, 10, 11, 13 CK

Supported CWL settings 5, 6, 7, 8, 9 CK

Notes: 1. The -107 speed grade is backward compatible with 1600, CL = 11 (-125) , 1333, CL = 9

(-15E) and 1066, CL = 7 (-187E).

2. tREFI depends on TOPER.

3. The CL and CWL settings result in tCK requirements. When making a selection of tCK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

2Gb: x4, x8, x16 DDR3 SDRAM

Speed Bin Tables

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Table 55: DDR3-2133 Speed Bins

DDR3-2133 Speed Bin -0931

Unit Notes

CL-tRCD-tRP 14-14-14

Parameter Symbol Min Max

Internal READ command to first data tAA 13.09 20

ACTIVATE to internal READ or WRITE delay time tRCD 13.09 – ns

PRECHARGE command period tRP 13.09 – ns

ACTIVATE-to-ACTIVATE or REFRESH command period tRC 46.13 – ns

ACTIVATE-to-PRECHARGE command period tRAS 33 9 x tREFI ns 2

CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 3

CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4

CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 3

CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4

CL = 7 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 4

CWL = 6 tCK (AVG) 1.875 <2.5 ns 3

CL = 8 CWL = 5, 8, 9 tCK (AVG) Reserved ns 4

CWL = 6 tCK (AVG) 1.875 <2.5 ns 3

CWL = 7 tCK (AVG) Reserved ns 4

CL = 9 CWL = 5, 6, 8, 9 tCK (AVG) Reserved ns 4

CWL = 7 tCK (AVG) 1.5 <1.875 ns 3

CL = 10 CWL = 5, 6, 9 tCK (AVG) Reserved ns 4

CWL = 7 tCK (AVG) 1.5 <1.875 ns 3

CWL = 8 tCK (AVG) Reserved ns 4

CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 4

CWL = 8 tCK (AVG) 1.25 <1.5 ns 3

CWL = 9 tCK (AVG) Reserved ns 4

CL = 12 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4

CWL = 9 tCK (AVG) Reserved ns 4

CL = 13 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4

CWL = 9 tCK (AVG) 1.071 <1.25 ns 3

CL = 14 CWL = 5, 6, 7, 8, 9 tCK (AVG) Reserved Reserved ns 4

CWL = 10 tCK (AVG) 0.938 <1.071 ns 3

Supported CL settings 5, 6, 7, 8, 9, 10, 11, 13, 14 CK

Supported CWL settings 5, 6, 7, 8, 9 CK

Notes: 1. The -093 speed grade is backward compatible with 1866, CL = 13 (-107) , 1600, CL = 11

(-125) , 1333, CL = 9 (-15E) and 1066, CL = 7 (-187E).

2. tREFI depends on TOPER.

3. The CL and CWL settings result in tCK requirements. When making a selection of tCK,

both CL and CWL requirement settings need to be fulfilled.

4. Reserved settings are not allowed.

2Gb: x4, x8, x16 DDR3 SDRAM

Speed Bin Tables

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Electrical Characteristics and AC Operating Conditions

Table 56: Electrical Characteristics and AC Operating Conditions

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Unit NotesMin Max Min Max Min Max Min Max

Clock Timing

Clock period average:

DLL disable mode

TC ≤ 85°C tCK

(DLL_DIS)

8 7800 8 7800 8 7800 8 7800 ns 9, 42

TC = >85°C to 95°C 8 3900 8 3900 8 3900 8 3900 ns 42

Clock period average: DLL enable mode tCK (AVG) See Speed Bin Tables (page 71) for tCK range allowed ns 10, 11

High pulse width average tCH (AVG) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 CK 12

Low pulse width average tCL (AVG) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 CK 12

Clock period jitter DLL locked tJITper –100 100 –90 90 –80 80 –70 70 ps 13

DLL locking tJITper,lck –90 90 –80 80 –70 70 –60 60 ps 13

Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN + tJITper MIN; MAX = tCK (AVG) MAX + tJITper

MAX

Clock absolute high pulse width tCH (ABS) 0.43 – 0.43 – 0.43 – 0.43 – tCK

(AVG)

Clock absolute low pulse width tCL (ABS) 0.43 – 0.43 – 0.43 – 0.43 – tCK

(AVG)

Cycle-to-cycle jitter DLL locked tJITcc 200 180 160 140 ps 16

DLL locking tJITcc,lck 180 160 140 120 ps 16

Cumulative error across 2 cycles tERR2per –147 147 –132 132 –118 118 –103 103 ps 17

3 cycles tERR3per –175 175 –157 157 –140 140 –122 122 ps 17

4 cycles tERR4per –194 194 –175 175 –155 155 –136 136 ps 17

5 cycles tERR5per –209 209 –188 188 –168 168 –147 147 ps 17

6 cycles tERR6per –222 222 –200 200 –177 177 –155 155 ps 17

7 cycles tERR7per –232 232 –209 209 –186 186 –163 163 ps 17

8 cycles tERR8per –241 241 –217 217 –193 193 –169 169 ps 17

9 cycles tERR9per –249 249 –224 224 –200 200 –175 175 ps 17

10 cycles tERR10per –257 257 –231 231 –205 205 –180 180 ps 17

11 cycles tERR11per –263 263 –237 237 –210 210 –184 184 ps 17

12 cycles tERR12per –269 269 –242 242 –215 215 –188 188 ps 17

n = 13, 14 . . . 49, 50

cycles

tERRnper tERRnper MIN = (1 + 0.68ln[n]) × tJITper MIN

tERRnper MAX = (1 + 0.68ln[n]) × tJITper MAX

ps 17

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 56: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Unit NotesMin Max Min Max Min Max Min Max

DQ Input Timing

Data setup time to

DQS, DQS#

Base (specification) tDS

(AC175)

75 – 25 – – – – – ps 18, 19,

VREF @ 1 V/ns 250 – 200 – – – – – ps 19, 20

Data setup time to

DQS, DQS#

Base (specification) tDS

(AC150)

125 – 75 – 30 – 10 – ps 18, 19,

VREF @ 1 V/ns 275 – 250 – 180 – 160 – ps 19, 20

Data setup time to

DQS, DQS#

Base (specification) tDS

(AC135)

––––––––ps18, 19

VREF @ 1 V/ns ––––––––ps19, 20

Data hold time from

DQS, DQS#

Base (specification) tDH

(DC100)

150 – 100 – 65 – 45 – ps 18, 19

VREF @ 1 V/ns 250 – 200 – 165 – 145 – ps 19, 20

Minimum data pulse width tDIPW 600 – 490 – 400 – 360 – ps 41

DQ Output Timing

DQS, DQS# to DQ skew, per access tDQSQ – 200 – 150 – 125 – 100 ps

DQ output hold time from DQS, DQS# tQH 0.38 – 0.38 – 0.38 – 0.38 – tCK

(AVG)

DQ Low-Z time from CK, CK# tLZDQ –800 400 –600 300 –500 250 –450 225 ps 22, 23

DQ High-Z time from CK, CK# tHZDQ – 400 – 300 – 250 – 225 ps 22, 23

DQ Strobe Input Timing

DQS, DQS# rising to CK, CK# rising tDQSS –0.25 0.25 –0.25 0.25 –0.25 0.25 –0.27 0.27 CK 25

DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK

DQS, DQS# differential input high pulse

width

tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK

DQS, DQS# falling setup to CK, CK# rising tDSS 0.2 – 0.2 – 0.2 – 0.18 – CK 25

DQS, DQS# falling hold from CK, CK# rising tDSH 0.2 – 0.2 – 0.2 – 0.18 – CK 25

DQS, DQS# differential WRITE preamble tWPRE 0.9 – 0.9 – 0.9 – 0.9 – CK

DQS, DQS# differential WRITE postamble tWPST 0.3 – 0.3 – 0.3 – 0.3 – CK

DQ Strobe Output Timing

DQS, DQS# rising to/from rising CK, CK# tDQSCK –400 400 –300 300 –255 255 –225 225 ps 23

DQS, DQS# rising to/from rising CK, CK#

when DLL is disabled

tDQSCK

(DLL_DIS)

110110110110ns26

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 56: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Unit NotesMin Max Min Max Min Max Min Max

DQS, DQS# differential output high time tQSH 0.38 – 0.38 – 0.40 – 0.40 – CK 21

DQS, DQS# differential output low time tQSL 0.38 – 0.38 – 0.40 – 0.40 – CK 21

DQS, DQS# Low-Z time (RL - 1) tLZDQS –800 400 –600 300 –500 250 –450 225 ps 22, 23

DQS, DQS# High-Z time (RL + BL/2) tHZDQS – 400 – 300 – 250 – 225 ps 22, 23

DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 0.9 Note 24 0.9 Note 24 0.9 Note 24 CK 23, 24

DQS, DQS# differential READ postamble tRPST 0.3 Note 27 0.3 Note 27 0.3 Note 27 0.3 Note 27 CK 23, 27

Command and Address Timing

DLL locking time tDLLK 512 – 512 – 512 – 512 – CK 28

CTRL, CMD, ADDR

setup to CK,CK#

Base (specification) tIS

(AC175)

200 – 125 – 65 – 45 – ps 29, 30,

VREF @ 1 V/ns 375 – 300 – 240 – 220 – ps 20, 30

CTRL, CMD, ADDR

setup to CK,CK#

Base (specification) tIS

(AC150)

350 – 275 – 190 – 170 – ps 29, 30,

VREF @ 1 V/ns 500 – 425 – 340 – 320 – ps 20, 30

CTRL, CMD, ADDR hold

from CK,CK#

Base (specification) tIH

(DC100)

275 – 200 – 140 – 120 – ps 29, 30

VREF @ 1 V/ns 375 – 300 – 240 – 220 – ps 20, 30

Minimum CTRL, CMD, ADDR pulse width tIPW 900 – 780 – 620 – 560 – ps 41

ACTIVATE to internal READ or WRITE delay tRCD See Speed Bin Tables (page 71) for tRCD ns 31

PRECHARGE command period tRP See Speed Bin Tables (page 71) for tRP ns 31

ACTIVATE-to-PRECHARGE command period tRAS See Speed Bin Tables (page 71) for tRAS ns 31, 32

ACTIVATE-to-ACTIVATE command period tRC See Speed Bin Tables (page 71) for tRC ns 31, 43

ACTIVATE-to-ACTIVATE

minimum command

period

x4/x8 (1KB page

size)

tRRD MIN = greater of

4CK or 10ns

MIN = greater of

4CK or 7.5ns

MIN = greater of

4CK or 6ns

MIN = greater of

4CK or 6ns

CK 31

x16 (2KB page size) MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns CK 31

Four ACTIVATE

windows

x4/x8 (1KB page

size)

tFAW 40 – 37.5 – 30 – 30 – ns 31

x16 (2KB page size) 50 – 50 – 45 – 40 – ns 31

Write recovery time tWR MIN = 15ns; MAX = n/a ns 31, 32,

33,34

Delay from start of internal WRITE

transaction to internal READ command

tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 56: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Unit NotesMin Max Min Max Min Max Min Max

READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32

CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK

Auto precharge write recovery + precharge

time

tDAL MIN = WR + tRP/tCK (AVG); MAX = n/a CK

MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK

MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK

MULTIPURPOSE REGISTER READ burst end to

mode register set for multipurpose register

exit

tMPRR MIN = 1CK; MAX = n/a CK

Calibration Timing

ZQCL command: Long

calibration time

POWER-UP and RE-

SET operation

tZQinit 512 – 512 – 512 – 512 – CK

Normal operation tZQoper 256 – 256 – 256 – 256 – CK

ZQCS command: Short calibration time tZQCS 64 – 64 – 64 – 64 – CK

Initialization and Reset Timing

Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK

Begin power supply ramp to power supplies

stable

tVDDPR MIN = n/a; MAX = 200 ms

RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms

RESET# LOW to I/O and RTT High-Z tIOZ MIN = n/a; MAX = 20 ns 35

Refresh Timing

REFRESH-to-ACTIVATE or REFRESH

command period

tRFC – 1Gb MIN = 110; MAX = 70,200 ns

tRFC – 2Gb MIN = 160; MAX = 70,200 ns

tRFC – 4Gb MIN = 260; MAX = 70,200 ns

tRFC – 8Gb MIN = 350; MAX = 70,200 ns

Maximum refresh

period

TC ≤ 85°C – 64 (1X) ms 36

TC > 85°C 32 (2X) ms 36

Maximum average

periodic refresh

TC ≤ 85°C tREFI 7.8 (64ms/8192) μs 36

TC > 85°C 3.9 (32ms/8192) μs 36

Self Refresh Timing

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 56: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Unit NotesMin Max Min Max Min Max Min Max

Exit self refresh to commands not requiring a

locked DLL

tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK

Exit self refresh to commands requiring a

locked DLL

tXSDLL MIN = tDLLK (MIN); MAX = n/a CK 28

Minimum CKE low pulse width for self re-

fresh entry to self refresh exit timing

tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK

Valid clocks after self refresh entry or power-

down entry

tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK

Valid clocks before self refresh exit,

power-down exit, or reset exit

tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK

Power-Down Timing

CKE MIN pulse width tCKE (MIN) Greater of 3CK

or 7.5ns

Greater of 3CK

or 5.625ns

Greater of 3CK

or 5.625ns

Greater of 3CK

or 5ns

Command pass disable delay tCPDED MIN = 1; MAX = n/a CK

Power-down entry to power-down exit tim-

ing

tPD MIN = tCKE (MIN); MAX = 9 * tREFI CK

Begin power-down period prior to CKE

registered HIGH

tANPD WL - 1CK CK

Power-down entry period: ODT either

synchronous or asynchronous

PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK

Power-down exit period: ODT either

synchronous or asynchronous

PDX tANPD + tXPDLL CK

Power-Down Entry Minimum Timing

ACTIVATE command to power-down entry tACTPDEN MIN = 1 CK

PRECHARGE/PRECHARGE ALL command to

power-down entry

tPRPDEN MIN = 1 CK

REFRESH command to power-down entry tREFPDEN MIN = 1 CK 37

MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK

READ/READ with auto precharge command

to power-down entry

tRDPDEN MIN = RL + 4 + 1 CK

WRITE command to

power-down entry

BL8 (OTF, MRS)

BC4OTF

tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK

BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 56: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Unit NotesMin Max Min Max Min Max Min Max

WRITE with auto

precharge command to

power-down entry

BL8 (OTF, MRS)

BC4OTF

tWRAP-

DEN

MIN = WL + 4 + WR + 1 CK

BC4MRS tWRAP-

DEN

MIN = WL + 2 + WR + 1 CK

Power-Down Exit Timing

DLL on, any valid command, or DLL off to

commands not requiring locked DLL

tXP MIN = greater of 3CK or 7.5ns;

MAX = n/a

MIN = greater of 3CK or 6ns;

MAX = n/a

Precharge power-down with DLL off to

commands requiring a locked DLL

tXPDLL MIN = greater of 10CK or 24ns; MAX = n/a CK 28

ODT Timing

RTT synchronous turn-on delay ODTLon CWL + AL - 2CK CK 38

RTT synchronous turn-off delay ODTLoff CWL + AL - 2CK CK 40

RTT turn-on from ODTL on reference tAON –400 400 –300 300 –250 250 –225 225 ps 23, 38

RTT turn-off from ODTL off reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 CK 39, 40

Asynchronous RTT turn-on delay

(power-down with DLL off)

tAONPD MIN = 2; MAX = 8.5 ns 38

Asynchronous RTT turn-off delay

(power-down with DLL off)

tAOFPD MIN = 2; MAX = 8.5 ns 40

ODT HIGH time with WRITE command and

BL8

ODTH8 MIN = 6; MAX = n/a CK

ODT HIGH time without WRITE command or

with WRITE command and BC4

ODTH4 MIN = 4; MAX = n/a CK

Dynamic ODT Timing

RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK

RTT(WR)-to-RTT,nom change skew - BC4 ODTLcwn4 4CK + ODTLoff CK

RTT(WR)-to-RTT,nom change skew - BL8 ODTLcwn8 6CK + ODTLoff CK

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 CK 39

Write Leveling Timing

First DQS, DQS# rising edge tWLMRD 40 – 40 – 40 – 40 – CK

DQS, DQS# delay tWLDQSEN 25 – 25 – 25 – 25 – CK

Write leveling setup from rising CK, CK#

crossing to rising DQS, DQS# crossing

tWLS 325 – 245 – 195 – 165 – ps

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 56: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Unit NotesMin Max Min Max Min Max Min Max

Write leveling hold from rising DQS, DQS#

crossing to rising CK, CK# crossing

tWLH 325 – 245 – 195 – 165 – ps

Write leveling output delay tWLO09090907.5ns

Write leveling output error tWLOE 02020202ns

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Notes: 1. AC timing parameters are valid from specified TC MIN to TC MAX values.

2. All voltages are referenced to VSS.

3. Output timings are only valid for RON34 output buffer selection.

4. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.

The unit CK represents one clock cycle of the input clock, counting the actual clock

edges.

5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environ-

ment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the

AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum

slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs

and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC).

6. All timings that use time-based values (ns, μs, ms) should use tCK (AVG) to determine the

correct number of clocks (Table 56 (page 76) uses CK or tCK [AVG] interchangeably). In

the case of noninteger results, all minimum limits are to be rounded up to the nearest

whole integer, and all maximum limits are to be rounded down to the nearest whole

integer.

7. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is

the rising edge. Clock or CK refers to the CK and CK# differential crossing point when

CK is the rising edge.

8. This output load is used for all AC timing (except ODT reference timing) and slew rates.

The actual test load may be different. The output signal voltage reference point is

VDDQ/2 for single-ended signals and the crossing point for differential signals (see Fig-

ure 29 (page 68)).

9. When operating in DLL disable mode, Micron does not warrant compliance with normal

mode timings or functionality.

10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG)

MIN is the smallest clock rate allowed, with the exception of a deviation due to clock

jitter. Input clock jitter is allowed provided it does not exceed values specified and must

be of a random Gaussian distribution in nature.

11. Spread spectrum is not included in the jitter specification values. However, the input

clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with

an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread

spectrum may not use a clock rate below tCK (AVG) MIN.

12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 con-

secutive clocks and is the smallest clock half period allowed, with the exception of a de-

viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values

specified and must be of a random Gaussian distribution in nature.

13. The period jitter (tJITper) is the maximum deviation in the clock period from the average

or nominal clock. It is allowed in either the positive or negative direction.

14. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one

rising edge to the following falling edge.

15. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-

ing edge to the following rising edge.

16. The cycle-to-cycle jitter tJITcc is the amount the clock period can deviate from one cycle

to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL

locking time.

17. The cumulative jitter error tERRnper, where n is the number of clocks between 2 and 50,

is the amount of clock time allowed to accumulate consecutively away from the average

clock over n number of clock cycles.

18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns slew rate DQs and 2 V/ns

slew rate differential DQS, DQS#.

19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-

tion edge to its respective data strobe signal (DQS, DQS#) crossing.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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20. The setup and hold times are listed converting the base specification values (to which

derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate

of 1 V/ns, are for reference only.

21. When the device is operated with input clock jitter, this parameter needs to be derated

by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output

deratings are relative to the SDRAM input clock).

22. Single-ended signal parameter.

23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-

rameters must be derated by the actual jitter error when input clock jitter is present,

even when within specification. This results in each parameter becoming larger. The fol-

lowing parameters are required to be derated by subtracting tERR10per (MAX): tDQSCK

(MIN), tLZDQS (MIN), tLZDQ (MIN), and tAON (MIN). The following parameters are re-

quired to be derated by subtracting tERR10per (MIN): tDQSCK (MAX), tHZ (MAX), tLZDQS

(MAX), tLZDQ MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtract-

ing tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN).

24. The maximum preamble is bound by tLZDQS (MAX).

25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-

spective clock signal (CK, CK#) crossing. The specification values are not affected by the

amount of clock jitter applied, as these are relative to the clock signal crossing. These

parameters should be met whether clock jitter is present.

26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.

27. The maximum postamble is bound by tHZDQS (MAX).

28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-

mands. In addition, after any change of latency tXPDLL, timing must be met.

29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address

slew rate and 2 V/ns CK, CK# differential slew rate.

30. These parameters are measured from a command/address signal transition edge to its

respective clock (CK, CK#) signal crossing. The specification values are not affected by

the amount of clock jitter applied as the setup and hold times are relative to the clock

signal crossing that latches the command/address. These parameters should be met

whether clock jitter is present.

31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM

[ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-

ple, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifi-

cations are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will

support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are

met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are

valid even if six clocks are less than 15ns due to input clock jitter.

32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-

ternal PRECHARGE command until tRAS (MIN) has been satisfied.

33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR.

34. The start of the write recovery time is defined as follows:

• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL

• For BC4 (OTF): Rising clock edge four clock cycles after WL

• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL

35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in

High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-

sive current, depending on bus activity.

36. The refresh period is 64ms when TC is less than or equal to 85°C. This equates to an aver-

age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at

least once every 70.3μs. When TC is greater than 85°C, the refresh period is 32ms.

37. Although CKE is allowed to be registered LOW after a REFRESH command when

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Electrical Characteristics and AC Operating Conditions

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tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN)

is required.

38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to

turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT

reference load is shown in Figure 21 (page 54). Designs that were created prior to JEDEC

tightening the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maxi-

mum.

39. Half-clock output parameters must be derated by the actual tERR10per and tJITdty when

input clock jitter is present. This results in each parameter becoming larger. The parame-

ters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both

tERR10per (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are

required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX).

40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT

turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is

shown in Figure 22 (page 57). This output load is used for ODT timings (see Figure 29

(page 68)).

41. Pulse width of a input signal is defined as the width between the first crossing of

VREF(DC) and the consecutive crossing of VREF(DC).

42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should

have at least one NOP command between it and another AUTO REFRESH command. Ad-

ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should

be followed by a PRECHARGE ALL command.

43. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in a reduction of REFRESH characteristics or

product lifetime.

44. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is

used, the associated setup time for that AC level must also be used. Additionally, one

VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and

VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/

command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min

with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min

with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Electrical Characteristics and AC Operating Conditions

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-1866 DDR3-2133

Unit NotesMin Max Min Max

Clock Timing

Clock period average:

DLL disable mode

TC = 0°C to 85°C tCK

(DLL_DIS)

8 7800 8 7800 ns 9, 42

TC = >85°C to 95°C 8 3900 8 3900 ns 42

Clock period average: DLL enable mode tCK (AVG) See Speed Bin Tables (page 71) for tCK range allowed ns 10, 11

High pulse width average tCH (AVG) 0.47 0.53 0.47 0.53 CK 12

Low pulse width average tCL (AVG) 0.47 0.53 0.47 0.53 CK 12

Clock period jitter DLL locked tJITper –60 60 –50 50 ps 13

DLL locking tJITper,lck –50 50 –40 40 ps 13

Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN +

tJITper MIN; MAX =

tCK (AVG) MAX +

tJITper MAX ps

Clock absolute high pulse width tCH (ABS) 0.43 – 0.43 – tCK

(AVG)

Clock absolute low pulse width tCL (ABS) 0.43 – 0.43 – tCK

(AVG)

Cycle-to-cycle jitter DLL locked tJITcc 120 120 ps 16

DLL locking tJITcc,lck 100 100 ps 16

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-1866 DDR3-2133

Unit NotesMin Max Min Max

Cumulative error across 2 cycles tERR2per –88 88 -74 74 ps 17

3 cycles tERR3per –105 105 -87 87 ps 17

4 cycles tERR4per –117 117 -97 97 ps 17

5 cycles tERR5per –126 126 -105 105 ps 17

6 cycles tERR6per –133 133 -111 111 ps 17

7 cycles tERR7per –139 139 -116 116 ps 17

8 cycles tERR8per –145 145 -121 121 ps 17

9 cycles tERR9per –150 150 -125 125 ps 17

10 cycles tERR10per –154 154 -128 128 ps 17

11 cycles tERR11per –158 158 -132 132 ps 17

12 cycles tERR12per –161 161 -134 134 ps 17

n = 13, 14 . . . 49, 50

cycles

tERRnper tERRnper MIN = (1 + 0.68ln[n]) × tJITper MIN

tERRnper MAX = (1 + 0.68ln[n]) × tJITper MAX

DQ Input Timing

Data setup time to

DQS, DQS#

Base (specification)

@ 2 V/ns

tDS

(AC135)

68 – 53 – ps 18, 19

VREF @ 2 V/ns 135 – 120.5 – ps 19, 20

Data hold time from

DQS, DQS#

Base (specification)

@ 2 V/ns

tDH

(DC100)

70 – 55 – ps 18, 19

VREF @ 2 V/ns 120 – 105 – ps 19, 20

Minimum data pulse width tDIPW 320 – 280 – ps 41

DQ Output Timing

DQS, DQS# to DQ skew, per access tDQSQ – 85 – 75 ps

DQ output hold time from DQS, DQS# tQH 0.38 – 0.38 – tCK

(AVG)

DQ Low-Z time from CK, CK# tLZDQ –390 195 –360 180 ps 22, 23

DQ High-Z time from CK, CK# tHZDQ – 195 – 180 ps 22, 23

DQ Strobe Input Timing

DQS, DQS# rising to CK, CK# rising tDQSS –0.27 0.27 –0.27 0.27 CK 25

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-1866 DDR3-2133

Unit NotesMin Max Min Max

DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 CK

DQS, DQS# differential input high pulse

width

tDQSH 0.45 0.55 0.45 0.55 CK

DQS, DQS# falling setup to CK, CK# rising tDSS 0.18 – 0.18 – CK 25

DQS, DQS# falling hold from CK, CK# rising tDSH 0.18 – 0.18 – CK 25

DQS, DQS# differential WRITE preamble tWPRE 0.9 – 0.9 – CK

DQS, DQS# differential WRITE postamble tWPST 0.3 – 0.3 – CK

DQ Strobe Output Timing

DQS, DQS# rising to/from rising CK, CK# tDQSCK –195 195 –180 180 ps 23

DQS, DQS# rising to/from rising CK, CK#

when DLL is disabled

tDQSCK

(DLL_DIS)

1 10 1 10 ns 26

DQS, DQS# differential output high time tQSH 0.40 – 0.40 – CK 21

DQS, DQS# differential output low time tQSL 0.40 – 0.40 – CK 21

DQS, DQS# Low-Z time (RL - 1) tLZDQS –390 195 –360 180 ps 22, 23

DQS, DQS# High-Z time (RL + BL/2) tHZDQS – 195 – 180 ps 22, 23

DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 0.9 Note 24 CK 23, 24

DQS, DQS# differential READ postamble tRPST 0.3 Note 27 0.3 Note 27 CK 23, 27

Command and Address Timing

DLL locking time tDLLK 512 – 512 – CK 28

CTRL, CMD, ADDR

setup to CK,CK#

Base (specification) tIS

(AC135)

65 – 60 – ps 29, 30,

VREF @ 1 V/ns 200 – 195 – ps 20, 30

CTRL, CMD, ADDR

setup to CK,CK#

Base (specification) tIS

(AC125)

150 – 135 – ps 29, 30,

VREF @ 1 V/ns 275 – 260 – ps 20, 30

CTRL, CMD, ADDR hold

from CK,CK#

Base (specification) tIH

(DC100)

100 – 95 – ps 29, 30

VREF @ 1 V/ns 200 – 195 – ps 20, 30

Minimum CTRL, CMD, ADDR pulse width tIPW 535 – 470 – ps 41

ACTIVATE to internal READ or WRITE delay tRCD See Speed Bin Tables (page 71) for tRCD ns 31

PRECHARGE command period tRP See Speed Bin Tables (page 71) for tRP ns 31

ACTIVATE-to-PRECHARGE command period tRAS See Speed Bin Tables (page 71) for tRAS ns 31, 32

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-1866 DDR3-2133

Unit NotesMin Max Min Max

ACTIVATE-to-ACTIVATE command period tRC See Speed Bin Tables (page 71) for tRC ns 31, 43

ACTIVATE-to-ACTIVATE

minimum command pe-

riod

1KB page size tRRD MIN = greater of 4CK or 5ns CK 31

2KB page size MIN = greater of 4CK or 6ns CK 31

Four ACTIVATE

windows

1KB page size tFAW 27 – 25 – ns 31

2KB page size 35 – 35 – ns 31

Write recovery time tWR MIN = 15ns; MAX = n/a ns 31, 32,

Delay from start of internal WRITE transac-

tion to internal READ command

tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34

READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32

CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK

Auto precharge write recovery + precharge

time

tDAL MIN = WR + tRP/tCK (AVG); MAX = n/a CK

MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK

MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK

MULTIPURPOSE REGISTER READ burst end to

mode register set for multipurpose register

exit

tMPRR MIN = 1CK; MAX = n/a CK

Calibration Timing

ZQCL command: Long

calibration time

POWER-UP and RE-

SET operation

tZQinit MIN = n/a

MAX = max(512nCK, 640ns)

Normal operation tZQoper MIN = n/a

MAX = max(256nCK, 320ns)

ZQCS command: Short calibration time MIN = n/a

MAX = max(64nCK, 80ns) tZQCS

Initialization and Reset Timing

Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK

Begin power supply ramp to power supplies

stable

tVDDPR MIN = n/a; MAX = 200 ms

RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms

RESET# LOW to I/O and RTT High-Z tIOZ MIN = n/a; MAX = 20 ns 35

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-1866 DDR3-2133

Unit NotesMin Max Min Max

Refresh Timing

REFRESH-to-ACTIVATE or REFRESH

command period

tRFC – 1Gb MIN = 110; MAX = 70,200 ns

tRFC – 2Gb MIN = 160; MAX = 70,200 ns

tRFC – 4Gb MIN = 260; MAX = 70,200 ns

tRFC – 8Gb MIN = 350; MAX = 70,200 ns

Maximum refresh

period

TC ≤ 85°C – 64 (1X) ms 36

TC > 85°C 32 (2X) ms 36

Maximum average

periodic refresh

TC ≤ 85°C tREFI 7.8 (64ms/8192) μs 36

TC > 85°C 3.9 (32ms/8192) μs 36

Self Refresh Timing

Exit self refresh to commands not requiring a

locked DLL

tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK

Exit self refresh to commands requiring a

locked DLL

tXSDLL MIN = tDLLK (MIN);

MAX = n/a

CK 28

Minimum CKE low pulse width for self re-

fresh entry to self refresh exit timing

tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK

Valid clocks after self refresh entry or power-

down entry

tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK

Valid clocks before self refresh exit,

power-down exit, or reset exit

tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK

Power-Down Timing

CKE MIN pulse width tCKE (MIN) Greater of 3CK or 5ns CK

Command pass disable delay tCPDED MIN = 2;

MAX = n/a

Power-down entry to power-down exit tim-

ing

tPD MIN = tCKE (MIN);

MAX = 9 * tREFI

Begin power-down period prior to CKE

registered HIGH

tANPD WL - 1CK CK

Power-down entry period: ODT either

synchronous or asynchronous

PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK

Power-down exit period: ODT either

synchronous or asynchronous

PDX tANPD + tXPDLL CK

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-1866 DDR3-2133

Unit NotesMin Max Min Max

Power-Down Entry Minimum Timing

ACTIVATE command to power-down entry tACTPDEN MIN = 2 CK

PRECHARGE/PRECHARGE ALL command to

power-down entry

tPRPDEN MIN = 2 CK

REFRESH command to power-down entry tREFPDEN MIN = 2 CK 37

MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK

READ/READ with auto precharge command

to power-down entry

tRDPDEN MIN = RL + 4 + 1 CK

WRITE command to

power-down entry

BL8 (OTF, MRS)

BC4OTF

tWRPDEN MIN = WL + 4 +

tWR/tCK (AVG)

BC4MRS tWRPDEN MIN = WL + 2 +

tWR/tCK (AVG)

WRITE with auto pre-

charge command to

power-down entry

BL8 (OTF, MRS)

BC4OTF

tWRAP-

DEN

MIN = WL + 4 + WR + 1 CK

BC4MRS tWRAP-

DEN

MIN = WL + 2 + WR + 1 CK

Power-Down Exit Timing

DLL on, any valid command, or DLL off to

commands not requiring locked DLL

tXP MIN = greater of 3CK or 6ns;

MAX = n/a

Precharge power-down with DLL off to

commands requiring a locked DLL

tXPDLL MIN = greater of 10CK or 24ns; MAX = n/a CK 28

ODT Timing

RTT synchronous turn-on delay ODTL on CWL + AL - 2CK CK 38

RTT synchronous turn-off delay ODTL off CWL + AL - 2CK CK 40

RTT turn-on from ODTL on reference tAON –195 195 –180 180 ps 23, 38

RTT turn-off from ODTL off reference tAOF 0.3 0.7 0.3 0.7 CK 39, 40

Asynchronous RTT turn-on delay

(power-down with DLL off)

tAONPD MIN = 2; MAX = 8.5 ns 38

Asynchronous RTT turn-off delay

(power-down with DLL off)

tAOFPD MIN = 2; MAX = 8.5 ns 40

ODT HIGH time with WRITE command and

BL8

ODTH8 MIN = 6; MAX = n/a CK

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)

Notes 1–8 apply to the entire table

Parameter Symbol

DDR3-1866 DDR3-2133

Unit NotesMin Max Min Max

ODT HIGH time without WRITE command or

with WRITE command and BC4

ODTH4 MIN = 4; MAX = n/a CK

Dynamic ODT Timing

RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK

RTT(WR)-to-RTT,nom change skew - BC4 ODTLcwn4 4CK + ODTLoff CK

RTT(WR)-to-RTT,nom change skew - BL8 ODTLcwn8 6CK + ODTLoff CK

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 CK 39

Write Leveling Timing

First DQS, DQS# rising edge tWLMRD 40 – 40 – CK

DQS, DQS# delay tWLDQSEN 25 – 25 – CK

Write leveling setup from rising CK, CK#

crossing to rising DQS, DQS# crossing

tWLS 140 – 125 – ps

Write leveling hold from rising DQS, DQS#

crossing to rising CK, CK# crossing

tWLH 140 – 125 – ps

Write leveling output delay tWLO 0 7.5 0 7 ns

Write leveling output error tWLOE 0 2 0 2 ns

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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Notes: 1. AC timing parameters are valid from specified TC MIN to TC MAX values.

2. All voltages are referenced to VSS.

3. Output timings are only valid for RON34 output buffer selection.

4. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.

The unit CK represents one clock cycle of the input clock, counting the actual clock

edges.

5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environ-

ment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the

AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum

slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs

(DQs are at 2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns for differential inputs in

the range between VIL(AC) and VIH(AC).

6. All timings that use time-based values (ns, μs, ms) should use tCK (AVG) to determine the

correct number of clocks (Table 57 (page 86) uses CK or tCK [AVG] interchangeably). In

the case of noninteger results, all minimum limits are to be rounded up to the nearest

whole integer, and all maximum limits are to be rounded down to the nearest whole

integer.

7. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is

the rising edge. Clock or CK refers to the CK and CK# differential crossing point when

CK is the rising edge.

8. This output load is used for all AC timing (except ODT reference timing) and slew rates.

The actual test load may be different. The output signal voltage reference point is

VDDQ/2 for single-ended signals and the crossing point for differential signals (see Fig-

ure 29 (page 68)).

9. When operating in DLL disable mode, Micron does not warrant compliance with normal

mode timings or functionality.

10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG)

MIN is the smallest clock rate allowed, with the exception of a deviation due to clock

jitter. Input clock jitter is allowed provided it does not exceed values specified and must

be of a random Gaussian distribution in nature.

11. Spread spectrum is not included in the jitter specification values. However, the input

clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with

an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread

spectrum may not use a clock rate below tCK (AVG) MIN.

12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 con-

secutive clocks and is the smallest clock half period allowed, with the exception of a de-

viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values

specified and must be of a random Gaussian distribution in nature.

13. The period jitter (tJITper) is the maximum deviation in the clock period from the average

or nominal clock. It is allowed in either the positive or negative direction.

14. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one

rising edge to the following falling edge.

15. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-

ing edge to the following rising edge.

16. The cycle-to-cycle jitter tJITcc is the amount the clock period can deviate from one cycle

to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL

locking time.

17. The cumulative jitter error tERRnper, where n is the number of clocks between 2 and 50,

is the amount of clock time allowed to accumulate consecutively away from the average

clock over n number of clock cycles.

18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns slew rate DQs (DQs are at

2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns slew rate differential DQS, DQS#.

2Gb: x4, x8, x16 DDR3 SDRAM

Electrical Characteristics and AC Operating Conditions

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19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-

tion edge to its respective data strobe signal (DQS, DQS#) crossing.

20. The setup and hold times are listed converting the base specification values (to which

derating tables apply) to VREF when the slew rate is 1 V/ns (DQs are at 2V/ns for

DDR3-1866 and DDR3-2133). These values, with a slew rate of 1 V/ns (DQs are at 2V/ns

for DDR3-1866 and DDR3-2133), are for reference only.

21. When the device is operated with input clock jitter, this parameter needs to be derated

by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output

deratings are relative to the SDRAM input clock).

22. Single-ended signal parameter.

23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-

rameters must be derated by the actual jitter error when input clock jitter is present,

even when within specification. This results in each parameter becoming larger. The fol-

lowing parameters are required to be derated by subtracting tERR10per (MAX): tDQSCK

(MIN), tLZDQS (MIN), tLZDQ (MIN), and tAON (MIN). The following parameters are re-

quired to be derated by subtracting tERR10per (MIN): tDQSCK (MAX), tHZ (MAX), tLZDQS

(MAX), tLZDQ (MAX), and tAON (MAX). The parameter tRPRE (MIN) is derated by sub-

tracting tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN).