MAX6901ETA-T - Maxim Integrated Products, Inc.

General Description

The MAX6901 3-wire serial interface real-time clock in a

TDFN package contains a real-time clock/calendar and

31 x 8 bits of static RAM (SRAM). The real-time

clock/calendar provides seconds, minutes, hours, day,

date, month, year, and century information. A

time/date-programmable polled ALARM is included in

the MAX6901. The end of the month date is automati-

cally adjusted for months with fewer than 31 days,

including corrections for leap year up to the year 2100.

The clock operates in either the 24hr or 12hr format

with an AM/PM indicator. A push-pull 32kHz output is

also included. The MAX6901 operates with a supply

voltage of +2V to +5.5V, is available in the ultra-small 8-

pin TDFN package, and works over the industrial tem-

perature range, -40°C to +85°C.

Applications

Point-of-Sale Equipment

Intelligent Instruments

Fax Machines

Battery-Powered Products

Portable Instruments

Features

♦Real-Time Clock Counts Seconds, Minutes,

Hours, Day of Week, Date of Month, Month, Year,

and Century

♦Leap-Year Compensation Valid up to Year 2100

♦Wide +2V to +5.5V Operating Voltage Range

♦3-Wire Serial Interface, 2MHz at 5V, 500kHz at 2V

♦31 x 8-Bit SRAM for Scratchpad Data Storage

♦Uses Standard 32.768kHz, 12.5pF Watch Crystal

♦Low Timekeeping Current (400nA at 2V)

♦Single-Byte or Multiple-Byte (Burst Mode)

Data Transfer for Read or Write of Clock

Registers or SRAM

♦8-Pin 3mm x 3mm x 0.8mm TDFN

Surface-Mount Package

♦Push-Pull 32.768kHz Clock Output

♦Programmable Time/Date Polled ALARM Function

♦No External Crystal Bias Resistors or Capacitors

Required

MAX6901

3-Wire Serial RTC in a TDFN

________________________________________________________________ Maxim Integrated Products 1

19-2085; Rev 2; 5/04

Ordering Information

PART TEMP

RANGE

PIN-

PACKAGE

TOP

MARK

MAX6901ETA-T -40°C to +85°C8 TDFN AGV

Related Real-Time Clock Products

PART SERIAL

INTERFACE ALARM

(bits) ALARM

FUNCTION OUTPUT

FREQUENCY PIN-PACKAGE

MAX6900 I2C™ compatible 31 x 8 — — 6 TDFN

MAX6901 3 wire 31 x 8 Polled 32kHz 8 TDFN

MAX6902 SPI™ compatible 31 x 8 Polled — 8 TDFN

Pin Configuration appears at end of data sheet.

Functional Diagram appears at end of data sheet.

µC

0.1µF

32.768kHz

CRYSTAL

3.3V

MAX6901

P1.0

CLKIN

P1.1

P1.2

SCLK

I/O

32KHZ

GND

VCC X1

Typical Operating Circuit

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

I2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated

Companies, conveys a license under the Philips I2C Patent rights to use these components in an I2C system provided that the system

conforms to the I2C Standard Specification as defined by Philips.

SPI is a trademark of Motorola, Inc.

MAX6901

3-Wire Serial RTC in a TDFN

2_______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VCC to GND.......................................................……-0.3V to +6V

All Other Pins to GND ................................-0.3V to (Vcc + 0.3V)

Current into Any Pin..........................................................±20mA

Rate-of-Rise, VCC ............................................................100V/µs

Continuous Power Dissipation (TA= +70°C)

8-Pin TDFN (derate 24.4mW/°C above +70°C).........1951.0mW

Junction Temperature .....................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection (all pins, Human Body Model) ..................2000V

Lead Temperature (soldering, 10s) .................................+300°C

DC ELECTRICAL CHARACTERISTICS

(VCC = +2.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating Voltage Range VCC 2 5.5 V

VCC = +2.0V 110

Active Supply Current (Note 2) ICC VCC = +5V 800 µA

VCC = +2.0V 0.4 0.7

Timekeeping Supply Current

(Note 3) ITK VCC = +5V 1.4 2.2 µA

32kHz OUTPUT

VCC = +2.0V, ISOURCE = -0.4mA 1.8

Output High Voltage (Note 5) VOH VCC = +5.0V, ISOURCE = -1mA 4.5 V

VCC = +2.0V, ISINK = 1.5mA 0.4

Output Low Voltage (Note 5) VOL VCC = +5.0V, ISINK = 4mA 0.4 V

Duty Cycle 40 %

Output Leakage Current VIN = 0 to VCC, 32kHz output disabled -10 10 nA

3-WIRE DIGITAL INPUTS AND OUTPUTS (SCLK, I/O, CS)

VCC = +2.0V 1.4

Input High Voltage VIH VCC = +5.0V 2.2 V

VCC = +2.0V 0.6

Input Low Voltage VIL VCC = +5.0V 0.8 V

Input Leakage Current VIN = 0 to VCC -10 10 nA

SCLK, RST Capacitance 5pF

I/O Capacitance 10 pF

VCC = +2.0V, ISINK = 1.5mA 0.4

I/O Output Low Voltage VOL VCC = +5.0V, ISINK = 4mA 0.4 V

VCC = +2.0V, ISOURCE = -0.4mA 1.8

I/O Output High Voltage VOH VCC = +5.0V, ISOURCE = -1mA 4.5 V

MAX6901

3-Wire Serial RTC in a TDFN

_______________________________________________________________________________________ 3

Note 1: All parameters are 100% tested at TA= +25°C. Limits over temperature are guaranteed by design and not production tested.

Note 2: ICC is specified with the I/O grounded, CS high, SCLK = 2MHz at VCC = +5V; SCLK = 500kHz at VCC = +2.0V, 32kHz output

enabled, and no load on 32kHz output.

Note 3: Timekeeping current is specified with CS = GND, SCLK = GND, I/O = GND, 32kHz = GND, and 32kHz disabled.

Note 4: All values referred to VIH min and VIL max levels.

Note 5: Guaranteed by design. Not production tested.

AC ELECTRICAL CHARACTERISTICS

(VCC = +2.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA= +25°C.) (Figures 4, 5

and Notes 1, 4)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OSCILLATOR

X1 to Ground Capacitance (Note 5) 25 pF

X2 to Ground Capacitance (Note 5) 25 pF

3-WIRE SERIAL TIMING

VCC = +2V 200

Data to CLK Setup tDC VCC = +5V 50 ns

VCC = +2V 280

CLK to Data Hold tCDH VCC = +5V 70 ns

VCC = +2V 800

CLK to Data Delay tCDD CL = 50pF VCC = +5V 200 ns

VCC = +2V 1000

CLK Low Time tCL VCC = +5V 250 ns

VCC = +2V 1000

CLK High Time tCH VCC = +5V 250 ns

VCC = +2V DC 0.5

CLK Frequency fCLK VCC = +5V DC 2.0 MHz

VCC = +2V 2000

CLK Rise and Fall Time tR, tFVCC = +5V 500 ns

VCC = +2V 4

CS to CLK Setup tCC VCC = +5V 1 µs

VCC = +2V 240

CLK to CS Hold tCCH VCC = +5V 60 ns

VCC = +2V 4

CS Inactive Time tCWH VCC = +5V 1 µs

VCC = +2V 0 280

CS to I/O High Z tCDZ RL = 1kΩ, CL = 60pF VCC = +5V 0 70 ns

VCC = +2V 0 280

SCLK to I/O High Z tCCZ RL = 1kΩ, CL = 60pF VCC = +5V 0 70 ns

MAX6901

Detailed Description

The MAX6901 is a real-time clock/calendar with a 3-wire

serial interface and 31 ✕8 bits of SRAM. It provides sec-

onds, minutes, hours, day of the week, date of the

month, month, and year information, held in seven 8-bit

timekeeping registers (Functional Diagram). An on-chip

32.768kHz oscillator circuit does not require any exter-

nal resistors or capacitors to operate. Table 1 specifies

the parameters for the external crystal, and Figure 1

shows a functional schematic of the oscillator circuit.

The MAX6901’s register addresses and definitions are

described in Tables 2 and 3. Time and calendar data

are stored in the registers in binary coded decimal

(BCD) format. A polled alarm function is included for

scheduled timing of user-defined times or intervals.

Command and Control

Address/Command Byte

Each data transfer into or out of the MAX6901 is initiat-

ed by an Address/Command byte. The Address/

Command byte specifies which registers are to be

accessed, and if the access is a read or a write. Table

2 shows the Address/Command bytes and their associ-

ated registers, and Table 3 lists the hex codes for all

read and write operations. The Address/Command

bytes are input LSB (bit 0) first. Bit 0 specifies a write

(logic 0) or read (logic 1). Bits 1 to 5 specify the desig-

nated register to be written or read. Bit 6 specifies reg-

ister data (logic 0), or RAM data (logic 1). The MSB (bit

7) must be logic 1. If the MSB is a zero, writes to the

MAX6901 are disabled.

3-Wire Serial RTC in a TDFN

4_______________________________________________________________________________________

Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

0.1 2.0 2.5 3.5 4.0 5.54.5 5.03.0

TIMEKEEPING CURRENT

vs. SUPPLY VOLTAGE

1.0

10.0

MAX6901 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

PIN NAME FUNCTION

1SCLK Serial Clock Input. 3-wire serial clock for I/O data transfers.

CC Power-Supply Pin. Bypass VCC to GND with a 0.1µF capacitor.

3X2External 32.768kHz Crystal Connection

4X1External 32.768kHz Crystal Connection

532KHZ Buffered Push-Pull 32.768kHz Output. When enabled, 32KHZ puts a buffered version of the timekeeping clock.

When disabled, 32KHZ is high impedance. The power-on reset (POR) default state of 32KHZ is enabled.

6GND Ground Connection

7CSChip-Select Input. Active-high for valid data transfers.

8I/O Data Input/Output. 3-wire serial data input/output connection.

—PAD Ground

Pin Description

Clock Burst Mode

Accessing the Clock Burst register specifies burst-

mode operation. In this mode, multiple bytes are read

or written with a single Address/Command write. If the

Clock Burst register is accessed (BEh for Write and

BFh for Read), the first seven clock/calendar registers

(Seconds, Minutes, Hours, Date, Month, Day, and Year)

and the Control register, are consecutively read or writ-

ten, starting with the LSB of the Seconds register. When

writing to the clock registers in burst mode, all seven

registers must be written in order for the data to be

transferred (see Example: Setting the Clock with a

Burst Write).

RAM Burst Mode

Sending the RAM Burst Address/Command specifies

Burst-Mode operation. In this mode, the 31 RAM regis-

ters can be consecutively read or written, starting with

bit 0 of address C0h for Writes, and C1h for Reads.

Burst Read outputs all 31 registers of RAM. When writ-

ing to RAM in burst mode, it is not necessary to write all

31 bytes for the data to transfer; each complete byte

written is transferred to RAM. When reading from RAM,

data bits are output until all 31 bytes have been read,

or until CS is driven low.

Setting the Clock

Writing to the Timekeeping Registers

The Time and Date are set by writing to the timekeep-

ing registers (Seconds, Minutes, Hours, Date, Month,

Day, Year, and Century). During a write operation, an

input buffer accepts the new time data while the time-

keeping registers continue to increment normally,

based on the crystal counter. The buffer also keeps the

timekeeping registers from changing as the result of an

incomplete Write operation, and collision detection cir-

cuitry ensures that a time write does not occur coinci-

dent with a Seconds register increment. The updated

time data are loaded into the timekeeping registers on

the falling edge of CS, at the end of the 3-wire serial

Write operation. An incomplete Write operation aborts

the update procedure, and the contents of the input

buffer are discarded. The timekeeping registers reflect

the new time, beginning with the first Seconds register

increment after the falling edge of CS.

Although both Single Writes and Burst Writes are possi-

ble, the best way to write to the timekeeping registers is

with a Burst Write. With a Burst Write, main timekeeping

registers (Seconds, Minutes, Hours, Date, Month, Day,

Year), and the Control register are written sequentially

following the Address/Command byte. They must be

written as a group of eight registers, with 8 bits each,

for proper execution of the Burst Write function. All

seven timekeeping registers are simultaneously loaded

into the clock counters by the falling edge of CS, at the

end of the 3-wire serial Write operation. For a normal

burst data transfer, the worst-case error that can occur

between the actual time and the written time update is

1 second.

If Single Write operations are used to enter data into the

timekeeping registers, error checking is required. If the

Seconds register is not to be written, then begin by

reading the Seconds register and save it as initial-sec-

onds. Write to the required timekeeping registers and

MAX6901

3-Wire Serial RTC in a TDFN

_______________________________________________________________________________________ 5

Figure 1. Oscillator Circuit Schematic

25pF

EXTERNAL

CRYSTAL

X1 X2

MAX6901

PARAMETER SYMBOL MIN TYP MAX UNITS

Frequency f 32.76 kHz

Equivalent Series Resistance (ESR) Rs40 60 kΩ

Parallel Load Capacitance CL11.2 12.5 13.7 pF

Q Factor Q 40,000 60,000

Table 1. Acceptable Quartz Crystal Parameters

MAX6901

then read the Seconds register again (final-seconds).

Check to see that final-seconds is equal to initial-sec-

onds. If not, repeat the write process. If the Seconds

first, and then read it back and store its value (initial-

seconds). Update the remaining timekeeping registers

and then read the Seconds register again (final-sec-

3-Wire Serial RTC in a TDFN

6_______________________________________________________________________________________

Table 2. Register Address/Definition

FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 D6 D5 D4 D3 D2 D1 D0

TIMEKEEPING

00-59 32kHz

EN 10 SEC 1 SEC

SECOND 1000000RD

/W *POR STATE 0 0 0 0 0000

00-59 ALM

OUT 10 MIN 1 MIN

MINUTE 1000001RD

/W *POR STATE 000 00000

00-23 12/24 10

HOUR 1000010RD

/W 01-12 1/0

0A/P

0/1

HR 1 HR

*POR STATE 0 0 0 00000

01-28/29

01-30

01-31

0 0 10 DATE 1 DATE

DATE 1000011RD

*POR STATE 0 0 000001

01-12 0 0 0 10M 1 MONTH

MONTH 1000100RD

/W *POR STATE 0 0 0 0 0001

01-07 0 0 0 0 0 WEEKDAY

DAY 1000101RD

/W *POR STATE 0 0 0 0 0 001

00-99 10 YEAR 1 YEAR

YEAR 1000110RD

/W *POR STATE 0 1 1 1 0 0 0 0

WP 0 0 0 0 0 0 0

CONTROL 1000111RD

/W *POR STATE 0 0 0 0 0 0 0 0

00-99 1000 YEAR 100 YEAR

CENTURY 1001001RD

/W *POR STATE 0 0 0 1 1 0 0 1

Note: *POR STATE defines power-on reset state of register content.

MAX6901

3-Wire Serial RTC in a TDFN

_______________________________________________________________________________________ 7

Table 2. Register Address/Definition (continued)

FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 D6 D5 D4 D3 D2 D1 D0

YEAR

DAY

MONTH

DATE

HOUR

MINUTE

SECOND

ALARM

CONFIG 1001010RD

*POR STATE 0 0 0 0 0 0 0 0

RESERVED 0 0 0 0 0 1 1 1

Do not write

to this location.

1001011RD

/W *POR STATE 00000111

ALARM

THRESHOLDS

00-59 010 SEC 1 SEC

SECOND 1001100RD

/W *POR STATE 0 1 1 1 1111

00-59 010 MIN 1 MIN

MINUTE 1001101RD

/W *POR STATE 011 11111

00-23 12/24 10

HOUR 1001110RD

/W 01-12 1/0

0A/P

0/1

HR 1 HR

*POR STATE 1 0 1 11111

01-28/29

01-30

01-31

0 0 10 DATE 1 DATE

DATE 1001111RD

*POR STATE 0 0 111111

01-12 0 0 0 10 M 1 MONTH

MONTH 1010000RD

/W *POR STATE 0 0 0 11111

01-07 0 0 0 0 0 WEEKDAY

DAY 1010001RD

/W *POR STATE 0 0 0 0 0 111

00-99 10 YEAR 1 YEAR

YEAR 1010010RD

/W *POR STATE 1 1 1 1 1111

CLOCK

BURST 1011111RD

Note: *POR STATE defines power-on reset state of register content.

MAX6901

onds). Check to see that final-seconds is equal to ini-

tial-seconds. If not, repeat the write process.

Note: After writing to any time or date register, no read

or write operations are allowed for 45µs.

AM/PM and 12Hr/24Hr Mode

Bit 7 of the Hours register selects 12hr or 24hr mode.

When high, 12hr mode is selected. In 12hr mode, bit 5 is

the AM/PM bit, logic high for PM. In 24hr mode, bit 5 is

the second 10hr bit, logic high for hours 20 through 23.

Write-Protect Bit

Bit 7 of the Control register is the write-protect bit.

When high, the write-protect bit prevents write opera-

tions to all registers except itself. After initial settings

are written to the timekeeping registers, set the write-

protect bit to logic 1 to prevent erroneous data from

entering the registers during power glitches or inter-

rupted serial transfers. The lower 7 bits (bits 0–6) are

unusable, and always read zero. Any data written to

bits 0–6 are ignored. Bit 7 must be set to zero before a

single byte write to the clock, before a write to RAM, or

during a burst write to the clock.

Example: Setting the Clock

with a Burst Write

To set the clock with a Burst Write operation to

10:11:31PM, Thursday July 4th, 2002, write BEh as

Address/Command byte, followed by 8 bytes, B1h,

11h, B0h, 04h, 07h, 04h, 02h, and 00h (Table 2). BEh

accesses the Clock Burst Write register. The first byte,

B1h, sets the Seconds register to 31, and disables the

32.768kHz output. The second byte, 11h, sets the

Minutes register to 11. The third byte, B0h, sets the

Hours register to 12hr mode, and 10PM. The fourth

byte, 04h, sets the Date register (day of the month) to

the 4th. The fifth byte, 07h, sets the Month register to

July. The sixth byte, 04h, sets the Day register (day of

the week) to Thursday. The seventh byte, 02h, sets the

Year register to 02. The eighth byte, 00h, clears the

write-protect bit of the Control register to allow writing to

the MAX6901. The Century register is not accessed

with a Burst Write and therefore must be written to sep-

arately to set the century to 20. Note the Century regis-

ter corresponds to the thousand and hundred digits of

the current year and defaults to 19.

Reading the Clock

Reading the Timekeeping Registers

The main timekeeping registers (Seconds, Minutes,

Hours, Date, Month, Day, Year) can be read with either

Single Reads or a Burst Read. In the MAX6901, a latch

buffers each clock counter’s data. Clock counter data

are latched by the 3-wire serial Read command (on the

falling edge of SCLK, after the Address/Command byte

has been sent by the Master to read a timekeeping reg-

ister). Collision-detection circuitry ensures that this

3-Wire Serial RTC in a TDFN

8_______________________________________________________________________________________

Table 2. Register Address/Definition (continued)

FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 D6 D5 D4 D3 D2 D1 D0

RAM

RAM 0 1100000RD

/W RAM DATA 0 xxxxxxxx

•• ••

RAM 30 1111110RD

/W RAM DATA 30 xxxxxxxx

RAM BURST 1111111RD

Note: *POR STATE defines power-on reset state of register content.

MAX6901

3-Wire Serial RTC in a TDFN

_______________________________________________________________________________________ 9

WRITE

ADDRESS/COMMAND

BYTE (HEX)

READ

ADDRESS/COMMAND

BYTE (HEX) DESCRIPTION POR CONTENTS

(HEX)

80 81 SECONDS 00

82 83 MINUTES 00

84 85 HOUR 00

86 87 DATE 01

88 89 MONTH 01

8A 8B DAY 01

8C 8D YEAR 70

8E 8F CONTROL 00

90 91 RESERVED Nonapplicable

92 93 CENTURY 19

94 95 ALARM CONFIGURATION 00

96 97 RESERVED 07

98 99 SECONDS ALARM THRESHOLD 7F

9A 9B MINUTES ALARM THRESHOLD 7F

9C 9D HOURS ALARM THRESHOLD BF

9E 9F DATE ALARM THRESHOLD 3F

A0 A1 MONTH ALARM THRESHOLD 1F

A2 A3 DAY ALARM THRESHOLD 07

A4 A5 YEAR ALARM THRESHOLD FF

BE BF CLOCK BURST Nonapplicable

C0 C1 RAM 0 Indeterminate

C2 C3 RAM 1 Indeterminate

C4 C5 RAM 2 Indeterminate

C6 C7 RAM 3 Indeterminate

C8 C9 RAM 4 Indeterminate

CA CB RAM 5 Indeterminate

CC CD RAM 6 Indeterminate

CE CF RAM 7 Indeterminate

D0 D1 RAM 8 Indeterminate

D2 D3 RAM 9 Indeterminate

D4 D5 RAM 10 Indeterminate

D6 D7 RAM 11 Indeterminate

D8 D9 RAM 12 Indeterminate

DA DB RAM 13 Indeterminate

DC DD RAM 14 Indeterminate

DE DF RAM 15 Indeterminate

E0 E1 RAM 16 Indeterminate

E2 E3 RAM 17 Indeterminate

Table 3. HEX Register Address/Description

MAX6901

does not happen coincident with a Seconds counter

increment to ensure accurate time data is being read.

The clock counters continue to count and keep accu-

rate time during the Read operation.

The simplest way to read the timekeeping registers is to

use a Burst Read. In a Burst Read, the main timekeep-

ing registers (Seconds, Minutes, Hours, Date, Month,

Day, Year) and the Control register are read sequential-

ly in the order listed with the Seconds register first.

They are read out as a group of eight registers, with 8

bits each. All timekeeping registers (except Century)

are latched upon the receipt of the Burst Read com-

mand. The worst-case error between the “actual” time

and the “read” time is 1 second for a normal data transfer.

The timekeeping registers may also be read using

Single Reads. If Single Reads are used, it is necessary

to do some error checking on the receiving end,

because it is possible that the clock counters could

change during the Read operations, and report inaccu-

rate time data. The potential for error is when the

Seconds register increments before all the registers are

read. For example, suppose a carry of 13:59:59 to

14:00:00 occurs during Single Read operations. The

net data read could be 14:59:59, which is erroneous.

To prevent errors from occurring with Single Read oper-

ations, read the Seconds register first (initial-seconds)

and store this value for future comparison. After the

remaining timekeeping registers have been read,

reread the Seconds register (final-seconds). Check that

the final-seconds value equals the initial-seconds value;

if not, repeat the entire Single Read process. Using

Single Reads at a 100kHz serial speed, it takes under

2.5ms to read all seven of the timekeeping registers,

including two reads of the Seconds register.

Example: Reading the Clock

with a Burst Read

To read the time with a Burst Read, send BFh as the

Address/Command byte. Then clock out 8 bytes,

Seconds, Minutes, Hours, Date of the month, Month,

Day of the week, Year, and finally the Control byte. All

data are output LSB first. Decode the required informa-

tion based on the register definitions listed in Table 2.

Using the Alarm

A polled alarm function is available by reading the ALM

OUT bit. The ALM OUT bit is D7 of the Minutes time-

keeping register. A logic 1 in ALM OUT indicates the

alarm function is triggered. There are eight registers

associated with the alarm function, seven programma-

ble Alarm Threshold registers and one programmable

Alarm Configuration register. The Alarm Configuration

are compared to the timekeeping registers, and the

ALM OUT bit sets if the compared registers are equal.

Table 2 shows the function of each bit of the Alarm

Configuration register. Placing a logic 1 in any given bit

of the Alarm Configuration register enables the respec-

3-Wire Serial RTC in a TDFN

10 ______________________________________________________________________________________

WRITE

ADDRESS/COMMAND

BYTE (HEX)

READ

ADDRESS/COMMAND

BYTE (HEX) DESCRIPTION POR CONTENTS

(HEX)

E4 E5 RAM 18 Indeterminate

E6 E7 RAM 19 Indeterminate

E8 E9 RAM 20 Indeterminate

EA EB RAM 21 Indeterminate

EC ED RAM 22 Indeterminate

EE EF RAM 23 Indeterminate

F0 F1 RAM 24 Indeterminate

F2 F3 RAM 25 Indeterminate

F4 F5 RAM 26 Indeterminate

F6 F7 RAM 27 Indeterminate

F8 F9 RAM 28 Indeterminate

FA FB RAM 29 Indeterminate

FC FD RAM 30 Indeterminate

FE FF RAM Burst Nonapplicable

Table 3. HEX Register Address/Description (continued)

tive alarm function. For example, if the Alarm

Configuration register is set to 0000 0011, ALM OUT is

set when both the minutes and seconds indicated in

the Alarm Threshold registers match the respective

timekeeping registers. Once set, ALM OUT stays high

until it is cleared by reading or writing to the Alarm

Configuration register, or by reading or writing to any of

the Alarm Threshold registers. The Alarm Configuration

read with Address/Command 95h.

Using the On-Board RAM

The static RAM is 31 x 8 bits addressed consecutively

in the RAM address space. Even-addressed com-

mands (C0h–FCh) are used for Writes, and odd-

addressed commands (C1h–FDh) are used for Reads.

The contents of the RAM are static and remain valid for

VCC down to 2V. All RAM data are lost if power is

cycled. The write-protect bit (bit 7 of the Control regis-

ter), when high, disallows any changes to RAM.

3-Wire Serial Interface

Interfacing the MAX6901 with a microcontroller is

accomplished by using a 3-wire, synchronous, serial

interface. Required to communicate are a Chip Select

signal (CS), a Serial Clock signal (SCLK), and a Data

line (I/O).

All data transfers are framed by the CS signal that must

be active-high for any data transfer to occur. At the

beginning of any data transfer (rising edge of CS),

SCLK should be low. This prevents the MAX6901 from

misinterpreting the transition of CS as a high-to-low

transition of SCLK (if SCLK were to be left high when

CS transitions from a low to high). The first 8 bits sent

after CS is pulled high by the microcontroller comprise

the Address/Command Byte, which tells the MAX6901

if the data transfer is a read or a write, and which regis-

ter is read to or written from. Data are clocked into the

MAX6901, through the I/O pin, on the rising edges of

SCLK, and data are clocked out on the falling edge of

SCLK. Data format is always LSB first to MSB last.

When CS is low, I/O is high impedance.

Single data transfer timing is shown in Figure 2. Burst-

mode data transfer timing is shown in Figure 3.

Detailed Read and Write timing diagrams are shown in

Figures 4 and 5, respectively.

Chip Select

CS serves two functions. First, CS turns on the control

logic that allows access to the Shift register for

Address/Command and data transfer. Second, CS pro-

vides a method of terminating either single-byte or mul-

tiple-byte data transfers. All data transfers are initiated

by driving CS high. If CS is low, I/O is high impedance.

At power-up, CS must be low until VCC ≥2.0V.

Serial Clock

A clock cycle on SCLK is a rising edge followed by a

falling edge. For data input, data must be valid at I/O

during the rising edge of the clock. For data outputs,

bits are valid on I/O after the falling edge of clock. Also,

SCLK must be low when CS is driven high.

Data Input (Single-Byte Write)

Following the eight SCLK cycles that input a Single-

Byte Write Address/Command, data bits are input on

the rising edges of the next eight SCLK cycles.

Additional SCLK cycles are ignored. Input data LSB first.

Data Input (Burst Write)

Following the eight SCLK cycles that input a Burst Write

Address/Command, data bits are input on the rising

edges of the following SCLK cycles. The number of

clock cycles depends on whether the timekeeping reg-

isters or RAM are being written. A clock Burst Write

requires an Address/Command byte, 7 timekeeping

data bytes, and 1 Control register byte. A Burst Write to

RAM may be terminated after any complete data byte

by driving CS low. Input data LSB first (Figures 3 and 5).

Data Output (Single-Byte Read

and Burst Read)

A read from the MAX6901 is initiated by an Address/

Command Write from the microcontroller (master) to the

MAX6901 (slave). The Address/Command Write portion

of the data transfer is clocked into the MAX6901 on ris-

ing clock edges. On the eighth rising SCLK edge, the

last bit of the Address/Command Byte is clocked into

the MAX6901. After tCDH (CLK to Data Hold time,

Figure 4), the microcontroller must release the data

line. On the eighth falling edge of SCLK, the MAX6901

takes control of the data line and begins to output data.

The MAX6901 outputs data on the falling edge of SCLK

after tCDD (CLK to Data Delay time, Figure 4). On the

next rising edge of SCLK, I/O goes to high impedance

after tCCZ (which is specified with a maximum time).

Minimum time for tCCZ can be 0ns. Since the I/O line

can go to high impedance on the rising edge of SCLK,

it is best to read the data from the MAX6901 before the

rising edge of SCLK but after tCDD (CLK to Data Delay

time). This is best accomplished through the microcon-

troller I/O port pins by writing a low to SCLK, waiting

tCDD (CLK to Data Delay time), reading the MAX6901

I/O pin, and then writing a high to SCLK. Data bytes are

output LSB first. Additional SCLK cycles transmit addi-

tional data bits, as long as CS remains high. This per-

mits continuous burst-mode read capability.

MAX6901

3-Wire Serial RTC in a TDFN

______________________________________________________________________________________ 11

MAX6901

32.768kHz Output (32KHZ)

32KHZ is a push-pull 32.768kHz output for timing or

clocking of external devices. Bit D7 in the Clock

Seconds register is the active-low enable bit for 32KHZ.

When D7 is logic 0, 32KHZ is enabled. When logic 1,

32KHZ is disabled and set to high impedance. Power-

on reset enables the 32.768kHz output.

Applications Information

Crystal Selection

The MAX6901 is designed to use a standard 32.768kHz

watch crystal. Table 1 details the recommended crystal

requirements. Some suggested crystals are listed in

Table 4. In addition to the specified SMT devices, some

of the listed manufacturers also offer other package

options.

Frequency Stability and Temperature

Timekeeping accuracy of the MAX6901 is dependent

on the frequency stability of the external crystal. To

determine frequency stability, use the parabolic curve

in Figure 6 and the following equations:

∆f = fk (T0- T)2

where:

∆f = change in frequency from +25°C

3-Wire Serial RTC in a TDFN

12 ______________________________________________________________________________________

Figure 2. Single Byte Data Transfer

SCLK

A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7

I/O

ADDRESS/COMMAND BYTE I/O DATA BYTE

11A1 A2 A3 A4 A5 R

R = RAM/ REGISTER SELECT BIT

RAM = 1, REGISTER = 0

ADDRESS/COMMAND BYTE

(b) 3-WIRE SINGLE BYTE WRITE:

(a) 3-WIRE SINGLE BYTE READ:

I/O DATA BYTE

A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6

SCLK

I/O

A1 A2 A3 A4 A5 R 1

R = RAM/ REGISTER SELECT BIT

RAM = 1, REGISTER = 0

f=nominal crystal frequency

k=parabolic curvature constant (-0.035ppm/°C2

±0.005ppm/°C2 for 32.768kHz watch crystals)

T0=turnover temperature (+25°C ±5°C for 32.768kHz

watch crystals)

T=temperature of interest (°C)

For example: What is the worst-case change in oscilla-

tor frequency from +25°C ambient to +45°C ambient?

∆fdrift = 32,768 ✕ (-0.04 ✕ (1 ✕ 10-6)) ✕ (20-45)2

= -0.8192Hz

What is the worst-case timekeeping error per second?

Error due to temperature drift:

∆tdrift = {[1 / [(f+∆fdrift) / 32768]]-1s} / 1s

∆tdrift = {[1 / [(32768 - 0.8192) / 32768]]-1}/1s

= 0.000025s/s

Error due to +25°C initial crystal tolerance of ±20ppm:

∆finitial = 32,768 ✕ (-20 ✕ ((1 ✕ 10-6)) = -0.65536Hz

∆tinitial = {[1 / [(f+∆finitial) / 32768]]-1s} / 1s

∆tinitial = {[1 / [(32768-0.65536) / 32768]]-1} / 1s

= 0.000025s/s

Total timekeeping error per second:

MAX6901

3-Wire Serial RTC in a TDFN

______________________________________________________________________________________ 13

Figure 3. Burst Mode Data Transfer

A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7

SCLK

I/O

ADDRESS/COMMAND BYTE I/O DATA BYTE 1

D0 D1 D2 D3 D4 D5 D6 D7

I/O DATA BYTE N

R1 11111 1

N = 8 FOR TIMEKEEPING REGISTER BURST

N = 31 MAX FOR RAM BURST

A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6

SCLK

I/O

D7 D0 D1 D2 D3 D4 D5 D6 D7

0111 11R1

R = RAM/ REGISTER SELECT BIT

RAM = 1, REGISTER = 0

R = RAM/ REGISTER SELECT BIT

RAM = 1, REGISTER = 0

ADDRESS/COMMAND BYTE I/O DATA BYTE 1 I/O DATA BYTE N

N = 8 FOR TIMEKEEPING REGISTER BURST

N = 31 MAX FOR RAM BURST

(b) 3-WIRE BURST WRITE:

()

MAX6901

∆ttotal = ∆tdrift + ∆tinitial

∆ttotal = 0.00002+0.000025=0.000045s/s

After 1 month, that translates to:

Total worst-case timekeeping error at the end of 1

month at +45°C is about 120s or 2 min (assumes negli-

gible parasitic layout capacitance).

Oscillator Start Time

The MAX6901 oscillator typically takes 5s to 10s to

begin oscillating. To ensure the oscillator is operating

correctly, the software should validate proper time-

keeping. This is accomplished by reading the Seconds

of zero is a validation of proper startup.

Power-On Reset

The MAX6901 contains an integral POR circuit that

ensures all registers are reset to a known state on

power-up. Once VCC rises above 1.6V (typ), the POR

circuit releases the registers for normal operation. When

∆t days hr

day hr

ss s

()

×







×







×







×

()

31 24 60 60

0 00045 120 528

min

./.

3-Wire Serial RTC in a TDFN

14 ______________________________________________________________________________________

Figure 4. 3-Wire Read Data Transfer Serial Timing Diagram

01701

SCLK

I/O

tCC

tDC tCDD

tCDZ

tCDD

tCCZ

tCDH

READ ADDRESS/COMMAND BYTE READ DATA BIT

Figure 5. 3-Wire Write Data Transfer Serial Timing Diagram

SCLK

I/O

tCC

tDC

tCDH

tCWH

tCL

tCDH

WRITE ADDRESS/COMMAND BYTE WRITE DATA BIT

tRtF

tCCH

017 0

VCC drops to less than 1.6V (typ), the MAX6901 resets

all register contents to the POR defaults (Table 2).

RESERVED Registers

Addresses/Commands 90h, 91h, 96h, and 97h are

reserved for factory testing ONLY. Do not write to these

registers. If inadvertent Writes are done to any of these

registers, cycle power to the MAX6901.

Power-Supply Considerations

For most applications, a 0.1µF capacitor from VCC to

GND provides adequate bypassing for the MAX6901. A

series resistor can be added to the supply line for oper-

ation in extremely harsh or noisy environments.

Timekeeping Current—Normal Operation

When I/O is high impedance (CS = low, or after each

rising-clock edge for a data output transfer), there is a

potential for increased timekeeping current (up to 100x)

if the I/O is allowed to float. If minimum timekeeping

current is desired, the microcontroller port pin should

be configured as an input with a weak pullup.

Alternatively, use a 100kΩor less pulldown or pullup

resistor (for microcontroller port pins with ≤1µA input

leakage).

There are similar considerations for 32KHZ if it is

placed in its high-impedance state. For lowest time-

keeping current, it should not be allowed to float. Force

it high or low, or terminate it with a pullup or pulldown

resistor.

Timekeeping Current—Battery Backup

Systems

Often times, an RTC is operated in a system with a

backup battery. A microprocessor supervisory circuit

with backup battery switchover, or other switching

arrangement, is used to switch power from VCC to

VBATT when VCC falls below a set threshold. Most of

these systems leave only the RTC and some SRAM to

run from VBATT. The microcontroller that communicates

with the RTC is powered only from VCC. When the

microcontroller is reset, its port pins typically become

high impedance. This essentially floats I/O, CS, and

SCLK on the MAX6901. There is a potential for

increased timekeeping current (up to x100) as VCC falls

through the linear region of the input gates for I/O,

SCLK, and CS. The duration of this effect depends on

the discharge rate of VCC. To minimize current draw

from VBATT in such systems, ensure that VCC falls

rapidly at power down. One option is a VCC discharge

resistor of 100kΩor less from VCC to ground. This also

ensures sufficient impedance when VCC is gone back

through the microcontroller’s ESD protection, to keep

I/O, SCLK, and CS from floating. Alternately, a 100kΩ

pulldown (for microcontroller port pins with ≤1µA input

leakage) on each pin (I/O, SCLK, and CS) ensures that

timekeeping current specifications are met during the

power switchover.

MAX6901

3-Wire Serial RTC in a TDFN

______________________________________________________________________________________ 15

Table 4. 32.768kHz Surface-Mount Watch Crystals

MANUFACTURER MANUFACTURER

PART NO. TEMP. RANGE CL (pF) +25°C FREQUENCY

TOLERANCE (ppm)

Abracon Corporation ABS25-32.768-12.5-B-2-T -40°C to +85°C 12.5 ±20

Caliber Electronics AWS2A-32.768kHz, -20°C to +70°C 12.5 ±20

ECS INC International ECS-.327-12.5-17 -10°C to +60°C 12.5 ±20

Fox Electronics FSM327 -40°C to +85°C 12.5 ±20

M-tron SX2010/ SX2020 -20°C to +75°C 12.5 ±20

Raltron RSE-32.768-12.5-C-T -10°C to +60°C 12.5 ±20

SaRonix 32S12A -40°C to +85°C 12.5 ±20

Figure 6. Typical Temperature Curve for 32.768kHz Watch

Crystal

TYPICAL TEMPERATURE CHARACTERISITICS

(k = 0.035ppm/°C2, TO = +25°C)

∆f (ppm)

TEMPERATURE (°C)

-250

-200

-150

-100

-50

0-50 -40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 90

MAX6901

There are similar considerations for 32KHZ if it is

placed in its high-impedance state. For lowest time-

keeping current, it should not be allowed to float. Force

it high or low, or terminate it with a pullup or pulldown

resistor.

PC Board Layout Considerations

The MAX6901 uses a very-low-current oscillator to mini-

mize supply current. This causes the oscillator pins, X1

and X2, to be relatively high impedance. Exercise care

to prevent unwanted noise pickup.

Connect the 32.768kHz crystal directly across X1 and

X2 of the MAX6901. To eliminate unwanted noise pick-

up, design the PC board using these guidelines (Figure

7): place the crystal as close to X1 and X2 as possible

and keep the trace lengths short; place a guard ring

around the crystal, X1 and X2 traces (where applica-

ble), and connect the guard ring to GND; keep all sig-

nal traces away from beneath the crystal, X1, and X2.

Finally, an additional local ground plane can be added

under the crystal on an adjacent PC board layer. The

plane should be isolated from the regular PC board

ground plane, and tied to ground at the MAX6901

ground pin. Restrict the plane to be no larger than the

perimeter of the guard ring. Do not allow this ground

plane to contribute significant capacitance between X1

and X2.

Chip Information

TRANSISTOR COUNT: 26,214

PROCESS: CMOS

3-Wire Serial RTC in a TDFN

16 ______________________________________________________________________________________

Figure 7. Printed Circuit Board Layout for Crystal Connections

SM WATCH CRYSTAL

0.1µF

SM CAP

LAYER 1 TRACE

GROUND PLANE

VIA CONNECTION

GUARD RING

GROUND PLANE

VIA CONNECTION

GROUND PLANE

VIA CONNECTION

VCC PLANE

VIA CONNECTION

LAYER 2 LOCAL GROUND PLANE

CONNECT ONLY TO PIN 6

GROUND PLANE VIA

MAX6901

3-Wire Serial RTC in a TDFN

______________________________________________________________________________________ 17

OSCILLATOR

32.768kHz

DIVIDER

31 × 8

RAM

ADDRESS

INPUT SHIFT

REGISTERS

CONTROL

LOGIC

1Hz

VCC

GND

SCLK

I/O

32kHz

ALARM

CONTROL

LOGIC

ALARM OUT

SECONDS

MINUTES

HOURS

DATE

MONTH

DAY

YEAR

CONTROL

CENTURY

ALARM

CONFIGURATION

TEST

CONFIGURATION

ALARM

THRESHOLDS

CLOCK

BURST

RAM

BURST

Functional Diagram

TDFN

TOP VIEW

GND

32KHZ

I/O

VCC

SCLK

MAX6901

Pin Configuration

MAX6901

3-Wire Serial RTC in a TDFN

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

6, 8, &10L, DFN THIN.EPS

PIN 1

INDEX

AREA

NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY

DETAIL A

21-0137

PACKAGE OUTLINE, 6, 8, 10 & 14L,

TDFN, EXPOSED PAD, 3x3x0.80 mm

COMMON DIMENSIONS

SYMBOL MIN. MAX.

A0.700.80

D2.903.10

E2.903.10

A1 0.00 0.05

L0.20 0.40

PKG. CODE ND2 E2 eJEDEC SPEC b[(N/2)-1] x e

PACKAGE VARIATIONS

0.25 MIN.k

A2 0.20 REF.

2.30±0.101.50±0.106T633-1 0.95 BSC MO229 / WEEA 1.90 REF

21-0137

PACKAGE OUTLINE, 6, 8, 10 & 14L,

TDFN, EXPOSED PAD, 3x3x0.80 mm

0.40±0.05

1.95 REF0.30±0.05

0.65 BSC

2.30±0.108

T833-1

2.00 REF0.25±0.05

0.50 BSC

2.30±0.1010

T1033-1

2.40 REF0.20±0.03- - - -

0.40 BSC

1.70±0.10 2.30±0.1014T1433-1

1.50±0.10

MO229 / WEEC

MO229 / WEED-3

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)