LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers Check for Samples: LF155, LF156, LF355, LF356, LF357 FEATURES 1 Advantages 23 * * * * * * Replace Expensive Hybrid and Module FET Op Amps Rugged JFETs Allow Blow-Out Free Handling Compared with MOSFET Input Devices Excellent for Low Noise Applications Using Either High or Low Source Impedance--Very Low 1/f Corner Offset Adjust Does Not Degrade Drift or Common-Mode Rejection as in Most Monolithic Amplifiers New Output Stage Allows Use of Large Capacitive Loads (5,000 pF) without Stability Problems Internal Compensation and Large Differential Input Voltage Capability APPLICATIONS * * * * * * * Precision High Speed Integrators Fast D/A and A/D Converters High Impedance Buffers Wideband, Low Noise, Low Drift Amplifiers Logarithmic Amplifiers Photocell Amplifiers Sample and Hold Circuits DESCRIPTION These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors ( BI-FETTM Technology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner. Common Features * * * * * * Low Input Bias Current: 30pA Low Input Offset Current: 3pA High Input Impedance: 1012 Low Input Noise Current: 0.01 pA/Hz High Common-Mode Rejection Ratio: 100 dB Large DC Voltage Gain: 106 dB Table 1. Uncommon Features Extremely fast settling time to 0.01% Fast slew rate LF155/ LF355 LF156/ LF256/ LF356 LF257/ LF357 (AV=5) Units 4 1.5 1.5 s 5 12 50 V/s Wide gain bandwidth 2.5 5 20 MHz Low input noise voltage 20 12 12 nV / Hz 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. BI-FET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com Simplified Schematic *3pF in LF357 series. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) LF155/6 LF256/7/LF356B LF355/6/7 Supply Voltage 22V 22V 18V Differential Input Voltage 40V 40V 30V 20V 20V 16V Continuous Continuous Continuous 150C 115C 115C P Package 100C 100C D Package 100C 100C Input Voltage Range (3) Output Short Circuit Duration TJMAX LMC Package Power Dissipation at TA = 25C (1) (4) LMC Package (Still Air) 560 mW 400 mW 400 mW LMC Package (400 LF/Min Air Flow) 1200 mW 1000 mW 1000 mW P Package 670 mW 670 mW D Package 380 mW 380 mW 160C/W 160C/W 160C/W 65C/W 65C/W 65C/W P Package 130C/W 130C/W D Package 195C/W 195C/W Thermal Resistance (Typical) JA LMC Package (Still Air) LMC Package (400 LF/Min Air Flow) (Typical) JC LMC Package 23C/W 23C/W 23C/W -65C to +150C -65C to +150C -65C to +150C 300C 300C 300C 260C 260C 260C Vapor Phase (60 sec.) 215C 215C Infrared (15 sec.) 220C 220C 1000V 1000V Storage Temperature Range Soldering Information (Lead Temp.) TO-99 Package Soldering (10 sec.) PDIP Package Soldering (10 sec.) SOIC Package ESD tolerance (100 pF discharged through 1.5k) (1) (2) (3) (4) 1000V The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is PD=(TJMAX-TA)/JA or the 25C PdMAX, whichever is less. If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside specified limits. Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 3 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com DC Electrical Characteristics Symbol Parameter Min VOS Input Offset Voltage RS=50, TA=25C Typ Max 3 5 Over Temperature VOS/T Average TC of Input Offset Voltage TC/VOS Change in Average TC with VOS Adjust RS=50, IOS Input Offset Current TJ=25C, (1) (3) (1) (3) RIN Input Resistance TJ=25C AVOL Large Signal Voltage Gain VS=15V, TA=25C Input Common-Mode Voltage Range PSRR Supply Voltage Rejection Ratio (1) 3 10 mV 13 mV 0.5 0.5 0.5 V/C per mV 20 3 20 3 50 pA 2 nA 200 pA 8 nA 1 100 30 100 50 30 5 1012 1012 200 50 200 25 1012 200 V/mV VO=10V, RL=2k Output Voltage Swing Common-Mode Rejection Ratio Max V/C TJTHIGH CMRR 5 Units Typ 5 30 50 Min 6.5 20 Input Bias Current VCM 3 Max 5 3 IB VO Typ LF355/6/7 5 TJTHIGH TJ=25C, Min 7 RS=50 (2) LF256/7 LF356B LF155/6 Conditions Over Temperature 25 VS=15V, RL=10k 12 13 12 13 12 13 V VS=15V, RL=2k 10 12 10 12 10 12 V +15.1 V -12 V VS=15V 11 25 +15.1 -12 11 15 15.1 -12 V/mV +10 85 100 85 100 80 100 dB 85 100 85 100 80 100 dB (4) Unless otherwise stated, these test conditions apply: LF155/156 LF256/257 LF356B LF355/6/7 Supply Voltage, VS 15V VS 20V 15V VS 20V 15V VS 20V VS= 15V TA -55C TA +125C -25C TA +85C 0C TA +70C 0C TA +70C THIGH +125C +85C +70C +70C (2) (3) (4) and VOS, IB and IOS are measured at VCM = 0. The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5V/C typically) for each mV of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment. The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA + JA Pd where JA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice. DC Electrical Characteristics TA = TJ = 25C, VS = 15V Parameter Supply Current 4 LF155 LF355 LF156/256/257/356B LF356 LF357 Typ Max Typ Max Typ Max Typ Max Typ Max 2 4 2 4 5 7 5 10 5 10 Submit Documentation Feedback Units mA Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 AC Electrical Characteristics TA = TJ = 25C, VS = 15V Symbol SR Parameter LF155/355 LF156/256/ 356B LF156/256/356/ LF356B LF257/357 Typ Min Typ Typ 5 7.5 12 Conditions Slew Rate LF155/6: AV=1, LF357: AV=5 GBW Gain Bandwidth Product ts Settling Time to 0.01% en Equivalent Input Noise Voltage in CIN (1) Equivalent Input Current Noise Units V/s 50 V/s 2.5 5 20 MHz 4 1.5 1.5 s f=100 Hz 25 15 15 nV/Hz f=1000 Hz 20 12 12 nV/Hz f=100 Hz 0.01 0.01 0.01 pA/Hz f=1000 Hz 0.01 0.01 0.01 pA/Hz 3 3 3 pF (1) RS=100 Input Capacitance Settling time is defined here, for a unity gain inverter connection using 2 k resistors for the LF155/6. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF357, AV = -5, the feedback resistor from output to input is 2k and the output step is 10V (See Settling Time Test Circuit). Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 5 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwise specified. 6 Input Bias Current Input Bias Current Figure 1. Figure 2. Input Bias Current Voltage Swing Figure 3. Figure 4. Supply Current Supply Current Figure 5. Figure 6. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 Typical DC Performance Characteristics (continued) Curves are for LF155 and LF156 unless otherwise specified. Negative Current Limit Positive Current Limit Figure 7. Figure 8. Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit Figure 9. Figure 10. Open Loop Voltage Gain Output Voltage Swing Figure 11. Figure 12. Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 7 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com Typical AC Performance Characteristics Gain Bandwidth Gain Bandwidth Figure 13. Figure 14. Normalized Slew Rate Output Impedance Figure 15. Figure 16. Output Impedance Figure 17. 8 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 Typical AC Performance Characteristics (continued) LF155 Small Signal Pulse Response, AV = +1 LF156 Small Signal Pulse Response, AV = +1 Figure 18. Figure 19. LF155 Large Signal Pulse Response, AV = +1 LF156 Large Signal Puls Response, AV = +1 Figure 20. Figure 21. Inverter Settling Time Inverter Settling Time Figure 22. Figure 23. Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 9 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com Typical AC Performance Characteristics (continued) 10 Open Loop Frequency Response Bode Plot Figure 24. Figure 25. Bode Plot Bode Plot Figure 26. Figure 27. Common-Mode Rejection Ratio Power Supply Rejection Ratio Figure 28. Figure 29. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 Typical AC Performance Characteristics (continued) Power Supply Rejection Ratio Undistorted Output Voltage Swing Figure 30. Figure 31. Equivalent Input Noise Voltage Equivalent Input Noise Voltage (Expanded Scale) Figure 32. Figure 33. Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 11 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com DETAILED SCHEMATIC *C = 3pF in LF357 series. Connection Diagrams (Top Views) *Available per JM38510/11401 or JM38510/11402 Figure 34. TO-99 Package (LMC) See Package Number LMC (O-MBCY-W8) 12 Submit Documentation Feedback Figure 35. SOIC and PDIP Package (D and P) See Package Number D (R-PDSO-G8) or P (R-PDIP-T8) Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 APPLICATION HINTS These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize "pickup" and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Typical Circuit Connections Figure 36. VOS Adjustment * * * * VOS is adjusted with a 25k potentiometer The potentiometer wiper is connected to V+ For potentiometers with temperature coefficient of 100 ppm/C or less the additional drift with adjust is 0.5V/C/mV of adjustment Typical overall drift: 5V/C (0.5V/C/mV of adj.) Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 13 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com * LF155/6 R = 5k, LF357 R = 1.25k Figure 37. Driving Capacitive Loads Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) 0.01F. Overshoot 20%, Settling time (ts) 5s For distortion 1% and a 20 Vp-p VOUT swing, power bandwidth is: 500kHz. Figure 38. LF357 - A Large Power BW Amplifier Typical Applications Figure 39. Settling Time Test Circuit * * * * 14 Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = -5 FET used to isolate the probe capacitance Output = 10V step AV = -5 for LF357 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 Large Signal Inverter Output, VOUT (from Settling Time Circuit) Figure 40. LF355 Figure 41. LF356 Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 15 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com Figure 42. LF357 Figure 43. Low Drift Adjustable Voltage Reference * * * * * 16 VOUT/T = 0.002%/C All resistors and potentiometers should be wire-wound P1: drift adjust P2: VOUT adjust Use LF155 for - Low IB - Low drift - Low supply current Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 Figure 44. Fast Logarithmic Converter * * * * * Dynamic range: 100A Ii 1mA (5 decades), |VO| = 1V/decade Transient response: 3s for Ii = 1 decade C1, C2, R2, R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 + 0.3%/C Figure 45. Precision Current Monitor * * * VO = 5 R1/R2 (V/mA of IS) R1, R2, R3: 0.1% resistors Use LF155 for - Common-mode range to supply range - Low IB - Low VOS - Low Supply Current Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 17 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com Figure 46. 8-Bit D/A Converter with Symmetrical Offset Binary Operation * * R1, R2 should be matched within 0.05% Full-scale response time: 3s EO B1 B2 B3 B4 B5 B6 B7 B8 Comments +9.920 1 1 1 1 1 1 1 1 Positive Full-Scale +0.040 1 0 0 0 0 0 0 0 (+) Zero-Scale -0.040 0 1 1 1 1 1 1 1 (-) Zero-Scale -9.920 0 0 0 0 0 0 0 0 Negative Full-Scale Figure 47. Wide BW Low Noise, Low Drift Amplifier * Parasitic input capacitance C1 (3pF for LF155, LF156 and LF357 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 R1 C1. Figure 48. Boosting the LF156 with a Current Amplifier * IOUT(MAX)150mA (will drive RL 100) * * No additional phase shift added by the current amplifier 18 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 R1, R4 matched. Linearity 0.1% over 2 decades. Figure 49. Decades VCO Figure 50. Isolating Large Capacitive Loads * * * Overshoot 6% ts 10s When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX): Figure 51. Low Drift Peak Detector * * * * By adding D1 and Rf, VD1=0 during hold mode. Leakage of D2 provided by feedback path through Rf. Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage of Cp. Diode D3 clamps VOUT (A1) to VIN-VD3 to improve speed and to limit reverse bias of D2. Maximum input frequency should be << 1/2RfCD2 where CD2 is the shunt capacitance of D2. Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 19 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com Figure 52. Non-Inverting Unity Gain Operation for LF157 Figure 53. Inverting Unity Gain for LF157 20 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 Figure 54. High Impedance, Low Drift Instrumentation Amplifier * * System VOS adjusted via A2 VOS adjust Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 21 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com Figure 55. Fast Sample and Hold * * Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible) Acquisition time TA, estimated by: * * * LF156 develops full Sr output capability for VIN 1V Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2 Figure 56. High Accuracy Sample and Hold * * * * * 22 By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1. - No VOS adjust required for A2. TA can be estimated by same considerations as previously but, because of the added - propagation delay in the feedback loop (A2) the overshoot is not negligible. Overall system slower than fast sample and hold R1, CC: additional compensation Use LF156 for - Fast settling time - Low VOS Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 LF155, LF156, LF355, LF356, LF357 www.ti.com SNOSBH0C - MAY 2000 - REVISED MARCH 2013 Figure 57. High Q Band Pass Filter * * * By adding positive feedback (R2) Q increases to 40 fBP = 100 kHz * * Clean layout recommended Response to a 1Vp-p tone burst: 300s Figure 58. High Q Notch Filter * * * * 2R1 = R = 10M - 2C = C1 = 300pF Capacitors should be matched to obtain high Q fNOTCH = 120 Hz, notch = -55 dB, Q > 100 Use LF155 for - Low IB - Low supply current Copyright (c) 2000-2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LF155 LF156 LF355 LF356 LF357 23 LF155, LF156, LF355, LF356, LF357 SNOSBH0C - MAY 2000 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C * 24 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 23 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LF155 LF156 LF355 LF356 LF357 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LF156H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -55 to 125 LF156H LF156H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) POST-PLATE Level-1-NA-UNLIM -55 to 125 LF156H LF256H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -25 to 85 LF256H LF256H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) POST-PLATE Level-1-NA-UNLIM -25 to 85 LF256H LF356H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI 0 to 70 LF356H LF356H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) POST-PLATE Level-1-NA-UNLIM 0 to 70 LF356H LF356M NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LF356 M LF356M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LF356 M LF356MX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LF356 M LF356MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LF356 M LF356N NRND PDIP P 8 40 TBD Call TI Call TI 0 to 70 LF 356N LF356N/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LF 356N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LF356MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LF356MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LF356MX SOIC D 8 2500 367.0 367.0 35.0 LF356MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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