Features e CMOS for optimum speed/power e High speed 15-ns max set-up 12-ns cleck to output e Low power 660 mW (commercial) 770 mW (military) e@ On-chip edge-triggered registers ~ Ideal for pipelined microepro- grammed systems On-chip diagnostic shift register For serial observability and con- trolability of the output register EPROM technology 100% programmable Reprogrammable (7C269W) @ 5V +10% Vcc, commercial and military Capable of withstanding >2001V stat- icdischarge Slim 300-mil, 28-pin plastic or her- metic DIP (7C269) THAG-A3 2% CY7C268 CY7C269 Functional Description The CY7C268 and the CY7C269 are 8192 x 8 registered diagnostic PROMs. They are both organized as 8,192 words by 8 bits wide, and they have both a pipeline output register and an onboard diagnostic shift register. Both devices feature a program- mable initialize byte that may be loaded into the pipeline register with theinitialize signal. The programmable initialize byte is the 8,193rd byte inthe PROM, and maybe programmedto any desired value, The CY7C268 has 32 pins and features full diagnostic capabilities while the CY7C269 provides limited diagnostics and is avail- able in a space-efficient 28-pin package. This allows the designers to optimize de- signs for either board-area efficiency with the CY7C269, or combine the CY7C268 with other diagnostic products using the stan- dard interface. CY7C268 The CY7C268 provides 13 address signals (Ap through Aj), 8 data out signals (Op through O7), ENA (enable), PCLK (pipe- line clock) and INIT (initialize) forcontrol. 8192 x 8 Registered Diagnostic PROM The fullstandard feature diagnostics ofthe CY7C268 utilize the SDI and SDO (shift in and shift out), MODE, and DCLK signals, These signals allow serial data to be shifted into and out of the diagnostic shift register at the same time the pipeline register is used for normal operation. The MODE signal is used to control the transfer of the informa- tion in the diagnostic register to the pipeline register, or the data on the output bus into the diagnostic register. The data on the out- put bus may be provided from the pipeline register or from an external source. When the MODE signal is LOW, the PROM operates in a normal pipeline mode. The contents of the addressed memory location are loaded into the pipe- line register on the rising edge of PCLK. the outputs are enabled with the ENA sig- nal eithersynchronously or asynchronous- ly, depending on how the device is confi- gured when programmed. If programmed for asynchronous enable, ENA LOW en- ables the outputs. If configured for syn- chronous enable, ENA LOW will enable theoutputssynchronously with PCLK dur- ing the rising edge of PCLK. ENA WBE D MM 25869bbe 0006804 O EACyYP =] Logic Block Diagram Ai2 Au Aig ROW Apress DECODER COLUMN SITET FTF: MODE (70269) CLOCK (7G269) DIAGNOSTIC MUX e-BiT EOGE- spl Pin Configurations CerDIP/Flatpack Top View CerDIP/Flatpack Top View 268-2 0268-3 PCLK 8-8 TRIGGERED DeLK 0268) EDGE-TRIGGERED SHIFT REGISTER (7c268) LCC/PLCC (Opaque Only)y ccmpEce (Opaque Oni rena $00 Top View hop verame Only vent FLLESEL F2e2S22 (70268) 43 211,323130 Aa er) MODE 70268 7 NC 26 DCLK 5 PCLK 2 Ay Ao 22 Op p13 214 07 1415 1617181920 asseigde O7 Og O5 403 O2 0; Oo SOSESHS 8 0268-5 o c268~-4 C268~1 3-83 TSR reer ten pt a eee ee PROMs| CYPRESS SEMICONDUCTOR WbE D oe See Sas 5 CY7C268 T-46-13-29 CY7C269 EM 2S4%bb2 0006809 2 eacyp Functional Description (continued) HIGH will synchronously disable the outputs during the rising edge of PCLK. The asynchronous initialize signal, INIT transfers the initialize byte into the pipeline register on a HIGH to LOW transition. LOW disables PCLK and must transition back to a HIGH in order to enable PCLK. DCLK shifts data into SDI and out of SDO on each rising edge. When MODE is HIGH, the rising edge of the PCLK signal loads the pipeline register with the contents of the diagnostic register. Similarly, DCLK, in this mode, loads the diagnostic register with the information on the data output pins. The information loaded will be either the contents of the pipeline register if the outputs are enabled, or data on the bus if the outputs are disabled (in a high-impedance state). . CY7C269 : The CY7C269 is optimized for applications that require diagnos- tics in a minimum amount of board area. Packaged in 28 pins, it has 13 address signals (Ag through Aj), 8 data out signals (Op through 07), (Enable or Initialize), and CLOCK (pipeline and diagnostic clock). Additional diagnostic signals consist of MODE, SDI (shift in) and SDO (shift out), Normal pipelined op- eration and diagnostic operation are mutually exclusive. When the MODE signal is LOW, the 7C269 operates in a normal pipelined mode. CLOCK functions as a pipeline clock, loading the contents of the addressed memory location into the pipeline register on each rising edge. The data will appear on the outputs if they are enabled. One pin on the 7C269 Is programmed to per- form either the Enable or the Initialize function. If the E/{ pin is used for a INIT (asynchronous initialize) function, the outputs are permanently enabled and the initialize word is loaded into the pipeline register on a HIGH to LOW transition of the INIT signal. The INIT LOW disables CLOCK and must return high to re-enable CLOCK. If the E/T pin is used for an enable signal, it may be programmed for either synchronous or asynchronous op- eration. This enable function then operates exactly the same as the 7268. When the MODE signal is HIGH, the 7C269 operates in the diagnostic mode. The E/T signal becomes a secondary mode sig- nal designating whether to shift the diagnostic shift register or to load either the diagnostic register or the pipeline register. If E/1 is HIGH, CLOCK performs the function of DCLK, shifting SDI into the least-significant location of the diagnostic register and all bits one location toward the most-significant location on each ris- ing edge. The contents of the most-significant location in the diagnostic register are available on the SDO pin. If the Eff signal is LOW, SDI becomes a direction signal, frans- ferring the contents of the diagnostic register into the pipeline register when SDI is LOW. When SDI is HIGH, the contents of the output pins are transferred into the diagnostic register. Both transfers occur on a LOW to HIGH transition of the CLOCK. If the outputs are enabled, the contents of the pipeline register are transferred into the diagnostic register. If the outputs are dis- abled, an external source of data may be loaded into the diagnos- tic register. In this condition, the SDO signal is internally driven to be the same as the SDI signal, thus propagating the direction of transfer information to the next device in the string. Selection Guide 7269-15 7C269-18 7C269-25 Maximum Set-Up Time (ns) 15 18 25 Maximum Clock to Output (ns) 12 15 20 Maximum Operating Current (mA) Commercial 120 120 120 Military 140 140 70268 40 7C26850 7C268-60 7C26940 7C269-~50 7C269-60 Maximum Set-Up Time (ns) 40 50 60 Maximum Clock to Output (ns) 20 25 25 Maximum Operating Current (mA) Commercial 100 80 80 Military 120 100 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............ce08- 65C to +150C Static Discharge Voltage ........cccccccuvcocs ++. >2001V Ambient Temperature with (per MIL-STD-883, Method 3015) Power Applied ...... decceces Seaceene 55Cto +125C = Latch-Up Current .........cccccccccccecccece >200 mA Supply Voltage to Ground Potential ..... +. 70.5V to +7.0V : n n DC Voltage Applied to Outputs Operating Range in High Z State oo... ....ccceccceecnees . = 0.5V to +7.0V Ambient DC Input Voltage .......ssescuscuee vase =3,0V to +7.0V Range Temperature Yee DC Program Voltage ...... Cee eecereeaees beeereee 13.0V Commercial 0C to +70C SV 10% UV Exposure ....... beeeeeeeees seeveeees 7258 Weecfom? |_Industriall4l ~ 40C to +85C SV + 10% Militaryl2) 55C to +125C 5V + 10% 3-84CY7C268 T-46-13-29 ey7c209 Electrical Characteristics Overthe Operating Rangel? 41 7C269-15 | 7C269~18 | 7026925 Parameters Description Test Conditions Min. | Max. | Min, | Max. | Min. | Max. | Units Vou Output HIGH Voltage Voc = Min. Jon = 2.0mA 2.4 2.4 2.4 Vv Vou Output LOW Voltage Vec = Min. Io, = 8.0mA | Com't 0.4 0.4 0.4 v Vec= Min.,Ior,=6.0mA | Mil 0.4 0.4 0.4 Vu Input HIGH Voltage 2.0 2.0 2.0 Vv Vi Input LOW Voltage 0.8 0.8 0.8 v Ix Input Load Current GND < Vin < Vcc ~10} +10 | -10] +10 |-10] +10] pA Toz. Output Leakage Current GND < Vout < Vco -40 | +40 | -40] +40 | -40] +40] pA Output Disabled Ios!) Output Short Circuit Current 90 90 90 | mA Tec Vcc Operating Supply Vec= Max. Iour =O0mA | Com'l 120 120 120 | mA Current . Mil 140 140 Vpp ProgrammingSupply Voltage 12 | 13 | 12 | 13 | 12 | 13 Vv Ipp Programming Supply Current 50 50 50 | mA Vine Input HIGH Programming 3.0 3.0 3.0 Vv Voltage Vite Input LOW Programming 0.4 0.4 0.4 Vv Voltage 7C26840 | 7C268-50 | 7C268-60 7C269~40 | 7C269-50 | 7C026960 Parameters Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Units Vou Output HIGH Voltage Voc = Min., Jou = 2.0mA 2.4 2.4 2.4 Vv VoL Output LOW Voltage Voc = Min, Io, = 12.0mA | Com'l 0.4 0.4 0.4 Vv Vcc = Min, IoL = 8.0mA | Mil 0.4 0.4 0.4 Vin Input HIGH Voltage 2.0 2.0 2.0 v Vin Input LOW Voltage 0.8 0.8 08 | V Ix Input Load Current GND < Vin Vcc 10] +10 | - 10) +10 |-10] +10] wA loz Output Leakage Current GND < Vour < Veo ~40 | +40 |-40 | +40 | -40 | +40 | pA Output Disabled . Tos Output Short Circuit Current | Vcc = Max., Vour = GND 90 90 90 | mA Teo Voc Operating Vcc = Max. Iour =OmA | Com't 100 80 80 | mA Supply Current Mil 120 100 Vpp Programming Supply Voltage 12 13 12 13 12.] 13 v Ipp Programming Supply Current 50 350 50. .| mA Vip Input HIGH Programming 3.0 3.0 3.0 Vv Voltage Vitp Input LOW Programming 0.4 0.4 0.4 Vv Voltage m Notes: 1, Contact a Cypress representative for industrial temperature range 4. See Introduction to CMOS PROMs in this Data Book for general in- specifications, 2, Tais the instant on case temperature. 3. Seethe last page of this specitication for Group A subgroup testing in- formation. formation on testing. 5. For test purposes, not more than one output at a time should be shorted, Short circuit test duration should not exceed 30 seconds. 3-85 ULE D = 258%bb2 0006410 9 EgcyYP PROMs iyEo eee CYPRESS SEMICONDUCTOR WEE D Ka 2589bbe 0006811 0 ECYP =<, CY7C268 =. T-46-13-29 CY7C269 SS SEMICONDUCTOR Capacitancel*: 4 Parameters Description Test Conditions Max. Units Cr InputCapacitance Ta = 25C, f = 1 MHz, 10 Cout Output Capacitance Vcc = 5.0V 10 Note: 6. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms Test Load for 15 thraugh 25 speeds Ai 500 R1 500Q (658Q MIL) ev (658Q MIL) $~_v- OUTPUT P OUTPUT 3.0V A2 333 A2 933 GND 80 pF I (4082 MIL) 5 pF I (4030 MIL) <5ns INCLUDING = = INCLUDING & = JIGAND - JIGAND ~ 7 SCOPE SCOPE cesa-8 0268-7 (a) (b) High Z Load Equivalent to: THEVENIN EQUIVALENT Rry 200 2. OUTPUT O-ww_ 2500, MIL Test Load for 40 through 60 speeds Rt 2509 R1 2502 5V 5V 0 mee TT or TT : orl R2 1672 rl R2 1672 INCLUDING = = INCLUDING + + JIG AND 7 JIGAND 7 7 c2e8~8 SCOPE SCOPE (c) (d) High Z Load Equivalent to: THEVENIN EQUIVALENT Rry 1002 OUTPUT Owan _ 2.0V Switching Characteristics Over the Operating Rangel?-4 : 71C269-15 7269-18 71C269-25 Parameters Description Min. | Max. | Min. | Max. | Min. | Max. | Units tas Address Set-Up to Clock 15 18 25 ns tHa Address Hold from Clock 0 0 0 ns tco Clock to Output Valid 12 15 20 ns tpw Clock Pulse Width 12 15 15 ns tsEs Es Set-Up to Clock (Sync Enable Only) 12 15 15 ns tues Es Hold from Clock 5 5 5 ns tor INIT to Out Valid 15 18 25 ns tri INIT Recovery to Clock 12 15 20 ns tewi INIT Pulse Width 12 18 25 ns tcos Output Valid from Clock (Sync. Made) 12 15 20 ns tuzs Output Inactive from Clock (Sync. Mode) 12 15 20 ns tpor. Output Valid from E LOW (Asynch, Mode) 12 15 20 ns tuze Output Inactive from E HIGH (Async, Mode) 12 15 20 nsCYPRESS SEMICONDUCTOR 4BE D WM 2585662 0006812 2 Eacyp CY7C268 =r T-46-13-29 CY7C269 Sa SEMICONDUCTOR Switching Characteristics Over the Operating Rangel*-4l (continued) 7C26840 7026850 7C26860 726940 7026950 70269 ~-60 | Parameters Description ~ | Min, | Max. [ Mim. [ Max. | Min. [ Max. | Units tas Address Set-Up to Clack 40 50 60 ns ; tra Address Hold from Clock 0 0 0 ns tco Clock to Output Valid 20 25 25 ns tpw Clock Pulse Width 15 20 20 ns 2 tszs Es Set-Up to Clock (Sync Enable Only) 15 15 15 ns o trEs Es Hold from Clock : 5 5 5 ns & tor INIT to Output Valid 25 35 |. 35 ns tar INIT Recovery to Clock 20 25 25 ns tpwr INIT Pulse Width 25 35 35 ns tcos Output Valid from Clock (Syne. Mode) 20 25 25 ns tuzs Output Inactive from Clock (Sync. Mode) 20 25 25 ns tpor Output Valid from E LOW (Asynch. Mode) 20 25 25 ns tuze Output Inactive from E HIGH (Async. Mode) 20 25 25 ns Diagnostic Mode Switching Characteristics Over the Operating Rangel3-41 7C26840,50,60 7C269-15 | 7C269-18 | 7C269-25 Parameters Description Min. | Max, | Min. | Max. | Min. | Max. | Min. | Max. | Units tsspr Set-Up SDI to 25 30 ns 25 30 35 tusp1 from 0 0 tpspo Delay from toch to Hold from toSDO SDI to SDO Data Set-Up to DCLK Data from DCLKlaa. - Fo ee ee CYPRESS SEMICONDUCTOR WBE D EM 258%bb2 0006813 4 EECYP CY7C268 . CY7C269 T~46 7 3. 29 Switching Waveforms!3.4] Pipeline Operation (Mode = 0) ADDDRESS * *K SYNCHRONOUS | ss tan PROGRAMMABLE It tHes tgeg [> PCLK/CLOCK ws "TY AON tai OUTPUT VALID DATA toy fuze | tae 7 ttook ASYNCHRONOUS INIT (70269 PROGRAMMABLE) ASYNCHRONOUS ENABLE C268-10 Diagnostic Waveform for the 7C268 DCLK 4 ht tom t tocH toc. > sol | tssor 0 tHso1 tss rt tus tom MODE / x | 'osp0 / ton ex FTF tso tho OUTPUT se Y 268-9CYPRESS SEMICONDUCTOR 4BE D 2589bbe OO0b81L4 & Eacyp CY7C268 _ 5 CY7C269 & RES T-46-1 3-29 C269 | SSS" SEMICONDUCTOR Switching Waveforms!3:4] (continued) Diagnostic Application for the 7C269 (Shifting the Shadow Register!]) CLOCK MODE spo PROMs | SDI Efi Diagnostic Application for the 7C269 (Parallel Data Transfer) ts CLOCK A tel] toc. > ts tun MODE ~ XY a 4 = ts bm Spi } tvs tss SDO a at {toy P} Bf _ 9) tco tso >i tho jets 040% oinourK ox) < _ c268-11 Notes: 7. Asynchronous enable mode only. 9, The mode transition to HIGH latches the asynchronous enable state. 8. Diagnostic register = shadow register = shift register. If the enable state is changed and held before leaving the diagnostic mode(modeH L)thentheoutputimpedancechange delay istys,CYPRESS SEMICONDUCTOR 4YBE D 258%bbe2 OO0b815 & EACYP CY7C268 T-46-13-29 CY7C269 Bit Map Data Programming Modes Programming support is available from Cypress as well as from a Programmer Address (Hex.) RAM Data number of third-party software vendors. For detailed program- Decimal Hex Contents ming information, including a listing of software packages, please 0 0 see the PROM Programming Information located at the end of Data this section. Programming algorithms can be obtained from any : : : Cypress representative. 8191 1FFF Data 8192 2000 Init Byte 8193 2001 Control Byte Control Byte 00 Asynchronous output enable (default condition) 01 Synchronous output enable 02 Asynchronous initialize (CY7C269 only) Table 1. CY7C268 Mode Selection Pin Function) Read or Output Disable A Au Ato Az Ag As AgA3 Ad At Mode Other Av Aun Aig Az As As Ag Ag Az Al Read Aw | An | Aio Az Ags As | Ag-Az | Ag Al Load SR to PR Ai Au Ajo - Ay A As Aqg~ A3 A2 Al Load Output to SR Ay Au Ajo ~ Az AG As Ag A3 Ag Ai Shift SR Ar | An | Ap Az Ag As | AqgA3 A Al Asynchronous Enable Read A12 Aun Ajo Az Ag As Ag Aj Ag At Synchronous Enable Read Ar Aun Ayo ~ Az Ag As Ag Ag A2 At Asynchronous Initialization Read Ar Ai Ajo Ay AG As Ag Ag Ag At Program Memory Ai { An | Ato ~ Az Ag As | AagA3 Ag AL Program Verify Aiz | An | Aso Az Ag As | Aq-Ag A2 Al Program Inhibit Ar Al Aig - Ay Ag As Ag Ag Ag Ay Program Synchronous Enable Vine | Vise Aig Az Viep | Vpp | Ag Ay Vine | Ver Program Initial Byte x Vitp Ajo Ay Vine | Vpp | Aa- Az | Virp | Vpp Pin Function] Read or Output Disable Ae MODE | DCLK PCLK SDI {| SDO E, Es, IY | O7 ~ Oe Mode [Other ae | Pom | pccK | PcLK | NA | VEY | Ver 1 D;~D, Read Ao Vit xX Vi/Vin | X | SDO Vit Q7- Og Load SR to PR Ag Vint Vit Vi/Vin | X SDI x O7- Oo Load Output to SR Ao Vin Vi/Via Vin Vn. | SDI Vin O7 - Oo Shift SR Ag Vint Vir/Viex Vit Din [ SDO x O7- Oo Asynchronous Enable Read Ag Vin Vit xX Vn, | SDO Vit O07 - Oo Synchronous Enable Read Ag Vit Vi. Vi/Vin | Vi. | SDO Vit 0O7~ Oo Asynchronous Initialization Read Ag Vit Vit x Vi, | SDO Vit 07-0 Program Memory Ao | Vip Vip Vip | Vip | View | Ver | D7-Do Program Verify Ago | Vip Vite Vip | Vie | Vite | Vep_ | 07- Oo Program Inhibit | Ag Vine Vitp Vite Vite | Vine Vpp High Z Program Synchronous Enable Vir | Vine Vip Vite | Vice | Vine Vpp Dz~Dg Progrant Initial Byte Vine | Vite Vip Virp__| Vip | Vine | Ver [| D7DoC PRESS SEMICONDUCTOR a PROMs Y WbE D ES 2549bb2 OO0b81b T EACYP a CY7C268 SSs2 Seaiwuctor T-46~13~29 C7C269 Table 2. CY7C269 Meade Selection Pin Function] Read or Output Disable Ai Aut Ajo Az Ag As Ag~ Ag Ad At Mode Other Ay Ay Ajo Az Ag As Ag- Ag Ag At Read Ai. | At Ajo Az As As | AaA3 A2 Ai Load SR to PR Ay Ay Ato Aq A6 As Ag Aj Ad Ai Load Output to SR Ay Aq Ato Az Ag As Ag Ag Ag At Shift SR Ai Ai Ayo Az Ag As Ag Ag Ag Ay Asynchronous Enable Read Ay Au Ajo Az Ag As Ag Ag Ag At Synchronous Enable Read Ai Ai Ajo Az Ag As Ag Ag Ag At Asynchronous InitializationRead A Au Aig Az Ag As | Ag-Ay Ag Al ProgramMemory Ar | An Ato A7 As As | AgA3 Ag At Program Verify Ay | An | Aio Az As As | AgAg Ag Ai Program Inhibit A An Aio ~ Az Ag As Ag A3 Ag Ay Program Synchronous Enable Vine | Vine Ajo A7 Vinp | Veep | AqAz3 | Vine | Vpp Programinitialize Vie | View Ajo Az Vine | Vpp | Aqg Ag Virp_ | Vpp Program Initial Byte Ay Vite Ato Az Vine | Vpp Ag Ag Virp | Vpp Pin Function!) Read or Output Disable Ag MODE CLK SDI sDO E,I 07 - Oo Mode | Other Ap | PGM CLK | NA | VEY Vep D7 Do Read Ao Vin Vi/Vin Xx High Z Vu, O7 Oo Load SR to PR Ag Vint Vo/Vox | Vi SDI Vit O07 ~ Oo Load Output to SR Ao Vinr Vo/Vin | Vix SDI Vir O07 - Oo ShiftSR Ag Vint Vo/Vix | Din SDO Viz Q7 - Oo Asynchronous Enable Read Ag Va Vit Xx HighZ Vir 07 - Og Synchronous Enable Read Ao Vit Va/Vin x HighZ Vir 07- Qo AsynchronousInitialization Read Ag Vit Vin x High Z Vit O7 - Oo ProgramMemory Ao Virp Vip x Vinp Vpp D7 - Do Program Verify Ag Vine Vitp x Virp Vpp O07 Oo Program Inhibit Ao Vine Vite xX Vine Vpp High Z Program Synchronous Enable ViILp Vite Vite xX Vine Vpp D7 - Do ProgramInitialize Vite ViLP Vip x Vine Vpp D7Do Program Initial Byte Vine Virp Vite x Vine Vpp D7-Do Ox = don't care but not to exceed Voc 5%. 3-91 Sey Re ee eed oe2 cs wee cee ee ee - =. Be a CYPRESS SEMICONDUCTOR WbE D KM 2589bb2 0006817 1 MCP CY7C268 Ss Frcs T-46-13-29 CY7C269 Se = CYP Sa SEMICONDUCTOR ) CerDIP/Flatpack CerDIP/Flatpack LCC/PLCC (Opaque Only) x LCC/PLCC (Opaque Only) ; g : & & + O50 OF Q ini zberSed Ato g Ay Ag 7 NA Ae NG 8 Vpp PGM Ms i Aion 1 12 a { Da 1 ono NA Ao VFY Do 219 07 14151817 181920 OOetno oogaa aaeedsa 268-16 C268~14 Figure 1, Programming Pinouts ree ee wee nae = SoS wee eei CYPRESS SEMICONDUCTOR 4BE D KM 2589662 0006818 3 ECYP =_ CY7C268 = Fires T-46-13-29 CY7C269 SSS SEMICONDUCTOR Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT ys. SUPPLY VOLTAGE ys. AMBIENT TEMPERATURE _ vs. OUTPUT VOLTAGE 6 1.2 < 60 e 8 1.4 g it A ai 50 a H 4.2 | a 3% Ej N Ico uw z tec A q 10 Q 30 & 1.0 3 s = = z a a 0.8 o 0.9 5 a. a Ta = 25C z 10 0.6 f= MAX, 08 3 0 40 45 50 55 60 55 25 425 00 10 20 #30 #40 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) OUTPUT VOLTAGE (V) NORMALIZED ACCESS TIME OUTPUT SINK CURRENT TYPICAL ACCESS TIME CHANGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE vs. QUIPUT LOADING 16 = 175 30.0 uw E E44 5 180 25.0 Pw i i 125 > 200 g 1.2 3 100 H 1.0 > g < Z | 5 g0 i 10.0 = a g 08 Eos Voc = 5.0V 5.0 Veo = 4.5V =z oO Ta = 25C Ta = 25C 0.6 0 .0 65 28 125 00 61006 200=~=*=st~<i CO 0.05 200 400 600 800 1000 AMBIENT TEMPERATURE (C) OUTPUT VOLTAGE (V) CAPACITANCE (pF) C268~17 3-93CYPRESS SEMICONDUCTOR Tea 4bE D ES 258%bbe 0006819 S EACYP ~~ CY7C268 SS F Crass T-46-~13_99 CY7C269 SEMICONDUCTOR Ordering Information!4] Speed] Icc Package | Operating Speed] Icc Package | Operating (ns) | (mA) Ordering Code Type Range (ms) | (mA) Ordering Code Type Range 40 100 | CY7C268-40DC D20 | Commercial 15 120 | CY7C269-15DC D22_ | Commercial CY7C26840WC Ww20 CY7C269-15PC P2i 50 80 CY7C26850DC D20 | Commercial CY7C269-15WC W22 CY7C268~SOWC Ww20 18 120 | CY7C269-18DC D22_| Commercial 120 | CY7C268-S50DMB | D20 | Military CY7C26918PC P21 CY7C268SOLMB L55 CY7C269-18WC W22 CY7C268SOQMB | Q55 140 | CY7C26918DMB {| D22 | Military CY7C268-SOWMB | W20 CY7C269-18LMB L64 60 80 CY7C26860DC D20 | Commercial CY7C269-18QMB | Q64 CY7C26860WC Ww20 CY7C269-18WMBj W22 100 | CY7C268-60DMB | D20 | Military 25 140 | CY7C26925DC D22 | Commercial CY7C26860LMB L55 CY7C26925LC L64 CY7C26860QMB | Q55 CY7C26925PC P2i CY7C268-60WMB| W20 CY7C269-25QC Q64 Notes: CY7C26925WC W22 11. Most of these products are available in industrial temperature range. C7C26925DMB | D22 | Military Contact a Cypress representative for specifications and productavail- CY7C26925LMB 1.64 abil. CY7C269-250MB | O64 CY7C269-25WMB | W22 40 100 | CY7C26940DC D22 | Commercial CY7C26940PC P21 CY7C26940WC Ww22 50 80 CY7C26950DC D222 | Commercial CY7C269-50PC P21 CY7C269-S50WC W22 120 | CY7C269-SODMB | D22 | Military CY7C269-S0LMB 164 CY7C269~SOQMB ] Q64 CY7C269-S0OWMB| W22 60 80 CY7C269-60DC D22 | Commercial CY7C269-60PC P21 . CY7C26960WC W22 100 | CY7C269-60DMB | D22 | Military CY7C269--60LMB L64 CY7C269-60QMB |] Q64 C7C269Y-60WMB} W22 3-94 pena eee ee tn ee a ee _CYPRESS SEMICONDUCTOR Sree, = =. SS; ee _" = CYPRESS as SEMICONDUCTOR WBE D MM 258%bbe 0006820 1 EaCcYp- CY7C268 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters Subgroups Vou 1,2,3 Vo. 1,2,3 Vin 1,2,3 Vit 1,2,3 Ix 1,2,3 loz 1,2,3 Icc 1,2,3 Isp 1,2,3 Switching Characteristics Parameters Subgroups tas 7, 8,9, 10, 11 tHa 7,8, 9, 10, 11 tco 7, 8, 9, 10, 11 tpw 7, 8,9, 10, 11 tsps 7,8, 9, 10, 14 tyes 7, 8, 9, 10, 11 tcos 7,8, 9, 10, 11 Diagnostic Mode Switching Characteristics Parameters Subgroups tsspr 7, 8, 9, 10, 11 tyspi 7, 8, 9, 10, 11 tpspo 7, 8, 9, 10, 11 toc. 7,8, 9, 10, 14 tpcH 7,8, 9, 10, 14 tum 7, 8,9, 10, i1 tus 7,8, 9, 10, 11 tss 7, 8, 9, 10, 11 Notes: 12. 7C269 only. Document #: 3800069C 3-95 T 16-1 3-29 PROMs By | CY7C269