2013 Microchip Technology Inc. DS20005206A-page 1
11AA02UID
DEVICE SELECTION TABLE
Features:
• Preprogrammed 32-Bit Serial Number:
- Unique across all UID-family EEPROMs
- Scalable to 48-bit, 64-bit, 128-bit, 256-bit,
and other lengths
• Single I/O, UNI/O® Serial Interface Bus
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 µA standby current (max.)
• 256 x 8 Bit Organization
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kbps Max. Bit Rate – Equivalent to 100 kHz
Clock Frequency
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write enable latch bit
- Write-In-Progress bit
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4,000V
• 3-Lead SOT-23 and 8-Lead SOIC Packages
• RoHS Compliant
• Available Temperature Ranges:
Description:
The Microchip Technology Inc. 11AA02UID device is a
2 Kbit Serial Electrically Erasable PROM with a
preprogrammed, 32-bit unique ID. The device is
organized in blocks of x8-bit memory and support the
patented* single I/O UNI/O® serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
correctly decode the timing and value of each bit.
Low-voltage design permits operation down to 1.8V,
with standby and active currents of only 1 uA and 1 mA,
respectively.
The 11AA02UID is available in standard 8-lead SOIC
and 3-lead SOT-23 packages.
Package Types (not to scale)
Pin Function Table
Part Number Density
(bits) VCC Range Page Size
(Bytes)
Temp.
Ranges Packages Unique ID
Length
11AA02UID 2K 1.8-5.5V 16 I SN, TT 32-Bit
- Industrial (I): -40°C to +85°C
Name Function
SCIO Serial Clock, Data Input/Output
VSS Ground
VCC Supply Voltage
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
NC
NC
SCIO
SOIC
(SN)
SOT23
2
3
1SCIO
VCC
VSS
(TT)
2K UNI/O® Serial EEPROM with Unique 32-Bit Serial Number
* Microchip’s UNI/O® Bus products are covered by the following patents issued in the U.S.A.: 7,376,020 and 7,788,430.
11AA02UID
DS20005206A-page 2 2013 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
SCIO w.r.t. VSS .................................................................................................................................... -0.6V to VCC+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias.................................................................................................................-40°C to 85°C
ESD protection on all pins..........................................................................................................................................4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C
VCC = 1.8V to 2.5V TA = -20°C to +85°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
D1 VIH High-level Input
Voltage
0.7*VCC VCC+1 V
D2 VIL Low-level Input
Voltage
-0.3
-0.3
0.3*VCC
0.2*VCC
V
V
VCC2.5V
VCC < 2.5V
D3 VHYS Hysteresis of Schmitt
Trigger inputs (SCIO)
0.05*Vcc — V VCC2.5V (Note 1)
D4 VOH High-level Output
Voltage
VCC -0.5
VCC -0.5
—
—
V
V
IOH = -300 A, VCC = 5.5V
IOH = -200 A, Vcc = 2.5V
D5 VOL Low-level Output
Voltage
—
—
0.4
0.4
V
V
IOI = 300 A, VCC = 5.5V
IOI = 200 A, Vcc = 2.5V
D6 IOOutput Current Limit
(Note 2)
—
—
±4
±3
mA
mA
VCC = 5.5V (Note 1)
Vcc = 2.5V (Note 1)
D7 ILI Input Leakage
Current (SCIO)
—±1AVIN = VSS or VCC
D8 CINT Internal Capacitance
(all inputs and
outputs)
—7pFTA = 25°C, FCLK = 1 MHz,
VCC = 5.0V (Note 1)
D9 ICC Read Read Operating
Current
—
—
3
1
mA
mA
VCC=5.5V, FBUS=100 kHz, CB=100 pF
VCC=2.5V, FBUS=100 kHz, CB=100 pF
D10 ICC Write Write Operating
Current
—
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
D11 Iccs Standby Current — 1 AV
CC = 5.5V, TA = 85°C
D12 ICCI Idle Mode Current — 50 AVCC = 5.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: The SCIO output driver impedance will vary to ensure IO is not exceeded.
2013 Microchip Technology Inc. DS20005206A-page 3
11AA02UID
TABLE 1-3: AC TEST CONDITIONS
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C
VCC = 1.8V to 2.5V TA = -20°C to +85°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
1F
BUS Serial Bus Frequency 10 100 kHz —
2TEBit Period 10 100 µs —
3T
IJIT Input Edge Jitter
Tole ranc e
—±0.06UI(Note 3)
4F
DRIFT Serial Bus Frequency
Drift Rate Tolerance
— ±0.50 % per byte —
5F
DEV Serial Bus Frequency
Drift Limit
—±5% per
command
—
6T
OJIT Output Edge Jitter — ±0.25 UI (Note 3)
7TRSCIO Input Rise Time
(Note 1)
— 100 ns —
8T
FSCIO Input Fall Time
(Note 1)
— 100 ns —
9T
STBY Standby Pulse Time 600 — µs —
10 T
SS Start Header Setup Time 10 — µs —
11 THDR Start Header Low Pulse
Time
5—µs—
12 T
SP Input Filter Spike
Suppression (SCIO)
—50ns(Note 1)
13 TWC Write Cycle Time
(byte or page)
—
—
5
10
ms
ms
Write, WRSR commands
ERAL, SETAL commands
14 — Endurance (per page) 1M — cycles 25°C, VCC = 5.5V (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at
www.microchip.com.
3: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency.
AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
CL = 100 pF
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC
11AA02UID
DS20005206A-page 4 2013 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING – START HEADER
FIGURE 1-2: BUS TIMING – DATA
FIGURE 1-3: BUS TIMING – STANDBY PULSE
FIGURE 1-4: BUS TIMING – JITTER
SCIO
2
Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’MAK bit NoSAK bit
1110
2
SCIO
7 8
Data ‘0’Data ‘1’Data ‘1’Data ‘0’
12
SCIO
9
Standby
Mode
Ideal Edge
3
2
3 6 6
2
6 6
Ideal Edge Ideal Edge Ideal Edge
from Master from Master from Slave from Slave
2013 Microchip Technology Inc. DS20005206A-page 5
11AA02UID
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 11AA02UID family of serial EEPROMs support
the UNI/O® protocol. They can be interfaced with
microcontrollers, including Microchip’s PIC® microcon-
trollers, ASICs, or any other device with an available
discrete I/O line that can be configured properly to
match the UNI/O protocol.
The 11AA02UID devices contain an 8-bit instruction
register. The devices are accessed via the SCIO pin.
Data is embedded into the I/O stream through
Manchester encoding. The bus is controlled by a
master device which determines the clock period, con-
trols the bus access and initiates all operations, while
the 11AA02UID works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is active.
FIGURE 2-1: BLOCK DIAGRAM
SCIO
STATUS
Register
I/O Control Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
Current-
Limited
Slope
Control
11AA02UID
DS20005206A-page 6 2013 Microchip Technology Inc.
3.0 BUS CHARACTERISTICS
3.1 Standby Pulse
When the master has control of SCIO, a standby pulse
can be generated by holding SCIO high for TSTBY. At
this time, the 11AA02UID will reset and return to
Standby mode. Subsequently, a high-to-low transition
on SCIO (the first low pulse of the header) will return
the device to the active state.
Once a command is terminated satisfactorily (i.e., via
a NoMAK/SAK combination during the Acknowledge
sequence), performing a standby pulse is not required
to begin a new command as long as the device to be
selected is the same device selected during the previ-
ous command. However, a period of TSS must be
observed after the end of the command and before the
beginning of the start header. After TSS, the start
header (including THDR low pulse) can be transmitted
in order to begin the new command.
If a command is terminated in any manner other than a
NoMAK/SAK combination, then the master must
perform a standby pulse before beginning a new
command, regardless of which device is to be selected.
An example of two consecutive commands is shown in
Figure 3-1. Note that the device address is the same
for both commands, indicating that the same device is
being selected both times.
A standby pulse cannot be generated while the slave
has control of SCIO. In this situation, the master must
wait for the slave to finish transmitting and to release
SCIO before the pulse can be generated.
If, at any point during a command an error is detected
by the master, a standby pulse should be generated
and the command should be performed again.
FIGURE 3-1: CONSECUTIVE COMMANDS EXAMPLE
3.2 Start Data Transfer
All operations must be preceded by a start header. The
start header consists of holding SCIO low for a period
of THDR, followed by transmitting an 8-bit ‘01010101’
code. This code is used to synchronize the slave’s
internal clock period with the master’s clock period, so
accurate timing is very important.
When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
T
SS must be observed after the end of the command
and before the beginning of the start header.
Figure 3-2 shows the waveform for the start header,
including the required Acknowledge sequence at the
end of the byte.
FIGURE 3-2: START HEADER
Note: After a POR/BOR event occurs, a low-to-
high transition on SCIO must be gener-
ated before proceeding with communica-
tion, including a standby pulse.
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
NoSAK
SAK
Standby Pulse(1)
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
NoSAK
SAK
NoMAK
SAK
TSS
Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first
standby pulse.
SCIO
Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’MAK NoSAKTSS THDR
2013 Microchip Technology Inc. DS20005206A-page 7
11AA02UID
3.3 Acknowledge
An Acknowledge routine occurs after each byte is
transmitted, including the start header. This routine
consists of two bits. The first bit is transmitted by the
master, and the second bit is transmitted by the slave.
The Master Acknowledge, or MAK, is signified by trans-
mitting a ‘1’, and informs the slave that the current
operation is to be continued. Conversely, a Not
Acknowledge, or NoMAK, is signified by transmitting a
‘0’, and is used to end the current operation (and initiate
the write cycle for write operations).
The slave Acknowledge, or SAK, is also signified by
transmitting a ‘1’, and confirms proper communication.
However, unlike the NoMAK, the NoSAK is signified by
the lack of a middle edge during the bit period.
A NoSAK will occur for the following events:
• Following the start header
• Following the device address, if no slave on the
bus matches the transmitted address
• Following the command byte, if the command is
invalid, including Read, CRRD, Write, WRSR,
SETAL, and ERAL during a write cycle.
• If the slave becomes out of sync with the master
• If a command is terminated prematurely by using
a NoMAK, with the exception of immediately after
the device address.
See Figure 3.3 and Figure 3-4 for details.
If a NoSAK is received from the slave after any byte
(except the start header), an error has occurred. The
master should then perform a standby pulse and begin
the desired command again.
FIGURE 3-3: ACKNOWLEDGE
ROUTINE
FIGURE 3-4: ACKNOWLEDGE BITS
3.4 Device Addressing
A device address byte is the first byte received from the
master device following the start header. The device
address byte consists of a 4-bit family code, for the
11AA02UID this is set as ‘1010’. The last four bits of
the device address byte are the device code, which is
hardwired to ‘0000’.
FIGURE 3-5: DEVICE ADDRESS BYTE
ALLOCATION
3.5 Bus Conflict Protection
To help guard against high current conditions arising
from bus conflicts, the 11AA02UID features a current-
limited output driver. The IOL and IOH specifications
describe the maximum current that can be sunk or
sourced, respectively, by the SCIO pin. The
11AA02UID will vary the output driver impedance to
ensure that the maximum current level is not exceeded.
Note: A MAK must always be transmitted
following the start header.
Note: When a NoMAK is used to end a WRITE
or WRSR instruction, the write cycle is not
initiated if no bytes of data have been
received.
Note: In order to guard against bus contention, a
NoSAK will occur after the start header.
Master Slave
MAK SAK
MAK (‘1’)
NoMAK (‘0’)
SAK (‘1’)
NoSAK(1)
Note 1:
valid SAK.
A NoSAK is defined as any sequence that is not a
1010000
MAK
SLAVE ADDRESS
0
SAK
11AA02UID
DS20005206A-page 8 2013 Microchip Technology Inc.
3.6 Device Standby
The 11AA02UID features a low-power Standby mode
during which the device is waiting to begin a new
command. A high-to-low transition on SCIO will exit
Low-Power mode and prepare the device for receiving
the start header.
Standby mode will be entered upon the following
conditions:
• A NoMAK followed by a SAK (i.e., valid termina-
tion of a command)
• Reception of a standby pulse
3.7 Device Idle
The 11AA02UID features an Idle mode during which
all serial data is ignored until a standby pulse occurs.
Idle mode will be entered upon the following condi-
tions:
• Invalid device address
• Invalid command byte, including Read, CRRD,
Write, WRSR, SETAL and ERAL during a write
cycle.
• Missed edge transition
• Reception of a MAK following a WREN, WRDI,
SETAL, or ERAL command byte
• Reception of a MAK following the data byte of a
WRSR command
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the
master. If the slave is not synchronized with the
master, an edge transition will be missed, thus causing
the device to enter Idle mode.
3.8 Synchronization
At the beginning of every command, the 11AA02UID
utilizes the start header to determine the master’s bus
clock period. This period is then used as a reference for
all subsequent communication within that command.
The 11AA02UID features re-synchronization circuitry
which will monitor the position of the middle data edge
during each MAK bit and subsequently adjust the inter-
nal time reference in order to remain synchronized with
the master.
There are two variables which can cause the
11AA02UID to lose synchronization. The first is
frequency drift, defined as a change in the bit period,
T
E. The second is edge jitter, which is a single occur-
rence change in the position of an edge within a bit
period, while the bit period itself remains constant.
3.8.1 FREQUENCY DRIFT
Within a system, there is a possibility that frequencies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some toler-
ance for such frequency drift. The tolerance range is
specified by two parameters, FDRIFT and FDEV. FDRIFT
specifies the maximum tolerable change in bus fre-
quency per byte. FDEV specifies the overall limit in fre-
quency deviation within an operation (i.e., from the end
of the start header until communication is terminated
for that operation). The start header at the beginning of
the next operation will reset the re-synchronization
circuitry and allow for another FDEV amount of
frequency drift.
3.8.2 EDGE JITTER
Ensuring that edge transitions from the master always
occur exactly in the middle or end of the bit period is not
always possible. Therefore, the re-synchronization
circuitry is designed to provide some tolerance for edge
jitter.
The 11AA02UID adjusts its phase every MAK bit, so
TIJIT specifies the maximum allowable peak-to-peak
jitter relative to the previous MAK bit. Since the position
of the previous MAK bit would be difficult to measure by
the master, the minimum and maximum jitter values for
a system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
The difference between the minimum and maximum
values, as a percentage of the bit period, should be cal-
culated and then compared against TIJIT to determine
jitter compliance.
Note: In the case of the WRITE, WRSR, SETAL,
or ERAL commands, the write cycle is
initiated upon receipt of the NoMAK,
assuming all other write requirements
have been met.
Note: Because the 11AA02UID only re-synchro-
nizes during the MAK bit, the overall ability
to remain synchronized depends on a
combination of frequency drift and edge
jitter (i.e., if the MAK bit edge is experienc-
ing the maximum allowable edge jitter,
then there is no room for frequency drift).
Conversely, if the frequency has drifted to
the maximum amount tolerable within a
byte, then no edge jitter can be present.
2013 Microchip Technology Inc. DS20005206A-page 9
11AA02UID
4.0 DEVICE COMMANDS
After the device address byte, a command byte must
be sent by the master to indicate the type of operation
to be performed. The code for each instruction is listed
in Table 4-1.
TABLE 4-1: INSTRUCTION SET
4.1 Read Instruction
The Read command allows the master to access any
memory location in a random manner. After the READ
instruction has been sent to the slave, the two bytes of
the Word Address are transmitted, with an Acknowl-
edge sequence being performed after each byte. Then,
the slave sends the first data byte to the master. If more
data is to be read, the master sends a MAK, indicating
that the slave should output the next data byte. This
continues until the master sends a NoMAK, which ends
the operation.
To provide sequential reads in this manner, the
11AA02UID contains an internal Address Pointer which
is incremented by one after the transmission of each
byte. This Address Pointer allows the entire memory
contents to be serially read during one operation. When
the highest address is reached, the Address Pointer
rolls over to address ‘0x00’ if the master chooses to
continue the operation by providing a MAK.
FIGURE 4-1: READ COMMAND SEQUENCE
Instruction Name Instruction Code Hex Code Description
READ 0000 0011 0x03 Read data from memory array beginning at specified address
CRRD 0000 0110 0x06 Read data from current location in memory array
WRITE 0110 1100 0x6C Write data to memory array beginning at specified address
WREN 1001 0110 0x96 Set the write enable latch (enable write operations)
WRDI 1001 0001 0x91 Reset the write enable latch (disable write operations)
RDSR 0000 0101 0x05 Read STATUS register
WRSR 0110 1110 0x6E Write STATUS register
ERAL 0110 1101 0x6D Write ‘0x00’ to entire array
SETAL 0110 0111 0x67 Write ‘0xFF’ to entire array
7654
Data Byte 1
32107654
Data Byte 2
32107654
Data Byte n
3210
SCIO
MAK
MAK
NoMAK
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
01000001
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
15 14 13 12
Word Address MSB
11 10 9 8
MAK
SAK
7654
Word Address LSB
3210
MAK
SAK
SAK
SAK
SAK
11AA02UID
DS20005206A-page 10 2013 Microchip Technology Inc.
4.2 Current Address Read (CRRD)
Instruction
The internal address counter featured on the
11AA02UID maintains the address of the last memory
array location accessed. The CRRD instruction allows
the master to read data back beginning from this
current location. Consequently, no word address is
provided upon issuing this command.
Note that, except for the initial word address, the
READ and CRRD instructions are identical, including
the ability to continue requesting data through the use
of MAKs in order to sequentially read from the array.
As with the READ instruction, the CRRD instruction is
terminated by transmitting a NoMAK.
Table 4-2 lists the events upon which the internal
address counter is modified.
TABLE 4-2: INTERNAL ADDRESS
COUNTER
FIGURE 4-2: CRRD COMMAND SEQUENCE
Command Event Action
— Power-on Reset Counter is undefined
Read or
Write
MAK edge
following each
Address byte
Counter is updated
with newly received
value
Read,
Write, or
CRRD
MAK/NoMAK
edge following
each data byte
Counter is incre-
mented by 1
Note: If, following each data byte in a READ,
WRITE, or CRRD instruction, neither a
MAK nor a NoMAK edge is received (i.e.,
if a standby pulse occurs instead), the
internal address counter will not be incre-
mented.
Note: During a Write command, once the last
data byte for a page has been loaded, the
internal Address Pointer will rollover to the
beginning of the selected page.
7654
Data Byte 1
32107654
Data Byte 2
3210
7654
Data Byte n
3210
SCIO
MAK
MAK
NoMAK
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
10000001
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
SAK
SAK
SAK
2013 Microchip Technology Inc. DS20005206A-page 11
11AA02UID
4.3 Write Instruction
Prior to any attempt to write data to the 11AA02UID, the
write enable latch must be set by issuing the WREN
instruction (see Section 4.4 “Write Enable (WREN)
and Write Disable (WRDI) Instructions”).
Once the write enable latch is set, the user may
proceed with issuing a WRITE instruction (including
the header and device address bytes) followed by the
MSB and LSB of the Word Address. Once the last
Acknowledge sequence has been performed, the
master transmits the data byte to be written.
The 11AA02UID features a 16-byte page buffer, mean-
ing that up to 16 bytes can be written at one time. To
utilize this feature, the master can transmit up to 16
data bytes to the 11AA02UID, which are temporarily
stored in the page buffer. After each data byte, the
master sends a MAK, indicating whether or not another
data byte is to follow. A NoMAK indicates that no more
data is to follow, and as such will initiate the internal
write cycle.
Upon receipt of each word, the four lower-order
Address Pointer bits are internally incremented by one.
The higher-order bits of the word address remain con-
stant. If the master should transmit data past the end of
the page, the address counter will roll over to the begin-
ning of the page, where further received data will be
written.
FIGURE 4-3: WRITE COMMAND SEQUENCE
Note: If a NoMAK is generated before any data
has been provided, or if a standby pulse
occurs before the NoMAK is generated,
the 11AA02UID will be reset, and the write
cycle will not be initiated.
Note: Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes actu-
ally being written. Physical page boundar-
ies start at addresses that are integer
multiples of the page size (16 bytes) and
end at addresses that are integer multi-
ples of the page size minus 1. As an
example, the page that begins at address
0x30 ends at address 0x3F. If a page
Write command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data previ-
ously stored there), instead of being writ-
ten to the next page as might be expected.
It is therefore necessary for the applica-
tion software to prevent page write opera-
tions that would attempt to cross a page
boundary.
7654
Data Byte 1
32107654
Data Byte 2
32107654
Data Byte n
3210
SCIO
MAK
MAK
No MAK
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
10101100
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
15 14 13 12
Word Address MSB
11 10 9 8
MAK
SAK
7654
Word Address LSB
3210
MAK
SAK
SAK
SAK
SAK
Twc
11AA02UID
DS20005206A-page 12 2013 Microchip Technology Inc.
4.4 Write Enable (WREN) and Write
Disable (WRDI) Instructions
The 11AA02UID contains a write enable latch. See
Table 6-1 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI instruction will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
•WRDI instruction successfully executed
•WRSR instruction successfully executed
•WRITE instruction successfully executed
•ERAL instruction successfully executed
•SETAL instruction successfully executed
FIGURE 4-4: WRITE ENABLE COMMAND SEQUENCE
FIGURE 4-5: WRITE DISABLE COMMAND SEQUENCE
Note: The WREN and WRDI instructions must be
terminated with a NoMAK following the
command byte. If a NoMAK is not
received at this point, the command will be
considered invalid, and the device will go
into Idle mode without responding with a
SAK or executing the command.
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
10010011
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
01010010
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
2013 Microchip Technology Inc. DS20005206A-page 13
11AA02UID
4.5 Read Status Register (RDSR)
Instruction
The RDSR instruction provides access to the STATUS
register. The STATUS register may be read at any time,
even during a write cycle. The STATUS register is
formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
11AA02UID is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘0’, the latch
prohibits writes to the array. This bit is set and cleared
using the WREN and WRDI instructions, respectively.
This bit is read-only for any other instruction.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user through the WRSR instruction.
These bits are nonvolatile.
The WIP and WEL bits will update dynamically (asyn-
chronous to issuing the RDSR instruction). Further-
more, after the STATUS register data is received, the
master can provide a MAK during the Acknowledge
sequence to request that the data be transmitted again.
This allows the master to continuously monitor the WIP
and WEL bits without the need to issue another full
command.
Once the master is finished, it provides a NoMAK to
end the operation.
FIGURE 4-6: READ STATUS REGISTER COMMAND SEQUENCE
7654 3 2 1 0
XXXX BP1 BP0 WEL WIP
Note: Bits 4-7 are don’t cares, and will read as ‘0’.
Note: If Read Status Register command is
initiated while the 11AA02UID is currently
executing an internal write cycle on the
STATUS register, the new Block
Protection bit values will be read during
the entire command.
Note: The current drawn for a Read Status
Register command during a write cycle is
a combination of the ICC Read and ICC
Write operating currents.
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
11000000
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
STATUS Register Data
3210
NoMAK
SAK
The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAK.Note:
0000
11AA02UID
DS20005206A-page 14 2013 Microchip Technology Inc.
4.6 Write Status Register (WRSR)
Instruction
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the STATUS register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as
illustrated in Tabl e 4- 3 .
After transmitting the STATUS register data, the master
must transmit a NoMAK during the Acknowledge
sequence in order to initiate the internal write cycle.
TABLE 4-3: ARRAY PROTECTION
FIGURE 4-7: WRITE STATUS REGISTER COMMAND SEQUENCE
Note: The WRSR instruction must be terminated
with a NoMAK following the data byte. If a
NoMAK is not received at this point, the
command will be considered invalid, and
the device will go into Idle mode without
responding with a SAK or executing the
command.
BP1 BP0 Array Addresses
Write-Protected
00 none
01 upper 1/4
(C0h-FFh)
10 upper 1/2
(80h-FFh)
11 all
(00h-FFh)
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
10101101
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
7654
Status Register Data
3210
NoMAK
SAK
Twc
2013 Microchip Technology Inc. DS20005206A-page 15
11AA02UID
4.7 Erase All (ERAL) Instruction
The ERAL instruction allows the user to write ‘0x00’ to
the entire memory array with one command. Note that
the write enable latch (WEL) must first be set by issuing
the WREN instruction.
Once the write enable latch is set, the user may pro-
ceed with issuing a ERAL instruction (including the
header and device address bytes). Immediately after
the NoMAK bit has been transmitted by the master, the
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0x00’.
The ERAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not ‘0’, meaning 1/4, 1/2, or
all of the array is protected.
FIGURE 4-8: ERASE ALL COMMAND SEQUENCE
4.8 Set All (SETAL) Instruction
The SETAL instruction allows the user to write ‘0xFF’
to the entire memory array with one command. Note
that the write enable latch (WEL) must first be set by
issuing the WREN instruction.
Once the write enable latch is set, the user may pro-
ceed with issuing a SETAL instruction (including the
header and device address bytes). Immediately after
the NoMAK bit has been transmitted by the master, the
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0xFF’.
The SETAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not ‘0’, meaning 1/4, 1/2, or
all of the array is protected.
FIGURE 4-9: SET ALL COMMAND SEQUENCE
Note: The ERAL instruction must be terminated
with a NoMAK following the command
byte. If a NoMAK is not received at this
point, the command will be considered
invalid, and the device will go into Idle
mode without responding with a SAK or
executing the command.
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
11101100
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Twc
Note: The SETAL instruction must be termi-
nated with a NoMAK following the com-
mand byte. If a NoMAK is not received at
this point, the command will be consid-
ered invalid, and the device will go into
Idle mode without responding with a SAK
or executing the command.
11010100
Start Header
SCIO
Device Address
MAK
00001010
MAK
Command
11001101
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Twc
11AA02UID
DS20005206A-page 16 2013 Microchip Technology Inc.
5.0 DATA PROTECTION
The following protection has been implemented to
prevent inadvertent writes to the array:
• The Write Enable Latch (WEL) is reset on power-
up
•A Write Enable (
WREN) instruction must be issued
to set the write enable latch
• After a write, ERAL, SETAL, or WRSR command,
the write enable latch is reset
• Commands to access the array or write to the
STATUS register are ignored during an internal
write cycle and programming is not affected
6.0 POWER-ON STATE
The 11AA02UID powers on in the following state:
• The device is in low-power Shutdown mode,
requiring a low-to-high transition on SCIO to enter
Idle mode
• The Write Enable Latch (WEL) is reset
• The internal Address Pointer is undefined
• A low-to-high transition, standby pulse and subse-
quent high-to-low transition on SCIO (the first low
pulse of the header) are required to enter the
active state
.
TABLE 6-1: WRITE PROTECT FUNCTIONALITY MATRIX
WEL Protected Blocks Unprotected Blocks Status Register
0Protected Protected Protected
1Protected Writable Writable
2013 Microchip Technology Inc. DS20005206A-page 17
11AA02UID
7.0 PREPROGRAMMED UNIQUE
32-BIT SERIAL NUMBER
The 11AA02UID is programmed at the factory with a
unique 32-bit serial number stored in the upper 1/4 of
the array and write-protected through the STATUS
register. The remaining 1,536 bits are available for
application use.
FIGURE 7-1: MEMORY ORGANIZATION
The 4-byte serial number is stored in array locations
0xFC through 0xFF, as shown in Figure 7-2.
7.1 Manufacturer and Device Codes
In addition to the serial number, a manufacturer code is
stored at location 0xFA and a device identifier is stored
at 0xFB. The manufacturer code is fixed as 0x29. For
the 11AA02UID, the device identifier is ‘0x11’. The first
‘1’ indicates the UNI/O® bus family and the second ‘1’
indicates a 2 Kbit memory density.
7.2 Factory-Programmed Write
Protection
In order to help guard against accidental corruption of
the serial number, the BP1 and BP0 bits of the STATUS
register are programmed at the factory to ‘0’ and ‘1’,
respectively, as shown in the following table:
This protects the upper 1/4 of the array (0xC0 to 0xFF)
from write operations. This array block can be utilized
for writing by clearing the BP bits with a Write Status
Register (WRSR) instruction. Note that if this is
performed, care must be taken to prevent overwriting
the serial number.
FIGURE 7-2: SERIAL NUMBER PHYSICAL MEMORY MAP EXAMPLE
7.3 Extending the 32-bit Serial
Number
For applications that require serial numbers larger than
32 bits, additional data bytes can be used to pad the
provided serial number to meet the required length.
Any data byte values can be used for padding as the
32-bit serial number ensures the extended serial
number remains unique.
The padding can be performed in two ways. The first
method is to pad the data in software by combining the
32-bit serial number from the 11AA02UID with fixed
data. The second method is to extend the number of
bytes read from the 11AA02UID to meet the required
length. Table 7-1 shows example address ranges and
their corresponding serial number lengths.
TABLE 7-1: EXTENDED READ EXAMPLES
Note: The 32-bit serial number is unique across
all Microchip UID-family serial EEPROM
devices.
00h
C0h
FFh
Write-Protected
Serial Number Block
Standard
EEPROM
7654 3 2 1 0
XXXX BP1 BP0 WEL WIP
———— 01——
FAh FFh
Manufacturer
Code 32-bit Serial Number
29h
Description
Data
Array
Address
11h 12h 34h 56h 78h
Device
Code
SerializedFixed
Type
FBh FCh FDh FEh
Start Address End Address Serial Number
Length
0xFC 0xFF 32 bits
0xFA 0xFF 48 bits
0xF8 0xFF 64 bits
0xF0 0xFF 128 bits
0xE0 0xFF 256 bits
11AA02UID
DS20005206A-page 18 2013 Microchip Technology Inc.
8.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Tab l e 8- 1.
TABLE 8-1: PIN FUNCTION TABLE
8.1 Serial Clock, Data Input/Output
(SCIO)
SCIO is a bidirectional pin used to transfer commands
and addresses into, as well as data into and out of, the
device. The serial clock is embedded into the data
stream through Manchester encoding. Each bit is
represented by a signal transition at the middle of the
bit period.
Name 3-pin SOT-23 8-pin SOIC Description
SCIO 1 5 Serial Clock, Data Input/Output
VCC 2 8 Supply Voltage
VSS 3 4 Ground
NC — 1,2,3,6,7 No Internal Connection
2013 Microchip Technology Inc. DS20005206A-page 19
11AA02UID
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
Part Number
1st Line Marking Code
SOT-23 SOIC
I Temp. I Temp.
11AA02UID AABNNN 11A2UIDT
8-Lead SOIC
XXXXYYWW
XXXXXXXT
NNN
Example:
SN 1328
11A2UIDI
1L7
3
e
3-Lead SOT-23
XXXNNN
Example:
AAB1L7
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
11AA02UID
DS20005206A-page 20 2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc. DS20005206A-page 21
11AA02UID
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
11AA02UID
DS20005206A-page 22 2013 Microchip Technology Inc.
!"#$%
& !"#$%&"'""($)%
*++&&&!!+$
2013 Microchip Technology Inc. DS20005206A-page 23
11AA02UID
'''"'(%
&
1 !""%31%#%!%)"#""%)"#"""6%7!!"%
!"%3817
;<* ;"!"6=#"&&#"
& !"#$%&"'""($)%
*++&&&!!+$
>" ??33
!"?!" @ @A E
@#!G)(" @ H
?%( 7;<
A#"%?%( 1 1;<
A=J K 11
%%($$"" 7 1
%)) 1 1 K 1
A=L% 3 1 K N
%%($L% 31 11N 1H 1
A=? N H7
? ? 1H 7 N
O K 1O
?%$"" K
?%L% G H K 7
b
N
E
E1
2
1
e
e1
D
A
A1
A2
c
L
φ
& <1;
11AA02UID
DS20005206A-page 24 2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc. DS20005206A-page 25
11AA02UID
APPENDIX A: REVISION HISTORY
Revision A (05/2013)
Initial release.
11AA02UID
DS20005206A-page 26 2013 Microchip Technology Inc.
NOTES:
2013 Microchip Technology Inc. DS20005206A-page 27
11AA02UID
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
11AA02UID
DS20005206A-page 28 2013 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
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Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS20005206A11AA02UID
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2013 Microchip Technology Inc. DS20005206A-page 29
11AA02UID
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X X /XX
PackageTemperatureTape & Reel
Device
Device: 11AA02UID = 2 Kbit, 1.8V UNI/O Serial EEPROM with
32-bit Serial Number
Tape & Reel: T = Tape and Reel
Blank = Tube
Temperature
Range:
I=-40C to+85C(Industrial)
Package: SN = 8-lead Plastic SOIC (3.90 mm body)
TT = 3-lead SOT 23 (Tape and Reel only)
Examples:
a) 11AA02UIDT-I/TT = 2 Kbit, 1.8V Serial
EEPROM with 32-bit serial number, Industrial
temp., Tape & Reel, SOT-23 package
b) 11AA02UID-I/SN = 2 Kbit, 1.8V Serial
EEPROM with 32-bit serial number, Industrial
temp., SOIC package
c) 11AA02UIDT-I/SN = 2 Kbit, 1.8V Serial
EEPROM with 32-bit serial number, Industrial
temp., Tape & Reel, SOIC package
Range
11AA02UID
DS20005206A-page 30 2013 Microchip Technology Inc.
NOTES:
2013 Microchip Technology Inc. DS20005206A-page 31
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620772287
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005206A-page 32 2013 Microchip Technology Inc.
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Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
11/29/12
