CS4270 - Cirrus Logic, Inc.

http://www.cirrus.com

Advance Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

24-Bit, 192 kHz Stereo Audio CODEC

D/A Features

High Performance

– 105 dB Dynamic Range

– -95 dB THD+N

Selectable Serial Audio Interface Formats

– Left-Justified up to 24-bit

– I²S up to 24-bit

– Right-Justified 16-, and 24-Bit

Control Output for External Muting

On-Chip Digital De-Emphasis

Popguard Technology

Multi-bit ∆Σ Conversion

Digital Volume Control

A/D Features

High Performance

– 105 dB Dynamic Range

– -95 dB THD+N

Multi-bit Delta Sigma Conversion

High-Pass Filter to remove DC Offsets

Selectable Serial Audio Interface Formats

– Left-Justified up to 24-bit

– I²S up to 24-bit

System Features

Direct Interface with Logic Levels 1.8 V to 5 V

Internal Digital Loopback

Stand-Alone or Control Port Functionality

Single-Ended Analog Architecture

Supports all Audio Sample Rates from 4 kHz to

216 kHz

Control Port Supply

1.8 V to 5 V

Configuration

Internal Voltage

Reference

Reset

Serial Interface

Level Translator

Digital Supply

3.3 V to 5 V

Hardware Mode or

I2C/SPI Software Mode

Control Data

Analog Supply

3.3 V to 5 V

Single-Ended

Outputs

PCM Serial

Audio In put Volume

Controls Digital

Filters Switch-Cap

DAC and

Analog Filters

Multi-bit ∆Σ

Modulators

External Mute

Control Mute Signals

Switch-Cap

ADC Single-Ended

Inputs

Digital

Filters

High-Pass

Filter

PCM Serial

Audio Output

MAY '05

DS686A1

CS4270

2DS686A1

CS4270

Stand-Alone Mode Feature Set

System Features

– Serial Audio Port Master or Slave Operation

– Single, Doub le , or Qu ad -Speed Operation

D/A Features

– Auto-mute on Static Samples

– 44.1 kHz 50/15 µs De-emphasis Available

– Selectable Serial Audio Interface Formats

Left-Justified up to 24-bit

I²S up to 24-bit

A/D Features

– High-Pass Filter

– Selectable Serial Audio Interface Formats

Left-Justified up to 24-bit

I²S up to 24-bit

Software Mode Feature Set

System Features

– Serial Audio Port Master or Slave Operation

– Internal Digital Loopback Available

D/A Features

– Selectable Auto-mute

– 44.1-kHz De-emphasis Filters

– Configurable Muting Controls

– Volume Control

– Selectable Serial Audio Interface Formats

Left-Justified up to 24-bit

I²S up to 24-bit

Right Justified 16, and 24-bit

A/D Features

– Selectable High-Pass Filter or DC Offset

Calibration

– Selectable Serial Audio Interface Formats

Left-Justified up to 24-bit

I²S up to 24-bit

General Description

The CS4270 is a high-performance, integrated audio

CODEC. The CS4270 perfor ms stereo analog- to-digital

(A/D) and digital-to-analog (D/A) conversion of up to

24-bit serial values at sample rates up to 216 kHz.

Standard 50/15 µs de-emphasis is available for sam-

pling rates of 44.1 kHz for compatibility with digital audio

programs mastered using the 50/15 µs pre-emphasis

technique.

Integrated level translators allow easy interfacing be-

tween the CS4270 and other devices operating over a

wide range of logic levels.

Independently addressable high-pass filters are avail-

able for the right and left channe l of the A/D. This allows

the A/D to be used in a wide variety of applications

where one audio channel and one DC measurement

channel is desired.

The CS4270’s wide dynamic range, negligible distor-

tion, and low noise make it ideal for applications such as

DVD-recorders, digital televisions, set top boxes, ef-

fects processors, and automotive audio systems.

ORDERING INFORMATION

Product Description Package Pb-Free Grade Temp Range Container Order #

CS4270 24-Bit 192 kHz Stereo

Audio CODEC 24-TSSOP YES Commercial -10° to +85° C Rail CS4270-CZZ

Tape & Reel CS4270-CZZR

CS4270 24-Bit 192 kHz Stereo

Audio CODEC 24-TSSOP YES Commercial -40° to +85° C Rail CS4270-DZZ

Tape & Reel CS4270-DZZR

CDB4270 CS4270 Evaluation Board - - - - - CDB4270

DS686A1 3
CS4270
TABLE OF CONTENTS
1.  PIN DESCRIPTIONS - SOFTWARE MODE ............................................................................. 6
2.  PIN DESCRIPTIONS - STAND-ALONE MODE ....................................................................... 7
3.  CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8
SPECIFIED OPERATING CONDITIONS................................................................................. 8
ABSOLUTE MAXIMUM RATINGS........................................................................................... 8
THERMAL CHARACTERISTICS.............................................................................................. 8
DAC ANALOG CHARACTERISTICS (CS4270-CZZ)............................................................... 9
DAC ANALOG CHARACTERISTICS (CS4270-DZZ)............................................................... 9
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 11
ADC ANALOG CHARACTERISTICS (CS4270-CZZ)............................................................. 12
ADC ANALOG CHARACTERISTICS (CS4270-DZZ)............................................................. 13
ADC ANALOG CHARACTERISTICS - ALL MODES ............................................................. 14
ADC DIGITAL FILTER CHARACTERISTICS ........................................................................ 14
DC ELECTRICAL CHARACTERISTICS ............. ... ... .... ... ... ... .................... ... ... ... .... ... ... ... ... ... 15
DIGITAL CHARACTERISTICS............................................................................................... 16
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 16
SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT....................................... 19
SWITCHING CHARACTERISTICS - SPI CONTROL PORT.................................................. 20
4.  TYPICAL CONNECTION DIAGRAM  ..................................................................................... 21
5.  APPLICATIONS  ..................................................................................................................... 22
5.1 Stand-Alone Mode .............. ... .... ... ................... ... .... ... ... ... .... ... ... ... .................... ... ... ... ... ...22
5.1.1 Recommended Power-Up Sequence  ................................................................. 22
5.1.2 Master/Slave Mode ............................................................................................. 22
5.1.3 System Clocking .............. ... ................... .... ... ... ... .... ................... ... ... .... ... ... ......... 22
5.1.4 Clock Ratio Selection .......................................................................................... 23
5.1.5  Interpolation Filter .............................................................................................. 23
5.1.6 High-Pass Filter  .. ... ... .... ... ... ................... .... ... ... ... .... ... ................... ... .... ... ... ... ... ... 23
5.1.7 Mode Selection & De-Emphasis ......................................................................... 24
5.1.8 Serial Audio Interface Format Selection ............................................................. 24
5.2 Control Port Mode  ........................ ... ... ... .... ... ................... .... ... ... ... ... .................... ... ... ... . .. 24
5.2.1 Recommende d Power-Up Sequence - Access to Control Port Mode  ................ 24
5.2.2 Master / Slave Mode Selection ........................................................................... 24
5.2.3 System Clocking .............. ... ................... .... ... ... ... .... ... ................... ... .... ... ... ... ... ... 25
5.2.4 Clock Ratio Selection .......................................................................................... 25
5.2.5 Internal Digital Loopback  .................................................................................... 26
5.2.6 Auto-Mute  .... .................... ... ... ... .... ... ... .................... ... ... ... ... .... ... ................... ... ... 26
5.2.7 High-Pass Filter and DC Offset Calibration ........................................................ 26
5.2.8 De-Emphasis  ... ... ... ... .... ... ... ................... .... ... ... ... .... ................... ... ... .... ... ... ......... 27
5.2.9 Oversampling Modes .......................... ... .... ... ... ... .... ... ... ... ... .................... ... ... ... ... 27
5.3 De-Emphasis Filter ....... ... ... ... .................... ... ... ... .... ... ... ... .................... ... ... ... .... ... ... ......... 27
5.4 Analog Connections  ..................... ... ... ... .... ... ... ... .... ................... ... ... .... ... ... ... .... ... ... ......... 28
5.4.1 Input Connections ..................... .... ................... ... .... ... ... ... ... .................... ... ... ... ... 28
5.4.2 Output Connections ...................... ... ................... .... ... ... ... ... .... ... ... ................... ... 29
5.5 Mute Control ............. .... ... ... ... .................... ... ... ... .... ... ... ... .... ... ................... ... .... ... ... ......... 29
5.6 Synchronization of Multiple Devices ................................................................................ 30
5.7 Grounding and Power Supply Decoupling ....................................................................... 30
6.  CONTROL PORT INTERFACE .............................................................................................. 31
6.1 SPI™ Mode  ..... ... ... ... .... ... ... ... .................... ... ... ... .... ... ... ................... .... ... ... ... .... ... ............ 31
6.2 I²C Mode ................................ .... ... ... ... ... .... ................... ... .... ... ... ... ... .................... ... ......... 32
7.  REGISTER QUICK REFERENCE .......................................................................................... 33
8.  REGISTER DESCRIPTION .................................................................................................... 34
8.1 Chip ID - Address 01h  ..................................................................................................... 34

4DS686A1
CS4270
8.2 Power Control - Address 02h  .......................................................................................... 34
8.2.1 Freeze (Bit 7) ...................................................................................................... 34
8.2.2 PDN_ADC (Bit 5) ................................................................................................ 34
8.2.3 PDN_DAC (Bit 1) ................................................................................................ 34
8.2.4 Power Down (Bit 0) ............................................................................................. 34
8.3 Mode Control - Address 03h ............................................................................................ 35
8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) .................................... 35
8.3.2 Ratio Select (Bits 3:1) ......................................................................................... 35
8.3.3 PopGuard Disable (Bit 0) .................................................................................... 35
8.4 ADC and DAC Control - Address 04h  ............................................................................. 35
8.4.1 ADC HPF Freeze A (Bit 7) .................................................................................. 35
8.4.2 ADC HPF Freeze B (Bit 6) .................................................................................. 36
8.4.3 Digital Loopback (Bit 5) ....................................................................................... 36
8.4.4 DAC Digital Interface Format (Bits 4:3) ............ ............. ............. ............. ............ 36
8.4.5 ADC Digital Interface Format (Bit 0)  ................................................................... 36
8.5 Transition Control - Address 05h ..................................................................................... 37
8.5.1 DAC Single Volume (Bit 7) .................................................................................. 37
8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ........................................................ 37
8.5.3 Invert Signal Polarity (Bits 4:1) ............................................................................ 37
8.5.4 De-Emphasis Control (Bit 0) ............................................................................... 38
8.6 Mute Control - Address 06h ............................................................................................. 38
8.6.1 Auto-Mute (Bit 5) ................................................................................................. 38
8.6.2 ADC Channel A & B Mute (Bits 4:3)  ................................................................... 38
8.6.3 Mute Polarity (Bit 2)  ............................................................................................ 38
8.6.4 DAC Channel A & B Mute (Bits 1:0)  ................................................................... 38
8.7 DAC Channel A Volume Control - Address 07h .............................................................. 39
8.8 DAC Channel B Volume Control - Address 08h .............................................................. 39
10.  PACKAGE DIMENSIONS  .................................................................................................... 41
11.  APPENDIX      ....................................................................................................................... 42
12.  REVISION HISTORY ............................................................................................................ 48
LIST OF FIGURES
Figure 1. Output Test Load ....................................................................................................................... 10
Figure 2. Maximum Loading ...................................................................................................................... 10
Figure 3. Master Mode Serial Audio Port Timing ...................................................................................... 17
Figure 4. Slave Mode Serial Audio Port Timing ........................................................................................ 17
Figure 5. Format 0, Left Justified up to 24-Bit Data .................................................................................. 18
Figure 6. Format 1, I²S up to 24-Bit Data .................................................................................................. 18
Figure 7. Format 2, Right Justified 16-Bit Data. (Available in Control Port Mode only)
Format 3, Right Justified 24-Bit Data. (Available in Control Port Mode only) ............ ................ ................ 18
Figure 8. I²C Mode Control Port Timing .................................................................................................... 19
Figure 9. SPI Control Port Timing .......................... ... ... ... .... ................... ... ... .... ... ... ... .... ... ... ... ... ................ 20
Figure 10. CS4270 Typical Connection Diagram ......................... .... ... ... ... ... .... ... ... ....................... ... ... ...... 21
Figure 11. De-Emphasis Curve ................................................................................................................. 27
Figure 12. CS4270 Recommended Analog Input Network ....................................................................... 28
Figure 13. CS5344 Example Analog Input Network .................................................................................. 29
Figure 14. CS4270 Recommended Analog Output Filter .......................................................................... 29
Figure 15. Suggested Active-Low Mute Circuit ......................................................................................... 30
Figure 16. Control Port Timing, SPI mode .......................... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 31
Figure 17. Control Port Timing, I²C Mode .... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 32
Figure 18. De-Emphasis Curve ................................................................................................................. 38
Figure 19. DAC Single-Speed (fast) Stopband Rejection ................... ... ... ... ....................... ... ... .... ... ... ... ... 42
Figure 20. DAC Single-Speed (fast) Transition Band ............................................................................... 42

DS686A1 5
CS4270
Figure 21. DAC Single-Speed (fast) Transition Band (detail)  ................................................................... 42
Figure 22. DAC Single-Speed (fast) Passband Ripple  .............................................................................42
Figure 23. DAC Single-Speed (slow) Stopband Rejection ........................................................................ 42
Figure 24. DAC Single-Speed (slow) Transition Band .............................................................................. 42
Figure 25. DAC Single-Speed (slow) Transition Band (detail) .................................................................. 43
Figure 26. DAC Single-Speed (slow) Passband Ripple ......................... ... ... .... ... ... ... .... ... ... ... ... ................ 43
Figure 27. DAC Double-Speed (fast) Stopband Rejection ........................................................................ 43
Figure 28. DAC Double-Speed (fast) Transition Band .............................................................................. 43
Figure 29. DAC Double-Speed (fast) Transition Band (detail) .................................................................. 43
Figure 30. DAC Double-Speed (fast) Passband Ripple ............................................................................ 43
Figure 31. DAC Double-Speed (slow) Stopband Rejection  ...................................................................... 44
Figure 32. DAC Double-Speed (slow) Transition Band .............................................................................44
Figure 33. DAC Double-Speed (slow) Transition Band (detail) ........ ................ ................ ................ ......... 44
Figure 34. DAC Double-Speed (slow) Passband Ripple ........................................................................... 44
Figure 35. DAC Quad-Speed (fast) Stopband Rejection  .......................................................................... 44
Figure 36. DAC Quad-Speed (fast) Transition Band ................................................................................. 44
Figure 37. DAC Quad-Speed (fast) Transition Band (detail) ..................................................................... 45
Figure 38. DAC Quad-Speed (fast) Passband Ripple ...............................................................................45
Figure 39. DAC Quad-Speed (slow) Stopband Rejection ...................... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 45
Figure 40. DAC Quad-Speed (slow) Transition Band ...............................................................................45
Figure 41. DAC Quad-Speed (slow) Transition Band (detail) ................................................................... 45
Figure 42. DAC Quad-Speed (slow) Passband Ripple ............................................................................. 45
Figure 43. ADC Single-Speed Mode Stopband Rejection  ........................................................................ 46
Figure 44. ADC Single-Speed Mode Transition Band ...............................................................................46
Figure 45. ADC Single-Speed Mode Transition Band (Detail) .................................................................. 46
Figure 46. ADC Single-Speed Mode Passband Ripple ............................................................................. 46
Figure 47. ADC Double-Speed Mode Stopband Rejection ....................................................................... 46
Figure 48. ADC Double-Speed Mode Transition Band ............................................................................. 46
Figure 49. ADC Double-Speed Mode Transition Band (Detail) ................................................................. 47
Figure 50. ADC Double-Speed Mode Passband Ripple ........................................................................... 47
Figure 51. ADC Quad-Speed Mode Stopband Rejection .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ................... 47
Figure 52. ADC Quad-Speed Mode Transition Band ...... .... ... ... ... .... ...................... ................................... 47
Figure 53. ADC Quad-Speed Mode Transition Band (Detail) ...................... .... ... ... ... .... ... ... ... ... ................ 47
Figure 54. ADC Quad-Speed Mode Passband Ripple ........ ... ... ... .... ... ... ... ... .... ... ... ... ....................... ... ... ... 47
LIST OF TABLES
Table 1. Speed Modes.. ... ................... .... ... ... ... ... .... ... ... .................... ... ... ... ... .... ... ... ... .... ......................... ..  22
Table 2. Clock Ratios - Stand-Alone Mode...............................................................................................  23
Table 3. CS4270 Stand-Alone Mode Control............................................................................................  24
Table 4. Speed Modes.. ... ................... .... ... ... ... ... .... ... ... .................... ... ... ... ... .... ... ... ... .... ......................... ..  25
Table 5. Clock Ratios - Control Port Mode................................................................................................  25
Table 6. Analog Input Design Parameters................................................................................................  28
Table 7. Memory Address Pointer . ... ... .... ... ... ... ... .................... ... ... .... ... ... ... ... .... ... ... ... .... ...................... ... ..  32
Table 8. Functional Mode Selection.... .... ... ................... ... .... ... ... ... .... ... ... ... ... .... ... ................... ... .... ... ... ... ..  35
Table 9. MCLK Divider Configuration...................................................................................................... ..  35
Table 10. DAC Digital Interface Formats ... ... ... ... .......................................... .......................................... ..  36
Table 11. ADC Digital Interface Formats ... ... ... ... .......................................... .......................................... ..  36
Table 12. Soft Cross or Zero Cross Mode Selection................................................................................. 37
Table 13. Digital Volume Control ........ .... ... ... ............................................................................................  39

6DS686A1

CS4270

1. PIN DESCRIPTIONS - SOFTWARE MODE

Pin Name # Pin Description

SDIN 1Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 2Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

MCLK 3Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

SCLK 4Serial Clock (Input/Output) - Serial clock for the serial audio interface.

VD 5Digital Power (Input) - Positive power supply for the digital section.

DGND 6Digital Ground (Input) - Ground reference for the internal digital section.

SDOUT 7Serial Audio Da ta Output (Output) - Output for two’s complement serial audio data.

VLC 8Control Port Power (Input) - Determines the signal level for the control port.

SDA/CDOUT 9Serial Control Data (Input/Output) - SDA is a data I/O in I²C mode. CDOUT is the output data line for

the control port interface in SPI mode.

SCL/CCLK 10 Serial Control Port Clock (Input) - Serial clock for the serial control port.

AD0/CS 11 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode.

CS is the chip select signal for SPI format.

AD1/CDIN 12 Address Bit 1 (I²C) / Serial Control Data (Input) - AD1 is a chip address pin in I²C mode. CDIN is the

input data line for the control port interface in SPI mode.

AD2 13 Address Bit 2 (I²C) (Input) - AD2 is a chip address pin in I²C mode.

RST 14 Reset (Input) - The device enters a low pow er mode when low.

AINA

AINB 15

16 Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics

specification table.

VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VA 19 Analog Power (Input) - Positive power for the analog sections.

AGND 20 Analog Ground (Input) - Ground reference. Must be connected to analog ground.

MUTEA

MUTEB 21

24 Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master

clock to left/right clock frequency ratio is incorrect, or power-down.

AOUTA

AOUTB 22

23 Analog Audio Outp ut (Output) - The full-scale output level is specified in the DAC Analog Character-

istics specification table.

SDIN

LRCK

MCLK

SCLK

DGND

SDOUT

VLC

SDA/CDOUT

SCL/CCLK

AD0/CS

AD1/CDIN

MUTEB

AOUTB

AOUTA

MUTEA

AGND

FILT+

AINB

AINA

RST

AD2

DS686A1 7

CS4270

2. PIN DESCRIPTIONS - STAND-ALONE MODE

Pin Name # Pin Description

SDIN 1Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 2Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

MCLK 3Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

SCLK 4Serial Clock (Input/Output) - Serial clock for the serial audio interface.

VD 5Digital Power (Input) - Positive power supply for the digital section.

DGND 6Digital Ground (Input) - Ground reference for the internal digital section.

SDOUT

(M/S) 7Serial Audio Data Outp ut (Output) - Output for two’s complement serial audi o data. This pin must be

pulled-up or pulled-down to sel ect Master or Slav e Mode.

VLC 8Control Port Power (Input) - Determines the signal level for the control port.

M0 9

10 Mode Selection (Input) - Determines the operational mode of the devic e.

I²S/LJ 11 Serial Audio Interface Select (Input) - Selects eit he r th e le ft-justified orI²S format for the Serial Audio

Interface.

MDIV1

MDIV2 12

13 MCLK Divide (Input) - Configures MCLK divider to divide by 1, 1.5, 2, or 4.

RST 14 Reset (Input) - The device enters a low pow er mode when low.

AINA

AINB 15

16 Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics

specification table.

VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VA 19 Analog Power (Input) - Positive power for the anal og s ect io n s.

AGND 20 Analog Ground (Input) - Ground reference. Must be connected to analog ground.

MUTEA

MUTEB 21

24 Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master

clock to left/right clock frequency ratio is incorrect, or power-down.

AOUTA

AOUTB 22

23 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris-

tics specificati on table.

SDIN

LRCK

MCLK

SCLK

DGND

SDOUT

VLC

I²S/LJ

MDIV1

MUTEB

AOUTB

AOUTA

MUTEA

AGND

FILT+

AINB

AINA

RST

MDIV2

8DS686A1

CS4270

3. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max char ac te rist ics an d sp ecif ica tio ns ar e gu ara nt ee d over the Specified Operating Conditions. Typical

performance characteristic s and spe cifications are deriv e d from measurements taken at nominal supply voltages

and TA = 25°C.)

SPECIFIED OPERATING CONDITIONS

(AGND = 0 V; all voltages with respect to ground.)

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V, All voltages with respect to gr ound.) (Note 1)

Notes:

1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extreme s.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SRC

latch-up.

THERMAL CHARACTERISTICS

3. θJA is specified according to JEDEC specifications for multi-layer PCBs.

Parameters Symbol Min Nom Max Units

DC Power Supplies: Analog

Digital

Control Port Interface

VLC

3.1

1.7

5.0

3.3

5.25

Ambient Operating Temperature (Power Applied) (-CZZ)

(-DZZ) TA-CZZ

TA-DZZ

-10

-40 -

-+70

+85 °C

°C

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Digital

Control Port Interface

VLC

-0.3

+6.0

Input Current (Note 2)Iin -10 - +10 mA

Analog Input Voltage VIN AGND-0.7 - VA+0.7 V

Digital Input Voltage Control Port Interface

Digital Interface VIND-C

VIND-D -0.3

-0.3 -VLC+0.3

VD+0.3 V

Ambient Operating Temperature (Power Applied) TAC -50 - +95 °C

Storage Temperature Tstg -65 - +150 °C

Parameters Symbol Min Typ Max Units

Allowable Junction Temperature - - 135 °C

Junction to Ambient Thermal Impedance (Note 3)

(Multi-layer PCB) TSSOP

(Multi-layer PCB) SOIC

(Single-layer PCB) TSSOP

(Single-layer PCB) SOIC

θJA-TM

θJA-SM

θJA-TS

θJA-SS

105

°C/W

DS686A1 9

CS4270

DAC ANALOG CHARACTERISTICS (CS4270-CZZ)

(Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF

(see Figure 1). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)

DAC ANALOG CHARACTERISTICS (CS4270-DZZ)

(Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 10 pF

(see Figure 1). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)

4. One-half LSB of triangular PDF dither added to data.

Parameter

VA = 5V VA = 3.3V

Min Typ Max Min Typ Max Unit

Dynamic Range 18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

105

102

103

100

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-95

-82

-42

-93

-73

-33

-89

-76

-36

-87

-67

-27

-95

-80

-40

-93

-73

-33

-89

-74

-34

-87

-67

-27

Parameter

VA = 5V VA = 3.3V

Min Typ Max Min Typ Max Unit

Dynamic Range 18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

105

102

103

100

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-95

-82

-42

-93

-73

-33

-85

-72

-32

-83

-63

-23

-95

-80

-40

-93

-73

-33

-85

-70

-30

-83

-63

-23

10 DS686A1

CS4270

DAC ANALOG CHARACTERISTICS - ALL MODES

Parameter Symbol Min Typ Max Unit

Interchannel Isolation (1 kHz) -100-dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 0.25 dB

Gain Drift -100 +100 ppm/°C

Analog Output

Full Scale Outp ut Voltage 0.640•VA 0.688•VA 0.739•VA Vpp

Max DC Current draw from AOUTA or AOUTB IOUTmax -10-µA

Max AC-Load Resistance (see Figure 2) RL-3-kΩ

Max Load Capacitance (see Figure 2) CL-100-pF

Output Impedance of AOUTA and AOUTB ZOUT -100-Ω

AOUTx

AGND

3.3 µF

Vout

RLCL

100

2.5

51015

Safe Operating

Region

C a p a c itiv e Lo a d - - C ( pF)

Resistive Load -- R (k

Ω

)

125

320

Figure 1. Output Test Load Figure 2. Maximum Loading

DS686A1 11

CS4270

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-

ple rate by multiplying the giv en characteristic by Fs.) (See Note 5)

5. Amplitude vs. Frequency plots of this data are available in Section 11. “Appendix” on page 42. See

Figures 19 through 42.

6. Response is clock dependent and will scale with Fs.

7. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.

For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.

For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.

8. De-emphasis is available only in Single-Speed Mode.

Parameter Symbol Min Typ Max Unit

Single-Speed Mode

Passband (Note 6) t o -0 .0 5 dB corner

to -3 dB corner 0

-.4780

.4996 Fs

Frequency Response 10 Hz to 20 kHz -.01 - +.08 dB

StopBand .5465 - - Fs

StopBand Attenuation (Note 7)50 - - dB

Group Delay tgd - 10/Fs - s

De-emphasis Error (Note 8) Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

+1.5/+0

+.05/-.25

-.2/-.4

Double-Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner 0

-.4650

.4982 Fs

Frequency Response 10 Hz to 20 kHz -.05 - +.2 dB

StopBand .5770 - - Fs

StopBand Attenuation (Note 7)55 - - dB

Group Delay tgd - 5/Fs - s

Quad-Speed Mode

Passband (Note 6) to -0.1 dB corner

to -3 dB corner 0

-0.397

0.476 Fs

Frequency Response 10 Hz to 20 kHz 0 - +0.00004 dB

StopBand 0.7 - - Fs

StopBand Attenuation (Note 7)51 - - dB

Group Delay tgd - 2.5/Fs - s

12 DS686A1

CS4270

ADC ANALOG CHARACTERISTICS (CS4270-CZZ)

Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.

9. Referred to the typical full-scale input voltage.

Parameter Symbol

VA = 5V VA = 3.3V

Min Typ Max Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted 99

96 105

102 -

-96

93 102

99 -

-dB

Total Harmonic Distortion + Noise (Note 9)

-1 dB

-20 dB

-60 dB

THD+N -

-98

-82

-42

-92

-95

-79

-39

-89

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise (Note 9)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-98

-82

-42

-95

-92

-95

-79

-39

-87

-89

Quad-Speed Mode Fs = 192 k Hz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise (Note 9)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-98

-82

-42

-95

-92

-95

-79

-39

-87

-89

DS686A1 13

CS4270

ADC ANALOG CHARACTERISTICS (CS4270-DZZ)

Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.

10. Referred to the typical full-scale input voltage.

Parameter Symbol

VA = 5V VA = 3.3V

Min Typ Max Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted 97

94 105

102 -

-94

91 102

99 -

-dB

Total Harmonic Distortion + Noise (Note 10)

-1 dB

-20 dB

-60 dB

THD+N -

-98

-82

-42

-90

-95

-79

-39

-87

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise (Note 10)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-98

-82

-42

-95

-90

-95

-79

-39

-87

Quad-Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise (Note 10 )

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-98

-82

-42

-95

-90

-95

-79

-39

-87

14 DS686A1

CS4270

ADC ANALOG CHARACTERISTICS - ALL MODES

ADC DIGITAL FILTER CHARACTERISTICS (Note 11)

(Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified)

Interchannel Isolation -90-dB

DC Accuracy

Interchannel Gain Mismatch -0.1-dB

Gain Error -3 - 3 %

Gain Drift -100 - +100 ppm/°C

Analog Input Characteristics

Full-scale Input Voltage 0.54*V

A0.56*VA 0.58*V

AVpp

Input Impedance -300-kΩ

Parameter Symbol Min Typ Max Unit

Single-Speed Mode

Passband (-0.1 dB) (Note 12)0 - 0.47 Fs

Passband Ripple -0.1 - 0.035 dB

Stopband (Note 12)0.58 - - Fs

Stopband Attenuation -95 - - dB

Group Delay tgd -12/Fs- s

Interchannel Phase Deviation - - 0.0001 deg

Double-Speed Mode

Passband (-0.1 dB) (Note 12)0 - 0.45 Fs

Passband Ripple -0.1 - 0.035 dB

Stopband (Note 12)0.68 - - Fs

Stopband Attenuation -92 - - dB

Group Delay tgd -9/Fs- s

Interchannel Phase Deviation - - 0.0001 deg

Quad-Speed Mode

Passband (-0.1 dB) (Note 12)0 - 0.24 Fs

Passband Ripple -0.1 - 0.035 dB

Stopband (Note 12)0.78 - - Fs

Stopband Attenuation -97 - - dB

Group Delay tgd -5/Fs- s

Interchannel Phase Deviation - - 0.0001 deg

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 13)-1

20 -

-Hz

Phase Deviation @ 20 Hz (Note 13)-10-deg

DS686A1 15

CS4270

11. Plots of this data are contained in Section 11. “Appendix” on page 42. See Figures 43 through 54.

12. The filter frequency response scales precisely with Fs.

13. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

DC ELECTRICAL CHARACTERISTICS

(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; MLCK=12.288 MHz; Master Mode)

14. Power Down Mode is defined as RST = Low with all clocks and data lines held static.

15. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Dia-

gram.

Passband Ripple --0dB

Filter Settling Time 105/Fs s

Parameter Symbol Min Typ Max Unit

Power Supply

Power Supply Current VA = 5 V

(Normal Operation) VA = 3.3 V

VD, VLC = 5 V

VD, VLC = 3.3 V

Power Supply Current VA = 5 V

(Power-Down Mode) (Note 14) VD, VLC = 5 V IA

-1.51

0.45 -

-mA

Power Consumption

VA = 5 V, VD = VLC= 3.3 V Normal Operation

VA = 5 V, VD = VLC = 5 V Normal Operation

Power-Down Mode (Note 14)

221

255

9.8

296

323

Power Supply Rejection Ratio (1 kHz) (Note 15)PSRR - 60 - dB

Common Mode Voltage

Nominal Common Mode Voltage VQ - VA/2 - VDC

Maximum DC Current Source/Sink from VQ -1-µA

VQ Output Impedance -25-kΩ

Positive Voltage Reference

FILT+ Nominal Voltage FILT+ - VA - VDC

Maximum DC Current Source/Sink from FILT+ -10-µA

FILT+ Output Impedance -18-kΩ

Mute Control

MUTEA, MUTEB Low-Level Output Voltage -0-V

MUTEA, MUTEB High-Level Output Voltage -VA-V

Maximum MUTEA & MUTEB Drive Current -3-mA

Parameter Symbol Min Typ Max Unit

16 DS686A1

CS4270

DIGITAL CHARACTERISTICS

16. Serial Port signals include: SCLK, LRCK, SDOUT, SDIN

Control Port signals include: SDA/CDOUT, SCL/CCLK, AD1/CDIN, AD0/CS, RST

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT

(Logic "0" = AGND = 0 V; Logic "1" = VD, CL = 20 pF)

Parameter (Note 16)Symbol Min Typ Max Units

High-Level Input Voltage Serial Port

Control Port VIH 0.7xVD

0.7xVLC -

-V

Low-Level Input Vo ltage Serial Port

Control Port VIL -

-0.2xVD

0.2xVLC V

High-Level Output V olt age at Io = 2 mA Serial Port

Control Port

MUTEA, MUTEB

VOH VD - 1.0

VLC - 1.0

VA - 1.0

Low-Level Output Voltage at Io = 2 mA VOL --0.4V

Input Leakage Current Iin -10 - 10 µA

Parameter Symbol Min Typ Max Unit

Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

100

108

216

kHz

MCLK Specifications

MCLK Frequency Stand-Alone Mode

(Note 17) Control Port Mode fmclk

fmclk 1.024

1.024 -

-55.296

55.296 MHz

MHz

MCLK Duty Cycle 40 50 60 ns

Master Mode

LRCK Duty Cycle -50-%

SCLK Period --s

SCLK Duty Cycle -50-%

SCLK falling to LRCK edge tslr -10 - 10 ns

SCLK falling to SDOUT valid tsdo - - 32 ns

SDIN valid to SCLK rising setup time tsdis 16 - - ns

SCLK rising to SDIN hold time tsdih 20 - - ns

Slave Mode

LRCK Duty Cycle 40 50 60 %

SCLK Period

(Note 17) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

tsclkw

SCLK Duty Cycle 45 50 55 ns

SCLK falling to LRCK edge tslr -10 - 10 ns

64()Fs

------------------

128()Fs

---------------------

128()Fs

---------------------

64()Fs

------------------

DS686A1 17

CS4270

17. In Control Port Mode, MCLK Frequency and Functional Mode Select bits must be configured according to

Table 5, Table 9, and Table 8

SCLK falling to SDOUT valid tsdo - - 32 ns

SDIN valid to SCLK rising setup time tsdis 16 - - ns

SCLK rising to SDIN hold time tsdih 20 - - ns

sdis

slr

SDOUT

SCLK

Output

LRCK

Output

SDIN

sdo

sdih

sdis

slr

SDOUT

SCLK

Input

LRCK

Input

SDIN

sdo

sdih

sclkw

Figure 3. Master Mode Serial Audio Port Timing

Figure 4. Slave Mode Serial Audio Port Timing

18 DS686A1

CS4270

Figure 5. Format 0, Left Justified up to 24-Bit Data

LRCK

SCLK

Left Channel Right Channel

SDATA +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4 -5 +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4

Figure 6. Format 1, I²S up to 24-Bit Data

LRCK

SCLK

Left Channel Right Channel

SDATA +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4 -5 +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4

LRCK

SCLK

Left Channel

SDATA +5 +4 +3 +2 +1 LSB

MSB-1-2-3-4-5

32 clocks

Right Channel

LSB +5 +4 +3 +2 +1 LSB

MSB - 1 - 2 - 3 - 4 -5

-6 +6

-6

Figure 7. Format 2, Right Justified 16-Bit Data. (Available in Control Port Mode only)

Format 3, Right Justified 24-Bit Data. (Available in Control Port Mode only)

DS686A1 19

CS4270

SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT

(Inputs: logic 0 = DGND, logic 1 = VLC)

18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Parameter Symbol Min Max Unit

I²C Mode

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to S tart tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated Start Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 18)thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise Time of Both SDA and SCL Lines tr-1µs

Fall Time of Both SDA and SCL Lines tf-300ns

Setup Time for Stop Condition tsusp 4.7 - µs

buf thdst

hdst

low

hdd

thigh

sud

sust

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

irs

RST

Figure 8. I²C Mode Control Port Timing

20 DS686A1

CS4270

SWITCHING CHARACTERISTICS - SPI CONTROL PORT

(Inputs: logic 0 = DGND, logic 1 = VLC)

19. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

20. Data must be held for sufficient time to bridge the transition time of CCLK.

21. For FSCK < 1 MHz

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency fsclk -6MHz

RST Rising Edge to CS Falling tsrs 500 - ns

CCLK Edge to CS Falling (Note 19)tspi 500 - ns

CS High Time Between Transmissions tcsh 1.0 - µs

CS Falling to CCLK Edge tcss 20 - ns

CCLK Low Time tscl 82 - ns

CCLK High Time tsch 82 - ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 20)tdh 15 - ns

Rise Time of CCLK and CDIN (Note 21)tr2 -100ns

Fall Time of CCLK and CDIN (Note 21)tf2 -100ns

tr2 tf2

dsu

sch

tscl

CCLK

CDIN

tcss t

csh

tspi

tsrs

RST

Figure 9. SPI Control Port Timing

DS686A1 21

CS4270

4. TYPICAL CONNECTION DIAGRAM

Figure 10. CS4270 Typical Connection Diagram

)LJ(I2S/CS /AD0

SDA / CDIN (M1)

SCL / CCLK (M0)

AINA

AINB

RST

Power Down

and Mode

Settings

(Control Port)

AOUTA

MUTEA

AOUTB

MUTEB

Analog Conditioning

Mute

LRCK

SCLK

MCLK Timing Logic

Clock

SDIN)S(M/SDOUT Audio Data

Processor

DGND

FILT+

AGND

+3.3 V to 5 V

CS4270

GND or VD

47 kΩ

5.1 Ω

Analo g In pu t

Network

47 µF 0.1 µF

1 µF 0.1 µF

1 µF0.1 µF

If us i ng s eparate supplies for

VA and VD, 5.1 Ω resistor not

needed. See "Grounding and

Power Supply Decoupling."

VLC

+1.8 V to 5 V

3. Use pull-up resistors in Software

Mode. In Hardware Mode, use

pull-up or pull-down. See "Mode

Select ion & De-Emphasis."

2 kΩ

(see Figures 12 & 13)

(see Figures 14 & 15 )

Use a 47 kΩ pull-down to select

Master Mode or 47 kΩ pull-up to

VD to select Slave Mode. See

"Master/Slave Mode Selection."

AD1 (MDIV2)

AD2 (MDIV1)

22 DS686A1

CS4270

5. APPLICATIONS

5.1 Stand-Alone Mode

5.1.1 Recommended Power-Up Sequence

Reliable power- up can be accomplished by keeping th e device in reset until the power supplies, clocks

and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital

supplies drop below the minimum specified operating voltages to prevent power glitch related issues.

5.1.2 Master/Slave Mode

The CS4270 supports operation in either Master Mode or Slave Mode.

In Master Mode, LRCK and SCLK are outputs and are synchronously generated on- chip. LRCK is equal

to Fs and SCLK is equal to 64x Fs.

In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.

It is recommended that SCLK be 48x or 64x Fs to maximize system performance.

In Stand-Alone Mode, the CS4270 will enter Slave Mode when SDOUT (M/S) is pulled low through a 47

kΩ resistor. Master Mode may be accessed by placing a 47 kΩ pull-up to VD on the SDOUT (M/S) pin.

Configuration of clock ratios in each of these modes is outlined in Table 2.

5.1.3 System Clocking

The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three

speed modes as shown in Table 1

Mode Sampling Frequency

Single-Speed 4-54 kHz

Double-Speed 50-108 kHz

Quad-Speed 100-216 kHz

Table 1. Speed Modes

DS686A1 23

CS4270

5.1.4 Clock Ratio Selection

Depending on whether the CS4270 is in Master or Slave Mode, different MCKL/LRCK and SCLK/LRCK

ratios may be used. These ratios are shown in the Table 2.

5.1.5 Interpolation Filter

In Stand-Alone Mode, the fast ro ll-off interpol ation filter is used. Filter specificatio ns can be found in Sec-

tion 3. Plots of the data are contained in Section 11. “Appendix” on page 42.

5.1.6 High-Pass Filter

The opera tional amplifiers in the input circ uitry driving the CS4270 may generate a small DC offset into

the ADC. The CS4270 includes a hig h-pass filter after the decimator to remove any DC offset which could

result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel

system. In Stand-Alone Mode, the high-pass filter continuously subtracts a measu re of the DC offset from

the output of the decimation filter This function cannot be disabled in Stand-Alone Mode.

Master Mode MCLK/LRCK SCLK/LRCK LRCK MDIV2 MDIV1

Single-Speed

256 64 Fs 0 0

384 64 Fs 0 1

512 64 Fs 1 0

1024 64 Fs 1 1

Double-Speed

128 64 Fs 0 0

192 64 Fs 0 1

256 64 Fs 1 0

512 64 Fs 1 1

Quad-Speed

64 64 Fs 0 0

96 64 Fs 0 1

128 64 Fs 1 0

256 64 Fs 1 1

Slave Mode MCLK/LRCK SCLK/LRCK LRCK MDIV2 MDIV1

Single-Speed

256 32, 48, 64, 128 Fs 0 0

384 32, 48, 64, 96 Fs 0 1

512 32, 48, 64, 128 Fs 1 0

1024 32, 48, 64, 96 Fs 1 1

Double-Speed

128 32, 48, 64 Fs 0 0

192 32, 48, 64 Fs 0 1

256 32, 48, 64 Fs 1 0

512 32, 48, 64 Fs 1 1

Quad-Speed

64 32, 48, 64 Fs 0 0

96 32, 48, 64 Fs 0 1

128 32, 48, 64 Fs 1 0

256 32, 48, 64 Fs 1 1

Table 2. Clock Rati os - Stand-Alon e Mod e

24 DS686A1

CS4270

5.1.7 Mode Selection & De-Emphasis

The sample rate, Fs, can be adjusted from 4 kHz to 216 kHz and De-emphasis, optimized for 44.1 kHz,

is available in Single-Speed Mode. In Stand-Alone Master Mode, the CS4270 must be set to the proper

mode via the mode pins, M1 and M0. In Slave Mode, the CS4270 auto-detects Speed Mode and the M0

pin becomes De-emph asis select. Stand-alone defini tions of the mode pins are shown in Table 3.

5.1.8 Serial Audio Interface Format Selection

Either I²S or Left-Justified serial audio data format may be selected in Stand-Alone Mode. The selection

will affect both the input and output format. Placing a 10 kΩ pull-up to VD on the I²S/LJ pin will select the

I²S format, while placing a 10 kΩ pull-down to DGND on the I²S/LJ pin will select the left justified format.

5.2 Control Port Mode

5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode

1. Pull RST low until the power supply, MCLK, and LRCK are stable.

2. Release RST. The control port will be accessible.

3. Initiate a SPI or I²C transaction as described in Section 6.1 or Section 6.2, respectively.

5.2.2 Master / Slave Mode Selection

The CS4270 suppor ts operation in either Master Mode or Slave Mode.

In Master Mode, LRCK and SCLK are outputs and are synchronously generated on- chip. LRCK is equal

to Fs and SCLK is equal to 64x Fs.

In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.

It is recommended that SCLK be 48x or 64x Fs to maximize system performance.

Configuration of clock ratios in each of these modes will be outlined in the Table 10 and Table 9.

In Control Port Mode the CS4270 will default to Slave Mode. The user may change this default setting by

changing the status of the M/S bits in the Functional Control Register (03h).

Mode 1 Mode 0 Mode Sample Rate (Fs) De-Emphasis

0 0 Single-Speed Mode 4 kHz - 54 kHz Off

0 1 Single-Speed Mode 4 kHz - 54 kHz 44.1 kHz

1 0 Double-Speed Mode 50 kHz - 108 kHz Of f

1 1 Quad-Speed Mode 100 kHz - 216 kHz Off

Table 3. CS4270 Stand-Alone Mode Control

DS686A1 25

CS4270

5.2.3 System Clocking

The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three

speed modes as sh own in Table 4.

5.2.4 Clock Ratio Selection

In Control Port Master Mode, the user must configure the mode bits (M0, M1, M2) to set the speed mode

and select the appropriate clock ratios. Depending on whether the CS4270 is in Master or Slave Mode,

different MCLK/LRCK and SCLK/L RCK ratios may be used. These ratios as well as the Control Port Reg-

ister Bits are shown in Table 5, Table 9 and Section 8.3 on page 35.

Mode Sampling Frequency

Single-Speed 4-54 kHz

Double-Speed 50-108 kHz

Quad-Speed 100-216 kHz

Table 4. Speed Modes

Master Mode

MCLK/LRCK SCLK/LRCK LRCK MCLK

Freq<2> MCLK

Freq<1> MCLK

Freq<0>

Single-Speed

256 64 Fs 0 0 0

384 64 Fs 0 0 1

512 64 Fs 0 1 0

768 64 Fs 0 1 1

1024 64 Fs 1 0 0

Double-Speed

128 64 Fs 0 0 0

192 64 Fs 0 0 1

256 64 Fs 0 1 0

384 64 Fs 0 1 1

512 64 Fs 1 0 0

Quad-Speed

64 64 Fs 0 0 0

96 64 Fs 0 0 1

128 64 Fs 0 1 0

192 64 Fs 0 1 1

256 64 Fs 1 0 0

Slave Mode

MCLK/LRCK SCLK/LRCK LRCK MCLK

Freq<2> MCLK

Freq<1> MCLK

Freq<0>

Single-Speed

256 32, 64, 128 Fs 0 0 0

384 32, 48, 64, 96, 128 Fs 0 0 1

512 32, 64, 128 Fs 0 1 0

768 32, 48, 64, 96, 128 Fs 0 1 1

1024 32, 64, 128 Fs 1 0 0

Table 5. Clock Ratios - Control Port Mode

26 DS686A1

CS4270

5.2.5 Internal Digital Loopback

In Control Port Mode, the CS4270 supports an internal digital loopback mode in which the output of the

ADC is routed to the input of the DAC. This mode may be activated by setting the Digital Loopback bit in

the ADC & DAC Ctrl register (04h).

When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270.

Any changes made to the DAC_DIF(4:3) bits while the Digital Loopbac k bit is set will have no impact on

operation until the Dig ital Loopback bit is released, at which time the Digital Interface Format of the DAC

will operate according to the format selected in the DAC _DIF(4:3) bits. While the Digital Loopback bit is

set, data will be present on the SDOUT pin in the format selected in the ADC_DIF(0) bit in register 04h.

5.2.6 Auto-Mute

The Auto-Mute function is contro lled by the status of the Au to Mute bi t in the Mute r egister. When set, the

DAC output will mute following the reception of 8192 consecutive audi o sample s of static 0 or -1 . A single

sample of non-static data will release the mute. Detection and muting are done independently for each

channel. The common mode on the output will be retained and the Mute Control pin for that channel will

become active during the mute period. The m uting function is affected, similar to volume control changes,

by the Soft and ZeroCross bits in the Transition and Control register. The Auto Mute bit is set by default.

5.2.7 High-Pass Filter and DC Offset Calibration

The input circuitry driving the CS4270 may generate a small DC offset into the A/D converter. The CS4270

includes a high-pass filter after the decimator to remove any DC offset which could result in rec ording a

DC level, possibly yielding "clicks" when switching between devices in a multichannel system.

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. The high-pass filter can be enabled if the hpf_freeze bit is set during normal operation, the current

value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be sub-

tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration

by:

1. Running the CS4270 with the high-pass filter enabled until the filter settles. See the Digital Filter

Characteristics for filter settling time.

2. Disabling the high-pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the

calibration point an d th e CS4 27 0.

Double-Speed

128 32, 48, 64 Fs 0 0 0

192 32, 48, 64 Fs 0 0 1

256 32, 48, 64 Fs 0 1 0

384 32, 48, 64 Fs 0 1 1

512 32, 64 Fs 1 0 0

Quad-Speed

64 32 Fs 0 0 0

96 48, 64 Fs 0 0 1

128 32, 64 Fs 0 1 0

192 48, 64 Fs 0 1 1

256 32, 64 Fs 1 0 0

Master Mode

Table 5. Clock Ratios - Control Port Mode (Continued)

DS686A1 27

CS4270

5.2.8 De-Emphasis

One de-emphasis mode is available via the Control Port and is optimized for 44.1 kHz sampling rate.

5.2.9 Oversampling Modes

The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selec-

tion is determined by the FM_&_M/S_Mode[1:0] bits in the Functional Mode register (03h). Single-Speed

mode supports input sample rates up to 54 kHz and uses a 128x oversampling ratio. Double-Speed mode

supports input sample rates up to 108 kHz and uses an oversampling ratio of 64x. Quad-Speed mode

supports input sample rate s up to 216 kHz and uses an oversampling ratio of 32x. See Table 10 for Con-

trol Port Mode settings.

5.3 De-Emphasis Filter

The CS4270 includes on-chip digital de-emphasis. Figure 11 shows the de - em p ha sis cu rve for Fs equal

to 44.1 kHz. The frequency response of the de-emphasis curv e will scale proportionally with changes in

sample rate, Fs. Plea se see Section 5.1.7 for the desired de-e mphasis control for Stand-Alo ne mode and

Section 5.2.8 for control port mode.

The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µs pre-emphasis

equalization as a means of noise reduction.

De-emphasis is only available in Single-Speed Mode.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kH z 10.61 kHz

Figure 11. De-Emphasis Curve

28 DS686A1

CS4270

5.4 Analog Connections

5.4.1 Input Connections

The analog modulator samples the input at 6.144 MHz.The digital filter will reject signals within the stopband of the

filter. However, there is no rejection for input signals which are multiples of the input sampling frequency

(n ×6.144 MHz), where n=0,1,2,... Refer to Figure 12 which shows the re commended to pology of the analog input

network. The capacitor values chosen not only provide the appropriate filtering of noise at the modulator sampling

frequency, but also act as a charge source for the internal sampling circuits. The use of capacitors which have a

large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal lin-

earity.

Three parameters determine the values of resistors R1 and R2 as shown in Figure 12: source impedance,

attenuation, and in put impedance. Sour ce impedance is defined as the impedance as seen from the ADC

looking back into the signal netwo rk. Analog perfor mance is optimized for small source impedance and a

source impedance above 2.5 kΩ results in degraded THD+N.

The required atten uation factor depends o n the magnit ude of th e input signa l. The full-scale in put voltage

scales with VA; for VA = 5 V, the CS5344 full-scale input magnitude is 1 Vrms. R1 and R2 should be set

such that an input signal greater than the full-scale input should be attenuated to the appropriate magni-

tude. Typical line-level voltage in audio applications is 2 Vrms, in which case R1 and R2 must combine to

form an attenuation factor of 2, thus giving the CS5344 a 1 Vrms input.

Input impedance is the impedance from the signal source to the ADC analog input pins. The target input

impedance depends on the overall system specifications, but typical audio systems requ ire an input im-

pedance of 10 kΩ. Table 6 shows the input parameters and the associated design equations. Figure 13

illustrates an example configuration for a source impedance of 46 Ω, an attenuation factor of 1, and input

impedance of 9.8 kΩ.

Source Impedance

Attenuation Factor

Input Impedance

Table 6. Analog Input Design Parameters

Figure 12. CS4270 Recommended Analog Input Network

CS4270

AINx

2200 pF

10 µFR1

Analog

Input

R1R2×()

R1R2+

-------------------------

R1R2×

--------------------

R1R2+()

DS686A1 29

CS4270

5.4.2 Output Connections

The analog output filter present in the CS4270 is a switched-capacitor filter fo llowed by a continuous tim e

low pass filter. Its response, combined with that of the digital interpolator, is give n in Figures Figures 19 -

42. The recommended extern al analog circuitry is shown in Figure 14.

5.5 Mute Control

The Mute Control pins become active during power-up initialization, reset, muting, when the MCLK to

LRCK ratio is inc orrect, and du ring power-down . The MUTE pins are intended to be used as contro l for

an external mute circuit in order to add off-chip mute capability.

The CS4270 also features Auto-Mute, which is enabled by default. The Auto-Mute function causes the

MUTE pin corresponding to an individual channel to activate following the re ception of 8192 consecutive

static-level audio samples on the respective channel. A single transition of data on the channel will cause

the corresponding MUTE pin to deactivate.

Use of th e Mute Control fu nction is not mand atory but recommended for designs requiring the absolute

minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system

Figure 13. CS5344 Example Analog Input Network

CS4270

AINx

2200 pF9.76 kΩ

10 µF47 Ω

Analog

Input

Figure 14. CS4270 Recommended Analo g Ou tput Filter

Analog Output

R+ 470

C= 4πFs(R470)

3.3µF

10kΩC

470Ω

Rext

ext

ext For best 20 kHz response

AOUTx

CS4270

30 DS686A1

CS4270

designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute

circuit. The MUTE pins are active-low. Se e Figure 15 for a suggested active-low mute circuit.

5.6 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To

ensure synchronous samp ling, the MCLK and LRCK must be the same for all of the CS4270’s in the sys-

tem. If only one MCLK source is needed, one solutio n is to place o ne CS4270 in Master Mode , and slave

all of the other CS4270’s to the one master. If multiple MCLK sources are needed, a possible solution

would be to supply all clocks from the same external source and time the CS4270 reset with the inactive

edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.

5.7 Grounding and Power Supply Decoupling

As with any high resolution con verter, the CS4270 requires careful attention to power supply and ground-

ing arrangements if its poten tial performance is to be realized. Figure 10 sho ws the recomme nded power

arrangements, with VA and VD connected to clean supplies. VD, which powers the digital filter, may be

run from the system digita l supp ly ( VD) or may be powered from the ana log sup ply (VA) via a resistor . In

this case, no additional devices should be powered from VD. Power supply decoupling capacitors should

be as near to the CS4270 as possible, with the low value ceramic capacitor being the nearest. All signals,

especially cloc ks, shou ld be k ept awa y from the VR EF and VCOM pins in order to avoid unwanted cou-

pling into the modulators. The VREF and VCOM decoupling capacitors, particularly the 0.1 µF, must be

positioned to minimize the elec trical path from V REF and AGND. The CDB4270 evaluatio n board dem-

onstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the

CS4270 digital outputs only to CMOS inputs.

LPF

+VEE

-VEE

560 ΩAudio

Out

2 kΩ

10 kΩ

-VEE

+VA

MMUN2111LT1

AOUTx

MUTEx

CS4270

Couple

47 kΩ

Figure 15. Suggested Active-Low Mute Circuit

DS686A1 31

CS4270

6. CONTROL PORT INTERFACE

The Control Port is used to load all the internal settings of the CS4270. The operation of the Control Por t may be

completely asynchronous to the au dio sample ra te . Howeve r, to avoid potential interference problems, the Contr ol

Port pins should remain static if no operation is required.

The Control Port has 2 modes: SPI and I²C, with the CS4270 operating as a slave to control messages in both

modes. If I²C operation is desired, AD0/CS should be tied to VLC or DGND. If the CS4270 ever detects a high to

low transition on AD0/CS after power-up, SPI mode will be selected.

Upon release of the RST pin, the CS4270 will wait approximately 10 ms before it begins its start-up sequence. The

part defaults to Stand-Alone Mode, in which all operational modes are controlled as described in Section 5.1 on

page 22. If the user initiates communi cation to the part through the SPI or I²C interface, the part en ters Control-Port

Mode and all operational modes ar e controlled by the Control Port registers. If system requirements do not allow

writing to the control port immediately following the release of RST, the SDIN line should be held at logic “0” until

the proper serial mode can be selected.

6.1 SPI™ Mode

In SPI mode, CS is the CS4270 chip select signal, CCLK is the control port bit clock, CDIN is the input data

line from the microcontroller and the chip address is 1001111. All control signals are inputs and data is

clocked in on the rising edge of CCLK.

Figure 16 shows the operation of the Control Port in SPI mode. To write to a register, bring CS low. The first

7 bits on CDIN form the chip address, and must be 10011 11. Th e eig hth bit is a rea d/write ind ica to r (R/W ),

which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the

address of the register that is to be updated. The next 8 bits are the data which will be placed into the register

designated by the MAP. See Table 9 on page 3 5.

The CS4270 has MAP auto increment capability, ena bled by the INCR bit in the MAP. If INCR is 0, then the

MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte

is written, allowing block writes to successive registers.

MAP

MSB LSB

DATA

byte 1 byte n

R/W

MAP = Memory Address Pointer

ADDRESS

CHIP

CDIN

CCLK

1001111

Figure 16. Control Port Timing, SPI mode

32 DS686A1

CS4270

6.2 I²C Mode

In I²C mode, SDA is a bi-d irectional data line. Data is clocked into and out of the par t by the clock, SCL, with

the clock to data relationship as shown in Figure 17. There is no CS pin. Pins AD0, AD1, and AD2 form the

partial chip address and should be tied to VLC or DGND as required. The upper 4 bits of the 7-bit address

field must be 10 01 . T o co m m un ica te with the CS4270, the three lower bits of the chip address field should

match the setting on th e AD0, AD1, and AD2 pins. The eighth bit of th e address byte is the R/W bit (high for

a read, low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be

read or written. If the operation is a write, the MAP is then followed by the data to be written. If the operation

is a read, then the contents of the register pointed to by the MAP will be output after the chip address.

The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the

MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte

is written, allowing block reads or writes of successive registers.

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

INCR - Auto MAP Increment Enable

Default = ‘0’.

0 - Disabled

1 - Enabled

MAP(3:0) - Memory Address Pointer

Default = ‘0000’.

Table 7. Memory Address Pointer

SDA

SCL

1001 ADDR

AD2 R/W

Start

ACK DATA

1-8 ACK DATA

1-8 ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Note 1

AD0

Figure 17. Control Port Timing, I²C Mode

DS686A1 33

CS4270

7. REGISTER QUICK REFERENCE

This table shows the register names and their associat ed default values.

Addr Function 7 6 5 4 3 2 1 0

01h ID id<3> id<2> id<1> id<0> rev<3> rev<2> rev<1> rev<0>

110 0 0 0 0 1

02h Power

Control Freeze Reserved PDN_ADC Reserved Reserved Reserved PDN_DAC PDN

000 0 0 0 0 0

03h Funct Mode Reserved Reserved FM_&_M/S

_Mode1 FM_&_M/S_

Mode0 MCLK

freq<2> MCLK

freq<1> MCLK

freq<0> PopGuard

Disable

001 1 0 0 0 0

04h Serial Format ADC HPF

Freeze A ADC HPF

Freeze B Digital

Loopback DAC_DIF1 DAC_DIF0 Reserved Reserved ADC_DIF0

000 0 0 0 0 0

05h Transition

Control DAC

Single Vol soft_dac zc_dac Invert ADC

ch B Invert ADC

ch A Invert DAC

ch B Invert DAC

ch A De-Emph

011 0 0 0 0 0

06h Mute Reserved Reserved Auto Mute Mute ADC

SP ch B Mute ADC

SP ch A Mute

Polarity Mute DAC

ch B Mute DAC

ch A

001 0 0 0 0 0

07h Vol Ctrl

AOUTA dacA

vol<7> dacA

vol<6> dacA

vol<5> dacA

vol<4> dacA

vol<3> dacA

vol<2> dacA

vol<1> dacA

vol<0>

000 0 0 0 0 0

08h Vol Ctrl

AOUTB dacB

vol<7> dacB

vol<6> dacB

vol<5> dacB

vol<4> dacB

vol<3> dacB

vol<2> dacB

vol<1> dacB

vol<0>

000 0 0 0 0 0

34 DS686A1

CS4270

8. REGISTER DESCRIPTION

** All registers are read/write in I²C mode and SPI mode, unless otherwise noted**

8.1 Chip ID - Address 01h

Function:

This register is Read-Only. Bits 7 thr ough 4 are the part num ber ID which is 1100b ( 01h) and the re maining

bits (b3:b0) are fo r the chip revision.

8.2 Power Control - Address 02h

8.2.1 Freeze (Bit 7)

Function:

This function allows modifications to be mad e to certain control port bi ts without the changes taking effect

until the Freeze bit i s disabled. To make multiple ch anges to these bits take effect simu ltaneously, set the

Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed

below:

– Register 05h (Bits 7:0)

– Register 06h (Bits 7:0)

– Register 07h (Bits 7:0)

– Register 08h (Bits 7:0)

8.2.2 PDN_ADC (Bit 5)

Function:

The ADC portion of the device will enter a low-power state whenever this bit is set.

8.2.3 PDN_DAC (Bit 1)

Function:

The DAC portion of the device will enter a low-power state whenever this bit is set.

8.2.4 Power Down (Bit 0)

Function:

The device will enter a low-power state whenever this bit is set. The contents of the control registers are

retained when the device is in power-down.

76543210

id<3> id<2> id<1> id<0> rev<3> rev<2> rev<1> rev<0>

76543210

Freeze Reserved PDN_ADC Reserved Reserved Reserved PDN_DAC PDN

DS686A1 35

CS4270

8.3 Mode Control - Address 03h

8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4)

Function:

In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Control

Port Slave Mode, the CS4270 auto-detects speed mode.

8.3.2 Ratio Select (Bits 3:1)

Function:

These bits are used to select the clocking ratios.

8.3.3 PopGuard Disable (Bit 0)

Function:

Disables PopGuard when set. PopGuard is enabled by default.

8.4 ADC and DAC Control - Address 04h

8.4.1 ADC HPF Freeze A (Bit 7)

Function:

When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current D C

offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 “High-

Pass Filter and DC Offset Calibration” on page 26.

76543210

Reserved Reserved FM_&_M/S_

Mode1 FM_&_M/S_

Mode0 MCLK freq<2> MCLK freq<1> MCLK freq<0> PopGuard

Disable

FM_&_M/S_

Mode1 FM_&_M/S_

Mode0 Mode

Single-Speed Mode: 4 to 54 kHz sampl e rates

Double-Speed Mode: 50 to 108 kHz sample rates

Quad-Speed Mode: 100 to 216 kHz sample rates

Slave Mode (default)

Table 8. Functional Mode Selection

MCLK freq<2> MCLK freq<1> MCLK freq<0> Mode

00 0

Divide by 1 (default)

00 1

Divide by 1.5

01 0

Divide by 2

01 1

Divide by 3

10 0

Divide by 4

Table 9. MCLK Divider Configuration

76543210

ADC HPF

Freeze A ADC HPF

Freeze B Digital

Loopback DAC_DIF1 DAC_DIF0 Reserved Reserved ADC_DIF0

36 DS686A1
CS4270
8.4.2 ADC HPF Freeze B (Bit 6)
Function:
When this bit is set, the internal high-pass filter for the  selected channel will be  disabled.The current DC
offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 “High-
Pass Filter and DC Offset Calibration” on page 26.
8.4.3 Digital Loopback (Bit 5)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please  refer to
Section 5.2.5 “Internal Digital Loopback” on page 26.
8.4.4 DAC Digital Interface Format (Bits 4:3)
Function:
The DAC Digita l Interface Format and the options are  detailed in Table 10 and Figures 5 through 7.
8.4.5 ADC Digital Interface Format (Bit 0)
Function:
The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Digital
Interface Format. The options are detailed in  Table 11 and may be seen in Figures 5 and 6.
DAC_DIF1 DAC_DIF0 Description Format Figure
0 0 Left Justified, up to 24-bit data (default) 0 5
0 1 I²S, up to 24-bit data 1 6
1 0 Right Justified, 16-bit Data 2 7
1 1 Right Justified, 24-bit Data 3 7
Table 10. DAC Digital Interface Formats
ADC_DIF Description Format Figure
0 Left Justified, up to 24-bit data (default) 0 5
1 I²S, up to 24- bit data 1 6
Table 11. ADC Digit al Interface Formats

DS686A1 37

CS4270

8.5 Transition Control - Address 05h

8.5.1 DAC Single Volume (Bit 7)

Function:

The AOUTA and AOUTB volume le vels are independently co ntrolled by the A and the B Channel Volume

Control Bytes when this function is disabled . The volume on both AOUTA an d AOUTB are determined by

the A Channel Volume Control Byte (07h) and the B Channel Byte (08h) is ignored when this function is

enabled. Volume and muting functions are affected by the Soft Ramp and ZeroCross functions below.

8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5)

Function:

Soft Ramp Enable

Soft Ramp allows level changes, bo th muting and attenuation, to be implemented by increme ntally ramp-

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

See Table 12 on page 37.

Zero Cross Enable

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to m inimize audible artifacts. The requested level cha nge will occur after a time-

out period between 512 and 1024 sample perio ds (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal

does not encounter a zero crossing. The zero cross function is independently monitored and implemented

for each channel. See Table 9 on page 35.

Soft Ramp and Zero Cross Enable

Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-

ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will

occur after a time-out perio d between 512 and 1024 sample periods ( 10.7 ms to 21.3 ms at 48 kHz sam-

ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-

itored and implemented for each channel. See Table 9 on page 35.

8.5.3 Invert Signal Polarity (Bits 4:1)

Function:

When set, this bit activates an inversion of the signal polarity for the appropriate channel. This is useful if

a board layout error has occurred or in other situations where a 180 degree phase shift is desirable.

76543210

DAC Single

Volume soft_dac zc_dac invert

ADC ch B invert

ADC ch A invert

DAC ch B invert

DAC ch A De-emph

Soft ZeroCross Mode

0 0 Changes to affect immediately

0 1 Zero Cross en abled

1 0 Soft Ramp enabled

1 1 Soft Ramp and Zero Cross enabled

(default)

Table 12. Soft Cross or Zero Cross Mode Sele ction

38 DS686A1

CS4270

8.5.4 De-Emphasis Control (Bit 0)

Function:

Implementation of the stan dar d 50 /1 5 µs digital de-emphasis filter on the DAC output requires reconfigu-

ration of the digital filter to maintain the proper filter response for 44.1 kHz sample rate. Figure 18 shows

the filter response. NOTE: De-emphasis is ava ilable only in Single-Speed Mode.

8.6 Mute Control - Address 06h

8.6.1 Auto-Mute (Bit 5)

Function:

When set, enables the Auto-Mute function. Section 5.2.6 “Auto-Mute” on page 26.

8.6.2 ADC Channel A & B Mute (Bits 4:3)

Function:

When this bit is set, the output of the ADC for the selected channel will be muted.

8.6.3 Mute Polarity (Bit 2)

Function:

The MUTEA and MUTEB pins (pins 24 and 21) are active low by default. When this bit is set, these pins

are active high.

8.6.4 DAC Channel A & B Mute (Bits 1:0)

Function:

When this bit is set, the output of the DAC for the selected channel will be muted.

76543210

Auto Mute Mute ADC SP

ch B Mute ADC SP

ch A mute polarity Mute DAC SP

ch B Mute DAC SP

ch B

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 18. De-Emphasis Curve

DS686A1 39

CS4270

8.7 DAC Channel A Volume Control - Address 07h

Function:

See Section 8.8 DAC Channel B Volume Control - Address 08h.

8.8 DAC Channel B Volume Control - Address 08h

Function:

The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB.

The vol<0> bit activates a 0.5 dB at tenuation when set, and no attenuation when cleared. The Vol[7:1]

bits activate attenuation equal to their decimal value (in dB). Example volume settings are decoded as

shown in Table 13. The volume changes are implemented as dictated by the DACSoft and DACZero-

Cross bits in the Transition Control register (see Section 8.5.2).

76543210

dacA

vol<7> dacA

vol<6> dacA

vol<5> dacA

vol<4> dacA

vol<3> dacA

vol<2> dacA

vol<1> dacA

vol<0>

76543210

dacB

vol<7> dacB

vol<6> dacB

vol<5> dacB

vol<4> dacB

vol<3> dacB

vol<2> dacB

vol<1> dacB

vol<0>

Binary Code Volume Setting

00000000 0 dB

00000001 -0.5 dB

00101000 -20 dB

00101001 -20.5 dB

11111110 -127 dB

11111111 -127.5 dB

Table 13. Digital Volume Control

40 DS686A1

CS4270

9. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.

Dynamic Range is a signal-to-noise ratio me asureme nt over the specified bandwidth made with a -60 dBFS signal.

60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the

distortion components are below the noise level and do not affect the measurement. This measurement technique

has been acce pted by the Audio Engineer ing Society, AES17-1991, and the Ele ctronic Industries Association of Ja-

pan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth

(typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS

as suggested in AES17-199 1 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz.

Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels . Measured for e ach channel at the converter's output

with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temper at ur e. Units in ppm/°C.

Offset Error

The deviation of th e mid -s c a le tra n sitio n (1 11 .. .1 11 to 000. ..0 00 ) fr om the idea l. Unit s in mV.

DS686A1 41

CS4270

10.PACKAGE DIMENSIONS

Notes:

1. “D” and “E1” are referen ce datums and do not include d mold flash or protrusions, but do include mold mis-

match and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” do es not include dambar protr usion/intrusion. Allowable dambar protrusion shall be 0.13 mm

total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimen-

sion “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the fla t section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A----0.47----1.20

A1 0.002 0.004 0.006 0.05 0.10 0.15

A2 0.03150 0.035 0.04 0.80 0.90 1.00

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.378 BSC 0.382 BSC 0.386 BSC 9.60 BSC 9.70 BSC 9.80 BSC 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.029 0.50 0.60 0.75

µ0° 4° 8° 0° 4° 8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

42 DS686A1

CS4270

11.APPENDIX

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 19. DAC Single-Speed (fast) Stopband Rejection Figure 20. DAC Single-Speed (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 21. DAC Single-Speed (fast) Transition Band (detail) Figure 22. DAC Single-Speed (fast) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 23. DAC Single-Speed (slow) Stopband Rejection Figure 24. DAC Single-Speed (slow) Transition Band

DS686A1 43

CS4270

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

Figure 25. DAC Single-Speed (slow) Transition Band (detail) Figure 26. DAC Single-Speed (slow) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 27. DAC Double-Speed (fast) Stopband Rejection Figure 28. DAC Double-Speed (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 29. DAC Double-Speed (fast) Transition Band (detail) Figure 30. DAC Double-Speed (fast) Passband Ripple

44 DS686A1

CS4270

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 31. DAC Double-Sp eed (slow) Stopband Rejection Figure 32. DAC Double-Speed (slow) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.3

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 33. DAC Double-Speed (slow) Transition Band (detail) Figure 34. DAC Double-Speed (slow) Passband Ripple

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 35. DAC Quad-Speed ( fast) Stopband Rejection Figure 36. DAC Quad-Speed (fast) Transition Band

DS686A1 45

CS4270

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.2

0.2

0.15

0.1

0.05

0.1

0.15

0.2

Frequency(normalized to Fs)

Amplitude (dB)

Figure 37. DAC Quad-Speed (fast) Transition Band (detail) Figure 38. DAC Quad-Speed (fast) Passband Ripple

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 39. DAC Quad-Speed (slow) Stopband Rejection Figure 40. DAC Quad-Speed (slow) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.02 0.04 0.06 0.08 0.1 0.1

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 41. DAC Quad-Speed (slow) Transition Band (detail) Figure 42. DAC Quad-Speed (slow) Passband Ripple

46 DS686A1

CS4270

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

Figure 43. ADC Single-Speed Mode Stopband Rejection Figure 44. ADC Single-Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 45. ADC Single-Speed Mode Transition Band (Detail) Figure 46. ADC Single-Speed Mode Passband Ripple

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70

Frequency (normalized to Fs)

Amplitude (dB)

Figure 47. ADC Double-Speed Mode Stopband Rejection Figure 48. ADC Double-Speed Mode Transition Band

DS686A1 47

CS4270

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.40 0.43 0.45 0.48 0.50 0.53 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normal ized to Fs)

Amplitude (dB)

Figure 49. ADC Double-Sp eed Mode Transition Band (Detail) Figure 50. ADC Double-Speed Mode Passband Ripple

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8

Frequency (normali zed to Fs)

Amplitude (dB)

Figure 51. ADC Quad-Speed Mode Stopband Rejection Figure 52. ADC Quad-Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25

Frequency (normalized to Fs)

Amplitude (dB)

Figure 53. ADC Quad-Speed Mode Transition Band (Detail) Figure 54. ADC Quad-Speed Mode Passband Ripple

48 DS686A1

CS4270

12.REVISION HISTORY

Release Date Changes

A1 May 2005 Initial Advance Release

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus")

believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS

IS" without warranty o f any kind ( express or impli ed). Custo mers are ad vi sed to obt ai n the lat est version of re levant informat i on to ver ify, before placing orders, that

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