Hybrid Systems HS 9410 Series 8 Channel, 12-Bit Data Acquisition System with pP Interface FEATURES = Complete 8 Channel, 12-bit Data Acquisition System with MUX, S/H, REF, Clock and three- state outputs = Full 8- or 16-Bit Microprocessor Bus Interface # Guaranteed Linearity Over Temperature # High Throughput Rate: 25kHz a Hermetic 28-Pin Ceramic or Low Cost Epoxy DIP = Low Power: 600mW DESCRIPTION The HS 9410 Series is a complete 8 channel, micro- creased accuracy, lower drift and reduced output noise processor compatible, 12-Bit data acquisition system over the A/D operating range. Precision low TCR laser with all the interface logic to connect directly to 8- or trimmed resistors are used in the converter for setting 16-Bit microprocessor buses. It is contained in a 28-pin critical performance parameters including gain, offset, DIP and inciudes an 8 channel multiplexer, a sample- input ranges, and accuracy. and-hold amplifier, and a 12-Bit A/D converter along with S ies i i i -seal the control logic needed to perform a complete data ac- The HS 9410 Series is offered in a hermetically-sealed quisition function. System throughput rate is 25 kHz for Pa td eonrocenes Sot Sytene cacarie. full rated accuracy. tary commercial package is offered for applications not The Analog-to-Digital converter section contains the now requiring the wider temperature exposure. standard HS 574 12-Bit ADC. This ADC is implemented * ; , ar The HS 9410 Series operates from +15V* and + 5V with with advanced bipolar and CMOS LSI chips resulting in a total power consumption of 600 mW. To take advan- maximum performance at lowest cost. The SAR, 12-Bit ni ; decoded D/A, control logic, switches and buffers are fab- ao oro 26 PO aK age tne eS wh pent hel po ricated using CMOS processing for lowest power. A . unique comparator, reference and required amplifiers canted See ae oO Che ree are fabricated using linear bipolar processes for maxi- ; Fr while the S and T models are specified over an extended mum speed and reduced offset and drift over temperature. temperature range of 55C to + 125C. Full screening Incorporating a unique precision comparator design, the to MIL-STD-883 Rev. C, Level B and processing in accord- ADC offers several advantages over more conventional ance with Method 5008.1 is available with models speci- circuits. A proprietary decoded 12-Bit D/A provides in- fied as B. *+12V operation possible; consult factory for further information. FUNCTIONAL DIAGRAM ran (STATUS) GAIN OFFSET 9 9 22 21 20 W 2 CHT OW HIGH -O DB (MSB)D83 CH? O75 Bone i -O DB19/DB2 CHS OTE LOW O DB9/DBy BYTE ANALOG = CH 4 OTF 8 CHANNEL SAMPLE & HOLD 12. BIT DBg/DBo (LSB) INPUTS = cH 5 O-> MULTIPLEXER AMPLIFIER DC 35 087 CHE OB 16 MIDDLE 24 CH? OFF BYTE 337 DBs cH8 -O DB4 T MA ef F > MUX MAY os ADDRESS MA2 coene. cLock REF HS 9410 SERIES 4 4 4 tf \ tb hb ta Ag RIE Veg, VEE VLOgic GNO 287SPECIFICATIONS (Typical @ + 25C with Voc = +15V, Vee = 15V, VLogic = +5V. unless otherwise specified.) MOOEL HS 941XJ HS 941XK HS 941XS HS 941XT TRANSFER CHARACTERISTICS Resolution 12-Bits . . Number of Channels 8 Single-Ended . . Throughput Rate 25 kHz . . * ANALOG INPUTS Input Ranges! (Specified as a suffix in the model number. See Ordering Guide.) HS 9410 Oto +10V . . HS 9411 +5V . * . HS 9412 +10V * . . Input Bias Current per Channel lig 25C +1.0nA . . , ~ 55C to + 125C +250nA max * Input Impedance ON Channel 4019 gI1 100pt , . : OFF Channel 1019 Oil 10pF . ' , DIGITAL INPUTS Logic Inputs RIC, Ag Vy min +2.0V * , . Vip max +5.5V * , . Vi_ max +0.8V . , . Vit min ~0.5V . . IL max + 50A max , lq max +50uA max . , . Muitipiexer Inputs Vi_ max +0.8V * * * Vin min +2.4V . +4.0Ve +4.0V2 input Capacitance (All Digital Inputs} 5pF typ * . . Minimum Start Pulse R/C-Negative 150ns * * . SIGNAL DYNAMICS Conversion Time 12-Bit Conversion 30us max . * . 8-Bit Conversion 21s max . * . DIGITAL OUTPUTS Logic Outputs DB,1-DBg, STS Logic 0 +0.4V max, Io_<1 6mA * * * Logic 1 +2.4V min, lop <0.5MA * . * Leakage (High Z State) + 40pA typ (DB, 4-DBg only) * . . Capacitance 5pF . Output Code Configuration Unipolar Positive True Binary * * * Bipolar Positive True Offset Binary * * * POWER SUPPLY VLOGIC +4.5to +5.5 Volts @ 20mA max . * * Voc +13.5to +16.5 Volts @ 25mMA max * , . VEE -13.5to - 16.5 Volts @ 35mA max * , Power Dissipation 800mW typ, 1.1W max * 600mW typ, 1W max 600mW typ, 1W max Rejection VLOGIC 0.002%/% typ, 0.005%/% max . , . Voc 0.002%/% typ, 0.005%/% max . , . VEE 0.002%/% typ, 0.005%/% max . , * ACCURACY Linearity Error (% of F.S.R. max) +0.025 +0.012 +0.025 +0.012 Ottset4 Unipolar (% of F.S.R. max) +0.05 . * . Bipolar {% of F.S.R. max) +0.25 +0.1 +0.25 +0.1 Gain4 (% to F.S.R. max) +0.3 * * . STABILITY Linearity (ppm/C max) +05 +05 +25 +25 Unipolar Offset (opm/C max) +10 +5 +25 +20 Bipolar Offset (ppm/ C max) +25 +20 +25 +20 Gain (Scale Factor)(ppm/C max) +50 +20 +50 +25 TEMPERATURE RANGE Operating 0 to + 70C . ~ 55C to + 126C - 55C to + 125C Storage - 25C to +85C . ~ 65C to + 150C -55C to + 125C PACKAGE CASE A CASE A CASE B CASE B NOTES 1. For J and K models, positive analog input voltage should not exceed Voc -4 volts. Exceeding Voc - 4 volts can cause an OFF channel to be turned ON. Negative input voltages and input voltages for S and T models may go to supply voltages. Input voltages exceeding these values wiil not resuit in permanent damage as long as the absolute maximum ratings are not exceeded. 2. 1K pullupto +5V recommended for MAg-MAg when driven by TTL. 3. Maximum change over rated supply voltage Specifications same as HS 9410J 288 4. Externally adjustable to zero. See Applications InformationPACKAGE OUTLINE ABSOLUTE MAXIMUM RATINGS Dimensions shown in inches and (mm). Voc to Common GND Oto +16.5V VeetoCommonGND ................. Oto ~ 16.5V CASEA 0.705 o.zss Viogict0 CommonGND.................. Oto +7V (97.907) 76-477 MAX DIMENSIONS Control Inputs (A,, R/C) to [= Max ly inch CommonGND............ 0.5V to Viggic + 0.5V Power Dissipation... 0.0.0.0... 0.0. 0.00000000. 1.3W |_, Lead Temperature, Soldering......... 300C, 10Sec PIN 1 DOT Maximum Input Voltage..............0., Voc + 20V Was zag | 5 Minimum Input Voltage. ... 02... ...00000, Vee 20V = Analog Input Maximum Current .............. 25mA 228 : || 2: CONTROL FUNCTIONS : : ] 540 The HS 9410 Series contains control functions : : Ce necessary to provide for microprocessor interface. All : : La control functions are defined in Tables 1, 2, and 3. : il. 540) 15144 Ne Function| Definition Function BOTTOM Ne 010 , 0.020 RIC Read/Convert | 1. initiates conversion. VIEW (0.254) * (0.508) 2. Low (0) disconnects data bus. CASE B 3. High (1) initiates read. 0.620 MAX | 9.145 ; i <a. (15.75)2| (3.68) Ay Device Address | 1. Selects conversion mode. peceea| Gee) 12-bits if low (0), 8-bits if high (1) when A/C ; 2. In read mode Aj selects the out- > (0.254) put format. If low (0) then 8 0.600 MSB's (high and middle byte) or ait5.240 YY if high (1) then only low byte |28 t and trailing zeroes. " S| 9.020 ty MA, 0.51 4 i . os af 52 MA, Multiplexer Select Channels 1-8 +} le) PIN1 MMOL . i HOOT (1.32) MA, Address (see MUX Logic Table 3) i C 1.414 MAX Table 1. Defining the Control Functions I | (35.92) 1s 14] ; BOTTOM 6.25 MIN Control Inputs Operation VIEW (3.18) RIC Ao L 0 Initiates 12-bit conversion L 1 Initiates 8-bit conversion 1 0 Enables 8 MSBs (high byte) 1 1 Enables 4 LSBs (low byte) and PIN ASSIGNMENTS 4 trailing zeros PIN FUNCTION PIN FUNCTION 0 Xx Output data (DB) goes to high impedance state. 1 DB,,/DB> 28 DB/DB, 2 DB,,(MSB)/DB, 27 DB,/DBo Table 2. Truth Table Control inputs 3 Ay 26 DB, = NOTES: 4 RIC 25 DBs Mux Address Channel | |; indicates logic HIGH. 5 | GROUND 24 | DB, Inputs Selected | > 4 indicates logic LOW A2 Ay Ao 3. X indicates don't care. 6 Vioaic 23 DB4 0 0 0 1 4 u indicates operation commences 7 Vee 22 STS(STATUS) on high to low transition. 0 0 1 2 / 8 | MUX ADDRESS A, 21_| GAIN a a ich Mia 9 MUX ADDRESS A, 20 OFFSET Bye Byte 0 1 1 4 6 XXXX =f LSB 10 MUX ADDRESS A, 19 Voc } 0 0 5 Low 11 | INPUT CH 1 18 | INPUTCHS5 toe a 6 ene 12 INPUT CH 2 17 INPUT CH 6 1 1 0 7 13 INPUT CH 3 16 INPUT CH 7 1 1 1 8 14 INPUT CH 4 15 INPUT CH 8 Table 3. Truth Table Multiplexer Address 289APPLICATIONS INFORMATION TIMING The timing diagrams are shown in Figures 1 through 6. Figures 1 and 2 show how the multiplexer addressing is related to the convert cycle, while Figures 3 and 4 show the timing sequence to start either a 12- or an 8-bit conversion. Figures 5 and 6 show how to read the multiplexed data from the internal register in the HS 9410. Figures 1 and 2 The multiplexer address can be changed either during or after a conversion, but care must be taken not to change the address within 1 microsecond after the convert command to insure that the sample/hold will not start to acquire the signal of the new channel. After the multiplexer address has been changed, you must allow the sample/hold at least 10 microseconds in sample mode to acquire the new input signal. \ tCON ( { ! STATUS \ i \ / ! ! t t MUX ADDRESS Pf ce RIC imUXxH Muitiplexer address hold time after convert command tus min tacq Minimum time between conversions (S/H acquisition time) 10us min 30ys max 30us max tcon Conversion time for -12 bit resolution J,K-Models S,T-Modets - 8 bit resolution J,K-Models S,T-Models 22us max 22us max Figure 1. Timing Diagram 8/12-Bit Conversion, MUX Address Changes During Conversion STATUS ToS rT tcon ogg el ( 4 MUX y ADDRESS | | R/C LS \ LS t ; ACQ tacgq Minimum time between MUX address change and convert command 10us min con Conversion time - Specifications, see Figure 1 Figure 2. Timing Diagram 8/12-Bit Conversion, MUX Address Changes Between Conversions Figures 3 and 4 Figures 3 and 4 show how to start a convert cycle. The logic level of the Ag line determines whether a 12- or 8-bit conversion will be initiated. lf Ag is low during the start convert command, a 12 bit conversion will be started; if Ag is high, an 8-bit conversion will occur. The Ag line has to be setup when the R/C line goes to logic O and must remain in the desired level for at least 150 ns. The RIC line is used both to start a conversion and to read the output data. If R/C is going low a con- 290 version is initiated. This is indicated by the STATUS line going high. A second start convert command during a conversion will be ignored. The R/C pulse must have a minimum width of 150 ns. For optimum performance the rising edge of the R/C pulse should not occur dur- ing a conversion if the conversion has been in progress for more than 1.5 microseconds, i.e., the negative R/C pulse should be either shorter than 1.5 microseconds or longer than the conversion time. HIGH -Z DATA OUTPUT \y }~_____>! 1 tHL i | tac RIC pulse width, Ag pulse width (Note 1) 150 ns min tos Status delay from R/C 200 ns max tHL Output float delay 150 ns max Figure 3. Timing Diagram to Start a 12-Bit Conversion STATUS DATA OUTPUT Y | tre R/C pulse width, Ag pulse width (Note 1) 150 ns min tos Status delay from R/C 200 ns max tHL Output float delay 150 ns max Figure 4. Timing Diagram to Start an 8-Bit ConversionFigures 5 and 6 | if a conversion is in progress the data output lines are -Sa disabled and in the high-impedance state. Data can be at | / enabled by bringing the R/C line high after a conver- - sion is complete (this is indicated by the STATUS line . i going low; Fig. 6). If R/C has been returned high during STATUS \ a conversion the data outputs will be enabled auto- | ; matically after STATUS goes low (Fig. 5). The Ag line is used to address either the 8 upper data bits or the 4 Ao k X lower data bits followed by 4 trailing zeros. If an 8-bit conversion has been performed the lower 4 bits will DATA Henze Ta) P ourrut Ce always be 0. After an 8-bit conversion, it is not | [ necessary to read the lower 4 bits prior to starting a rtrd th! new conversion. Note that Ag only controls the address of the two data bytes while the high impedance state of tsTs Status going low prior to R/C going high Ons min the output buffers is controlled by the R/C and STATUS tga Ag Set-up time prior to R/C going high (Note 2) 100 ns min line. The output buffers will not return to the high ta1 Access time, 1st data byte (from A/C) 125 ns max : . t A time, 2nd data b f A 225 impedance state when Ag is changed to address the R2 Access time, 2nd data byte (from Ao) nemen second data byte. Figure 6. Timing Diagram Read Cycle, R/C Going High After Conversion 1 tSRC | | RE } | po USING THE Ao LINE STATUS \ The state of A, at the start of a conversion places the | tSA DAS in either a full 12-bit conversion or in an 8-bit short | | cycle mode. During a READ at the end of a conversion ' \-t : Ao aa Y A, is used to format the data as follows: t boy, DATA HIGH - Z ! { YYYYY' 1. Prior to Conversion (WRITE) OUTPUT | MODE | ! Aj=1 Short cycle 8-bit conversion ira | tra | A.=0 Full 12-bit conversion 2. After Conversion (READ) . . . . Ag=1 Data = Low Byte (LSB) tsrnc R/C set-up time prior to status going low Ons min followed by zeros tsa Ao set-up time prior to status going low (Note 2) 100 ns min A,=0 Data = High Byte (MSBs) tri Access time, 1st data byte (from status) 125 ns max followed by middle byte. tro Access time, 2nd data byte (from Ao) 225 ns max In a uP application A, can be considered a pair of W/R Figure 5. Timing Diagram Read Cycle, locations as follows: R/C Going High During Conversion 1. Prior to Conversion (WRITE) _. MODE WR = 0 in low address (A, = 0) Full 12-bit conversion NOTES: W/R =0 in high address (A, = 1) Short cycle 8-bit conversion 1. For optimum performance the positive edge of the RIT pulse 2. After Conversion (READ) should not occur during a conversion if the conversion has been Wik=1 in high add A a1 LSBs & started for more than 1.5 microseconds. The negative R/C pulse WIR = 1 in high address (A, = 1) S & Zeros should be either shorter than 1.5 microseconds or longer than the WIR = 1 in low address (A, = 0) 8 MSB's only conversion time. 2. If the set-up time for Ag cannot be met, the access time for the first data byte will be increased. In that case the first data byte will become valid 225 ns max after the change of the Ag line. 291MICROPROCESSOR INTERFACE The HS 9410 Series DAS can be interfaced with most popular 8-bit microprocessors. The DAS may be either positioned in a memory location (memory map) or as an VO device. In the case of memory mapping, the DAS acts as a static RAM where READ and WRITE instructions are given to the selected address. When the DAS Is con- nected as an I/O device, the I/O enable can be substituted for the MEMR or MEMW command. Figure 7 shows a typical scheme to implement this interface. STS is not used in this example; the uP must read data 30ys after conversion starts. This delay can be generated with NOP or other instructions inserted between the WRITE and READ functions. The STS line can also be used to cause the processor to WAIT or HALT or can be used as an interrupt line such as IREQ (in the case of 6800 or 6502). Ao SEE TEXT ~# , 4 sTs Ao HS 9410 8 SERIES DATA a OUTPUT pus PODS cH DATA 74LS$244 8 8 | mux ENABLE ADDR RT A A 74LS175 L 73 Do-D2 3 cK 74LS139 | WR 1G 10 At 1A > 1v1 1 1B AD ~______|___ 26 2A J S| 270 2B ST ADDRESS ADDRES DECODE OUT joJ ADDR SEL = CS (CHIP SELECT) VOOR MEN) HS 9410 Function A, A, WR RD ADOR SEL}Read/Write Operation XPO;L#s]1 0 WRITE MUX ADDRESS ofije} 1 0 WRITE | START 12-BIT CONV. fife} i 0 WRITE | START 8-BIT CONV. oO, XxX} 7 40 0 READ } HIGH BYTE (8 MSB's) 1] XX] 1 0 0 READ LOW BYTE (4 LSB's) NOTES: 1.1 indicates logic HIGH. 2. 0 indicates logic LOW. 3. X indicates don't care. 4. indicates operation commences on low to high transition. 5. wy indicates operation commences on high to low transition. Figure 7. Interfacing the HS 9410 Series 292 INPUT EXPANSION The DAS is configured with an 8 channel high level multiplexer input. This was done to optimize package size (28 pin DIP) and cost. In the event the user wishes to increase the number of input channels, a double rank MUX input is recommended (series connected). This typical configuration is shown in Figure 8. HS 9410 SERIES ANALOG INPUTS 8 CHANNEL MUX [ MUX ADDRESS NOTE: EXPANSION SHOWN FOR CHANNEL 8 OF DAS i.e. x[xfxqo [fal \ cee peel \enreem rome! 8 CHANNEL 9410 MUX Figure 8. Multiplexer Expansion EXPANSION ADDRESS ZERO AND GAIN CONNECTIONS The DAS is normally used with external zero and gain calibration potentiometers. However, if maximum ac- curacy is not required, they may be omitted. The zero control has a range of about + 20LSB, and the gain control has a range of about + 13LSB. Proper gain and zero calibration requires great care and the use of extremely sensitive and accurate in- struments. The voltage source used as a signal input must be very stable. It also should be capable of being set to within 1/10LSB at both ends of its range. The DAS's zero and gain adjustments are independent of each other if the zero (or offset) adjustment is made first. - 1,2 MUX 2, \ ADDRESS 6-10 23-28| _PB0-DBI HS 9410 A ANALOG SERIES * ? INPUTS 11-18 RIT 4 +15V STS 22 Ve Ra 20K 2*V J 21. GAIN +5V 6 6M ~15V -15V 7 Mv IN Vo RI +15 19 20K VWJ 20 ~ OFFSET 1.5M GND 5 ~15V % NOTES: 1. OFFSET (VOLTS) = Vo 5 2. GAIN (%) = V 200 100 +Ry 100 + Ro Where Ry and R2 are shown in kohms Figure 9. Gain and Offset Input ConnectionsZERO ADJUSTMENT PROCEDURE 1, For unipolar ranges: a) Set input voltage precisely to + YeLSB. b) Adjust zero control until converter is switching from 000000000000 to 000000000001. For bipolar ranges: POWER SUPPLY CONSIDERATION Power supplies used for the DAS should be selected for low noise operation. In particular they should be free of high frequency noise. Unstable output codes may result with noisy power sources. It is important to remember that 2.44mV is 1LSB for a 10 volt input. a) Set input voltage precisely to /2LSB above F.S. 1b above Decoupling capacitors are recommended on all power b) Adjust zero contro! until converter is switching supply pins located as close to the converter as possi- from 000000000000 to 000000000001 GAIN ADJUSTMENT PROCEDURE 1. Set input voltage precisely to 2LSB less than all bits on value. Note that this is 1%2LSB less than nominal full scale. Adjust gain control until converter is switching from 1441111117110 to 111111111111. Tabie 4 summarizes the zero and gain adjustment pro- cedure, and shows the proper input test voltages used in calibrating the DAS. ble. Suitable decoupling capacitors are 10uF tantalum type in parallel with 0.1pF disc ceramic type. GROUNDING CONSIDERATIONS The common at pin 5 is the ground reference point for the internal reference and is thus the high quality ground for the DAS. In order to achieve all of the high accuracy performance available from the DAS in an environment of high digital noise content, care should be taken when handling analog and digital grounds, as follows. Where analog and digital grounds are run separately on the PCB, these should be connected together at the package (pin 5). However, if the grounds are connected separately in the system for other reasons, then only the analog ground should be Input Adjust input to point connected a re package to i 5. If igre como Voltage Adjust- Input where converter is contains d through the cx ote shat INS Range ment Voltage just on the verge of Noise my be wired e converter, So tnat some switching between caution will be required. the two codes shown.' It is also important in the layout to carefully consider the placement of digital lines. It is recommended that jaital |i i - oo0000000000 digital lines not be run directly under the DAS. For op ZERO 1.22mV ogo000000001 timum system performance, if space permits, a ground 0 to +10V 4111111140 plane is advised under the DAS. This should be con- GAIN 9.9963V " mn nected to a digital ground. Finally, in packaging the rata assembled DAS, the designer should also try to mini- 000000000000 mize any capacitive coupling that might occur at the ZERO | 4,.9988V t he devi 000000000001 op to the device. +8V 111111111110 GAIN 4.9963V 191111111111 zero | 99976v 000000000000 10V 000000000001 + 111111111110 GAIN 9.9927V 491111111111 Codes shown are natural binary for unipolar input ranges and offset binary for bipolar ranges. Table 4. Calibration Data 293ORDERING INFORMATION System Full Scale Model input Accuracy T.C. Temp. MIL Number Range (% FSR) (ppm/C) Range Screening HS 94XXJ +0.025 50.0 0C to + 70C - HS 94XXK +0.012 20.0 0C to + 70C _ HS 94XXS SEE +0.025 50.0 ~5C to + 125C _ HS 94XXT NOTE 1 +0.012 25.0 - 55C to + 125C _ HS 94XXS/B +0.025 50.0 - 55C to +125C 883 Rev. C HS 94XXT/B +0.012 25.0 - 55C to +125C 883 Rev. C NOTES: 1 HS 94XX J MODEL INPUT Specifications subject to change without notice. SUFFIX RANGE 10 Oto +10V 14 +5V 12 +10V Add letter suffix as required above. CAUTION: ESD (Electro-Static Discharge) sensitive device. Permanent damage may occur when unconnected devices are subjected to high energy electro-static fields. Unused devices must be stored in conductive foam or shunts. Protective foam should be discharged to the destination socket before devices are removed. Devices should be handled at static safe workstations only. Unused digital inputs must be grounded or tied to the logic supply voitage. Unless otherwise noted, the voltage at any digital input should never exceed the supply voltage by more than 0.5 volts or go below 0.5 volts. If this condition cannot be maintained, limit input current on digital inputs by using series resistors or contact Hybrid Systems for technical assistance. 294