A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package FEATURES AND BENEFITS * 3.3 V supply operation * QVO temperature coefficient programmed at AllegroTM for improved accuracy * Miniature package options * High-bandwidth, low-noise analog output * High-speed chopping scheme minimizes QVO drift across operating temperature range * Temperature-stable quiescent voltage output and sensitivity * Precise recoverability after temperature cycling * Output voltage clamps provide short-circuit diagnostic capabilities * Undervoltage lockout (UVLO) * Wide ambient temperature range: -40C to 150C * Immune to mechanical stress * Enhanced EMC performance for stringent automotive applications PACKAGES 3-pin ultramini SIP 1.5 mm x 4 mm x 3 mm (suffix UA) 3-pin SOT23-W 2 mm x 3 mm x 1 mm (suffix LH) DESCRIPTION New applications for linear output Hall-effect sensors, such as displacement and angular position, require higher accuracy and smaller package sizes. The Allegro A1318 and A1319 linear Hall-effect sensor ICs have been designed specifically to meet both requirements. These temperature-stable devices are available in both surface-mount and through-hole packages. The accuracy of each device is enhanced via end-of-line optimization. Each device features non-volatile memory to optimize device sensitivity and the quiescent voltage output (QVO: output in the absence of a magnetic field) for a given application or circuit. This A1318 and A1319 optimized performance is sustained across the full operating temperature range by programming the temperature coefficient for both sensitivity and QVO at Allegro end-of-line test. These ratiometric Hall-effect sensor ICs provide a voltage output that is proportional to the applied magnetic field. The quiescent voltage output is adjusted around 50% of the supply voltage. The features of these linear devices make them ideal for use in automotive and industrial applications requiring high accuracy, and operate across an extended temperature range, -40C to 150C. Each BiCMOS monolithic circuit integrates a Hall element, temperature-compensating circuitry to reduce the intrinsic Continued on the next page... Not to scale Functional Block Diagram V+ CBYPASS Tuned Filter Dynamic Offset Cancellation VCC Sensitivity and Sensitivity TC VOUT Offset and Offset TC GND A1318-DS, Rev. 4 MCO-0000357 January 15, 2019 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package DESCRIPTION (continued) sensitivity drift of the Hall element, a small-signal high-gain amplifier, a clamped low-impedance output stage, and a proprietary dynamic offset cancellation technique. The A1318 and A1319 sensor ICs are offered in two package styles. The LH is a SOT-23W style, miniature, low-profile package for surface-mount applications. The UA is a 3-pin, ultramini, single inline package (SIP) for through-hole mounting. Both packages are lead (Pb) free, with 100% matte-tin leadframe plating. SELECTION GUIDE Output Polarity Sensitivity (typ) (mV/G) Packing [1] Package A1318LLHLX-1-T [2] Forward 1.35 10,000 pieces per reel 3-pin SOT-23W surface mount A1318LLHLT-1-T [2] Forward 1.35 3,000 pieces per reel 3-pin SOT-23W surface mount A1318LLHLX-2-T [2] Forward 2.5 10,000 pieces per reel 3-pin SOT-23W surface mount A1318LLHLT-2-T [2] Forward 2.5 3,000 pieces per reel 3-pin SOT-23W surface mount A1318LUATN-2-T Forward 2.5 4,000 pieces per reel 3-pin SIP through hole A1318LUA-2-T Forward 2.5 500 pieces per bag 3-pin SIP through hole A1319LLHLX-5-T [2] Forward 5 10,000 pieces per reel 3-pin SOT-23W surface mount A1319LLHLT-5-T [2] Forward 5 3,000 pieces per reel 3-pin SOT-23W surface mount A1319LUATN-5-T Forward 5 4,000 pieces per reel 3-pin SIP through hole A1319LUA-5-T Forward 5 500 pieces per bag 3-pin SIP through hole Part Number [1] Contact AllegroTM for additional packing options. [2] This part variant is in production but has been determined to be NOT FOR NEW DESIGN. Sale of this part is currently restricted to existing customer programs already using the part. The part should not be purchased for new programs or designed into new applications. Samples are no longer available. Contact Allegro for suggested replacement. Date of Status Change: December 14, 2017. ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Notes Rating Unit Forward Supply Voltage VCC 8 V Reverse Supply Voltage VRCC -0.1 V Forward Output Voltage VOUT 7 V Reverse Output Voltage VROUT -0.1 V Output Source Current IOUT(SOURCE) VOUT to GND 2 mA IOUT(SINK) VCC to VOUT 10 mA Output Sink Current Operating Ambient Temperature TA -40 to 150 C Maximum Junction Temperature TJ(max) 165 C Tstg -65 to 170 C Storage Temperature Range L Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package Pinout Diagrams Terminal List Table 3 Name 1 2 LH Package 1 2 Number Description LH UA VCC 1 1 Input power supply; tie to GND with bypass capacitor VOUT 2 3 Output signal GND 3 2 Ground 3 UA Package THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Symbol Test Conditions Package LH, 1-layer PCB with copper limited to solder pads Package Thermal Resistance RJA Package LH, 2-layer PCB with 0.463 side connected by thermal vias in.2 of copper area each Package UA, 1-layer PCB with copper limited to solder pads Value Units 228 C/W 110 C/W 165 C/W Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package OPERATING CHARACTERISTICS: Valid over TA , CBYPASS = 0.1 F, VCC = 3.3 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Unit [1] 3 3.3 3.63 V ELECTRICAL CHARACTERISTICS Supply Voltage Undervoltage Threshold [2] Supply Current VCC VUVLOHI Tested at TA = 25C and TA = 150C (device powers on) - - 3 V VUVLOLO Tested at TA = 25C and TA = 150C (device powers off) 2.5 - - V - 7.7 10 mA ICC No load on VOUT Time [3][4] tPO TA = 25C, CL(PROBE) = 10 pF - 50 - s VCC Ramp Time [3][4] tVCC TA = 25C 0.005 - 100 ms VCCOFF Power-On VCC Off Level [3][4] TA = 25C 0 - 0.33 V tCLP TA = 25C, CL = 10 nF - 30 - s VZ TA = 25C, ICC = 13 mA 6 7.3 - V Small signal -3 dB - 20 - kHz fC TA = 25C - 400 - kHz VN VCC = 3.3 V, TA = 25C, CBYPASS = open, Sens = 5 mV/G, no load on VOUT - 13 - mV(p-p) Input Referred RMS Noise Density [4] VNRMS VCC = 3.3 V, TA = 25C, CBYPASS = open, Sens = 5 mV/G, no load on VOUT, fmeasured << BWi - 2.3 - mG/Hz DC Output Resistance [4] ROUT - <1 - 4.7 - - k Delay to Clamp [3][4] Supply Zener Clamp Voltage Internal Bandwidth [4] Chopping Frequency [5] BWi OUTPUT CHARACTERISTICS Output Referred Noise [4] Output Load Resistance [4] Output Load Capacitance [4] Output Voltage Clamp [6] Sensitivity [7] RL VOUT to GND CL VOUT to GND - - 10 nF VCLPHIGH TA = 25C, B = +400 G, RL = 10 k (VOUT to GND) 2.842 2.97 3.069 V VCLPLOW TA = 25C, B = -400 G, RL = 10 k (VOUT to VCC) 0.264 0.33 0.462 V A1318LLHLX-1-T 1.289 1.35 1.411 mV/G A1318LLHLX-2-T 2.388 2.5 2.613 mV/G 2.388 2.5 2.613 mV/G 4.85 5 5.15 mV/G Sens A1318LUA-2-T TA = 25C A1319LLHLX-5-T A1319LUA-5-T 4.85 5 5.15 mV/G A1318LLHLX-1-T 1.638 1.65 1.662 V 1.638 1.65 1.662 V 1.638 1.65 1.662 V A1318LLHLX-2-T Quiescent Voltage Output (QVO) VOUT(Q) A1318LUA-2-T TA = 25C A1319LLHLX-5-T 1.635 1.65 1.665 V A1319LUA-5-T 1.635 1.65 1.665 V Continued on the next page... Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package OPERATING CHARACTERISTICS (continued): Valid over TA , CBYPASS = 0.1 F, VCC = 3.3 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Unit [1] 0.08 0.12 0.16 %/C 0.08 0.12 0.16 %/C 0.08 0.12 0.16 %/C 0.08 0.12 0.16 %/C 0.08 0.12 0.16 %/C LinERR - 1.5 - % SymERR - 1.5 - % ELECTRICAL CHARACTERISTICS (continued) A1318LLHLX-1-T A1318LLHLX-2-T Sensitivity Temperature Coefficient TCSens A1318LUA-2-T A1319LLHLX-5-T Programmed at TA = 150C, calculated relative to Sens at 25C A1319LUA-5-T ERROR COMPONENTS Linearity Sensitivity Error Symmetry Sensitivity Error Ratiometry Quiescent Voltage Output Error [8] RatVOUT(Q) Across supply voltage range (relative to VCC = 5 V) - 1.5 - % Ratiometry Sensitivity Error [8] RatSens Across supply voltage range (relative to VCC = 5 V) - 1.5 - % TA = 25C, across supply voltage range (relative to VCC = 5 V) - 1.5 - % A1318LLHLX-1-T -15 - 5 mV A1318LLHLX-2-T -18 - 8 mV Ratiometry Clamp Error [9] RatVOUTCLP DRIFT CHARACTERISTICS Typical Quiescent Voltage Output Drift Across Temperature Range Sensitivity Drift Due to Package Hysteresis VOUT(Q) SensPKG A1318LUA-2-T TA = 150C -13 0 13 mV A1319LLHLX-5-T -20 - 20 mV A1319LUA-5-T -15 0 15 mV - 2 - % TA = 25C, after temperature cycling [1] 1 G (gauss) = 0.1 mT (millitesla), power-up, the output of the device is held low until VCC exceeds VUVLOHI. After the device is powered, the output remains valid until VCC drops below VUVLOLO , when the output is pulled low. [3] See the Characteristic Definitions section. [4] Determined by design and characterization, not evaluated at final test. [5] f varies as much as approximately 20% across the full operating ambient temperature range and process. C [6] V CLPLOW and VCLPHIGH scale with VCC due to ratiometry. [7] Sensitivity drift through the life of the part, Sens LIFE , can have a typical error value 3% in addition to package hysteresis effects. [8] Percent change from actual value at V CC = 3.3 V, for a given temperature. [9] Percent change from actual value at V CC = 3.3 V, TA = 25C. [2] On Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package CHARACTERISTIC DEFINITIONS Power-On Time. When the supply is ramped to its operating voltage, the device output requires a finite time to react to an input magnetic field. Power-On Time, tPO , is defined as the time it takes for the output voltage to begin responding to an applied magnetic field after the power supply has reached its minimum specified operating voltage, VCC(min), as shown in figure 1. Delay to Clamp. A large magnetic input step may cause the clamp to overshoot its steady state value. The Delay to Clamp, tCLP , is defined as the time it takes for the output voltage to settle within 1% of its steady state value, after initially passing through its steady state voltage, as shown in figure 2. Quiescent Voltage Output. In the quiescent state (no significant magnetic field: B = 0 G), the output, VOUT(Q), is at a constant ratio to the supply voltage, VCC, across the entire operating ranges of VCC and Operating Ambient Temperature, TA. Quiescent Voltage Output Drift Across Temperature. Range Due to internal component tolerances and thermal considerations, the Quiescent Voltage Output, VOUT(Q), may drift due to temperature changes within the Operating Ambient Temperature, TA. For purposes of specification, the Quiescent Voltage Output Drift Across Temperature Range, VOUT(Q) (mV), is defined as: VOUT(Q) = VOUT(Q)(TA) -VOUT(Q)(25C) V VCC VCC(typ) Sensitivity. The amount of the output voltage change is proportional to the magnitude and polarity of the magnetic field applied. This proportionality is specified as the magnetic sensitivity, Sens (mV/G), of the device and is defined as: VOUT 90% VOUT Sens = VCC(min) t1 t2 tPO +t Figure 1. Definition of Power On Time, tPO Device Output, VOUT (V) tCLP t1 t2 t1= time at which output voltage initially reaches steady state clamp voltage t2= time at which output voltage settles to within 1% of steady state clamp voltage time (s) Figure 2. Definition of Delay to Clamp, tCLP Magnetic Input Signal Magnetic Input Signal VOUT (B+) - (B-) (2) Sensitivity Temperature Coefficient. The device sensitivity changes as temperature changes, with respect to its Sensitivity Temperature Coefficient, TCSENS. TCSENS is programmed at 150C, and calculated relative to the baseline sensitivity programming temperature of 25C. TCSENS is defined as: t2= time at which output voltage settles within 10% of its steady state value under an applied magnetic field 0 VOUT(B+) - VOUT(B-) where B+ is the magnetic flux density in a positive field (south polarity) and B- is the magnetic flux density in a negative field (north polarity). t1= time at which power supply reaches minimum specified operating voltage VCLPHIGH (1) 1 SensT2 - SensT1 TCSens = 100 x (%/C) (3) SensT1 T2-T1 where T1 is the baseline Sens programming temperature of 25C, and T2 is the TCSENS programming temperature of 150C. The ideal value of Sens across the full ambient temperature range, SensIDEAL(TA), is defined as: SensIDEAL(TA) = SensT1 x [100 (%) + TCSENS (TA -T1)] (4) Sensitivity Drift Across Temperature Range. Second order sensitivity temperature coefficient effects cause the magnetic sensitivity, Sens, to drift from its ideal value across the operating ambient temperature range, TA. For purposes of specification, Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package the Sensitivity Drift Across Temperature Range, SensTC, is defined as: SensTA - SensIDEAL(TA) SensTC = x 100 (%) SensIDEAL(TA) (5) Sensitivity Drift Due to Package Hysteresis. Package stress and relaxation can cause the device sensitivity at TA = 25C to change during and after temperature cycling. This change in sensitivity follows a hysteresis curve. For purposes of specification, the Sensitivity Drift Due to Package Hysteresis, SensPKG, is defined as: Sens(25C)(2) - Sens(25C)(1) SensPKG = Sens(25C)(1) x 100 (%) (6) where Sens(25C)(1) is the programmed value of sensitivity at TA = 25C, and Sens(25C)(2) is the value of sensitivity at TA = 25C after temperature cycling TA up to 150C, down to -40C, and back to up 25C. Linearity Sensitivity Error. The A1318 and A1319 are designed to provide linear output in response to a ramping applied magnetic field. Consider two magnetic fields, B1 and B2. Ideally, the sensitivity of a device is the same for both fields, for a given supply voltage and temperature. Linearity error is present when there is a difference between the sensitivities measured at B1 and B2. Linearity Sensitivity Error, LINERR , is calculated separately for positive (LinERR+) and negative (LinERR- ) applied magnetic fields. LINERR (%) is measured and defined as: Sens(B+)(2) x 100 LinERR+ = 1- Sens(B+)(1) (%) Sens(B-)(2) x 100 LinERR- = 1- Sens(B-)(1) (%) (7) |VOUT(Bx) - VOUT(Q)| Bx BMAX(-) = VCLPHIGH - VOUT(Q) (10) Sens VOUT(Q) - VCLPLOW Sens Symmetry Sensitivity Error. The magnetic sensitivity of the device is constant for any two applied magnetic fields of equal magnitude and opposite polarities. Symmetry error, SymERR (%), is measured and defined as: Sens(B+) x 100 (%) SymERR = 1- (11) Sens(B-) where SensBx is as defined in equation 10, and B+ and B- are positive and negative magnetic fields such that |B+| = |B-|. Ratiometry Error. The A1318 and A1319 provide ratiometric output. This means that the Quiescent Voltage Output, VOUT(Q) , magnetic sensitivity, Sens, and clamp voltages, VCLPHIGH and VCLPLOW , are proportional to the supply voltage, VCC. In other words, when the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same percentage. Error is the difference between the measured change in the supply voltage relative to 3.3 V, and the measured change in each characteristic. The ratiometric error in quiescent voltage output, RatVOUT(Q) (%), for a given supply voltage, VCC, is defined as: (%) (12) The ratiometric error in magnetic sensitivity, RatSens (%), for a given supply voltage, VCC, is defined as: (8) and Bx are positive and negative magnetic fields, with respect to the quiescent voltage output, such that |B(+)(2)| > |B(+)(1)| and |B(-)(2)| > |B(-)(1)| The effective linearity error is: LinERR = max(|LinERR+| , |LinERR- |) BMAX(+) = VOUT(Q)(VCC) / VOUT(Q)(3.3V) RatVOUT(Q) = 1- x 100 VCC / 3.3 (V) where: SensBx = The output voltage clamps, VCLPHIGH and VCLPLOW , limit the operating magnetic range of the applied field in which the device provides a linear output. The maximum positive and negative applied magnetic fields in the operating range can be calculated: (9) Sens(VCC) / Sens(3.3V) x 100 (%) RatSens = 1- VCC / 3.3 (V) (13) The ratiometric error in the clamp voltages, RatVOUTCLP (%), for a given supply voltage, VCC, is defined as: VCLP(VCC) / VCLP(3.3V) x 100 RatVOUTCLP = 1- VCC / 3.3 (V) (%) (14) where VCLP is either VCLPHIGH or VCLPLOW . Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package Undervoltage Lockout. The A1318 and A1319 provide an undervoltage lockout feature which ensures that the device outputs a VOUT signal only when VCC is above certain thresholds . The undervoltage lockout feature provides a hysteresis of operation to eliminate indeterminate output states. VUVLOHI VCC The output of the A1318 and A1319 is held low (GND) until VCC exceeds VUVLOHI . After VCC exceeds VUVLOHI , the device VOUT output is enabled, providing a ratiometric output voltage that is proportional to the input magnetic signal and VCC . If VCC should drop back down below VUVLOLO after the device is powered up, the output would be pulled low (see figure 3) until VUVLOHI is reached again and VOUT would be reenabled. VCC Off Level. For applications in which the VCC pin of the A1318 or A1319 is being power-cycled (for example using a multiplexer to toggle the part on and off), the specification of VCC Off Level, VCCOFF , determines how high a VCC off voltage can be tolerated while still ensuring proper operation and startup of the device (see figure 4). VOUT time Figure 3. Definition of Undervoltage Lockout VCC(typ) Supply Voltage, VCC (V) VCC Ramp Time. The time taken for VCC to ramp from 0 V to VCC(typ), 3.3 V (see figure 4). VUVLOLO tVCC VCCOFF 0 time Figure 4. Definition of VCC Ramp Time, tVCC Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package APPLICATION INFORMATION A1318 A1319 VOUT VCC 3.3 V 0.1 F RL GND 4.7 nF Figure 5. Typical Application Circuit Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. Allegro employs a technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. In addition to the removal of the thermal and mechanical stress related offset, this novel technique also reduces the amount of thermal noise in the Hall sensor IC while completely removing the modulated residue resulting from the chopper operation. The chopper stabilization technique uses a high frequency sampling clock. For demodulation process, a sample and hold technique is used. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with highdensity logic integration and sample-and-hold circuits. Regulator Clock/Logic Hall Element Amp Anti-aliasing Tuned LP Filter Filter Figure 6. Chopper Stabilization Technique Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package Package LH, 3-Pin (SOT-23W) +0.12 2.98 -0.08 1.49 D 44 3 A +0.020 0.180-0.053 0.96 D +0.10 2.90 -0.20 +0.19 1.91 -0.06 2.40 0.70 D 0.25 MIN 1.00 2 1 0.55 REF 0.25 BSC 0.95 Seating Plane Gauge Plane 8X 10 REF B PCB Layout Reference View Branded Face 1.00 0.13 0.95 BSC +0.10 0.05 -0.05 0.40 0.10 NNN 1 C Standard Branding Reference View N = Last three digits of device part number For Reference Only; not for tooling use (reference DWG-2840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Active Area Depth, 0.28 mm REF B Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances C Branding scale and appearance at supplier discretion D Hall element, not to scale Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package Package UA, 3-Pin SIP +0.08 4.09 -0.05 45 B C E +0.08 3.02 -0.05 2.04 1.52 0.05 1.44 E 10 Mold Ejector Pin Indent E Branded Face A 1.02 MAX 45 0.79 REF NNN 1 1 2 D Standard Branding Reference View 3 = Supplier emblem N = Last three digits of device part number +0.03 0.41 -0.06 14.99 0.25 +0.05 0.43 -0.07 For Reference Only; not for tooling use (reference DWG-9065) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Dambar removal protrusion (6X) B Gate and tie bar burr area C Active Area Depth, 0.50 mm REF D Branding scale and appearance at supplier discretion E Hall element (not to scale) 1.27 NOM Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A1318 and A1319 Linear Hall-Effect Sensor ICs with Analog Output Available in a Miniature, Low-Profile Surface-Mount Package Revision History Number Date Description 1 June 27, 2014 2 April 8, 2016 Updated Selection Guide table 3 January 3, 2018 Updated Selection Guide table 4 January 15, 2019 Minor editorial updates Updated product offerings, VCLPHIGH Copyright (c)2019, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12