1 of 31 April 23, 2008
© 2008 Integrated Device Technology, Inc. DSC 6921
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
Device Overview
The 89HPES24N3A is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES24N3A is a 24-lane, 3-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
◆High Performance PCI Express Switch
– Twenty-four 2.5 Gbps PCI Express lanes
– Three switch ports
– Upstream port configurable up to x8
– Downstream ports configurable up to x8
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/
10B encoder/decoder (no separate transceivers needed)
◆Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
Block Diagram
Figure 1 Internal Block Diagram
x8 Upstream Port and Two x8 Downstream Ports
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
3-Port Switch Core
Frame Buffer Route Table Port
Arbitration Scheduler
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Dem u ltiple xe r
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
24 PCI Express Lanes
89HPES24N3A
Data Sheet
24-Lane 3-Port
PCI Express® Switch
2 of 31 April 23, 2008
IDT 89HPES24N3A Data Sheet
◆Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification
(PCI-PM 1.1)
• Supports device power management states: D0, D3hot and
D3cold
– Unused SerDes are disabled
◆Testability and Debug Features
– Ability to read and write any internal register via the SMBus
◆Eight General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆Packaged in 27x27mm 420 ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES24N3A
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 3
ports across 24 integrated serial lanes. Each lane provides 2.5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base specification revision 1.1.
SMBus Interface
The PES24N3A contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES24N3A,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES24N3A to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Bit Slave
SMBus
Address
Master
SMBus
Address
1 SSMBADDR[1] MSMBADDR[1]
2 SSMBADDR[2] MSMBADDR[2]
3 SSMBADDR[3] MSMBADDR[3]
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 2, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 2(a), the master and slave SMBuses are tied together and the
PES24N3A acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES24N3A registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES24N3A may be configured to operate in a split configuration as
shown in Figure 2(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES24N3A supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
4 0 MSMBADDR[4]
5 SSMBADDR[5] 1
61 0
71 1
Bit Slave
SMBus
Address
Master
SMBus
Address
Table 1 Master and Slave SMBus Address Assignment
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IDT 89HPES24N3A Data Sheet
Figure 2 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES24N3A supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24N3A
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES24N3A generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES24N3A. In response to an I/O expander interrupt, the PES24N3A generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES24N3A provides eight General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO
pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
The PES24N3A is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Trans-
action layers in compliance with PCI Express Base specification Revision 1.1. The PES24N3A can operate either as a store and forward or cut-
through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with
sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded applications.
Figure 3 I/O Expansion Application
Processor
PES24N3A
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES24N3A
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
... ...
(a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses
Memory
Memory
Memory
Processor
Memory
North
Bridge
PES24N3APES24N3A PES24N3A
I/O
10GbE I/O
10GbE I/O
SATA I/O
SATA
PCI Express
Slots
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IDT 89HPES24N3A Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES24N3A. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note: In the PES24N3A, the two downstream ports are labeled port 2 and port 4.
Signal Type Name/Description
PE0RP[7:0]
PE0RN[7:0] IPCI Express Port 0 Serial Data Receive. Differential PCI Ex press rec eive
pairs for port 0. Port 0 is the upstream port.
PE0TP[7:0]
PE0TN[7:0] OPCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PE2RP[7:0]
PE2RN[7:0] IPCI Express Port 2 Serial Data Receive. Differential PCI Ex press rec eive
pairs for port 2.
PE2TP[7:0]
PE2TN[7:0] OPCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE4RP[7:0]
PE4RN[7:0] IPCI Express Port 4 Serial Data Receive. Differential PCI Ex press rec eive
pairs for port 4.
PE4TP[7:0]
PE4TN[7:0] OPCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PEREFCLKP[2:1]
PEREFCLKN[2:1] IPCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
Signal Type Name/Description
MSMBADDR[4:1] I Master SMB us Address . These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM or I/O Expanders are being accessed.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins
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IDT 89HPES24N3A Data Sheet
Signal Type Name/Description
GPIO[0] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[1] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
GPIO[2] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
GPIO[3] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[4] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input
GPIO[5] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[6] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
Table 4 General Purpose I/O Pins
Signal Type Name/Description
CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi-
cates that a common clock is being used between the downstream device
and the downstream port.
CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi-
cates that a common clock is being used between the upstream device and
the upstream port.
MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
Table 5 System Pins (Part 1 of 2)
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IDT 89HPES24N3A Data Sheet
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside
PES24N3A and initiates a PCI Express fundamental reset.
RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES24N3A executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[3:0] I Switch Mode. These configuration pins determine the PES24N3A switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
Signal Type Name/Description
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal Type Name/Description
VDDCORE I Core VDD. Power supply for core logic.
VDDIO I I/O VDD. LVTTL I/O buffer power supply.
VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
Table 7 Power and Ground Pins
Signal Type Name/Description
Table 5 System Pins (Part 2 of 2)
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IDT 89HPES24N3A Data Sheet
Pin Characteristics
Note: Some input pads of the PES24N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE I PCI Express Termination Power.
VSS IGround.
Function Pin Name Type Buffer I/O
Type Internal
Resistor1Notes
PCI Express Inter-
face PE0RN[7:0] I CML Serial link
PE0RP[7:0] I
PE0TN[7:0] O
PE0TP[7:0] O
PE2RN[7:0] I
PE2RP[7:0] I
PE2TN[7:0] O
PE2TP[7:0] O
PE4RN[7:0] I
PE4RP[7:0] I
PE4TN[7:0] O
PE4TP[7:0] O
PEREFCLKN[2:1] I LVPECL/
CML Diff. Clock
Input Refer to Table 9
PEREFCLKP[2:1] I
REFCLKM I LVTTL Input pull-down
SMBus MSMBADDR[4:1] I LVTTL Input pull-up
MSMBCLK I/O STI2pull-up on board
MSMBDAT I/O STI pull-up on board
SSMBADDR[5,3:1] I Input pull-up
SSMBCLK I/O STI pull-up on board
SSMBDAT I/O STI pull-up on board
General Purpose I/O GPIO[7:0] I/O LVTTL High Drive pull-up
Table 8 Pin Characteristics (Part 1 of 2)
Signal Type Name/Description
Table 7 Power and Ground Pins
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IDT 89HPES24N3A Data Sheet
System Pins CCLKDS I LVTTL Input pull-up
CCLKUS I pull-up
MSMBSMODE I pull-down
PERSTN I
RSTHALT I pull-down
SWMODE[3:0] I pull-down
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up External pull-down
1. Internal resist or values under typical operating con ditions are 54K Ω for pull-up and 251K Ω for pull-down.
2. Schmitt Trigger Input (STI).
Function Pin Name Type Buffer I/O
Type Internal
Resistor1Notes
Table 8 Pin Characteristics (Part 2 of 2)
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IDT 89HPES24N3A Data Sheet
Logic Diagram — PES24N3A
Figure 4 PES24N3A Logic Diagram
Reference
Clocks
PEREFCLKP
PEREFCLKN
JTAG_TCK
GPIO[7:0]
8
General Purpo se
I/O
V
DD
CORE
V
DD
IO
V
DD
PE
V
DD
APE
Power/Ground
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
4
Master
SMBus Interface
Slave
SMBus Interface
CCLKUS
RSTHALT
System
Functions
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG
V
SS
SWMODE[3:0]
4
2
2
CCLKDS
PERSTN
REFCLKM
MSMBSMODE
V
TT
PE
PE0RP[0]
PE0RN[0]
PE0RP[7]
PE0RN[7]
PCI Express
Switch
SerDes Input
PE0TP[0]
PE0TN[0]
PE0TP[7]
PE0TN[7]
PCI Express
Switch
SerDes Output
...
Port 0
Port 0
...
PE2RP[0]
PE2RN[0]
PE2RP[7]
PE2RN[7]
PCI Express
Switch
SerDes Input
PE2TP[0]
PE2TN[0]
PE2TP[7]
PE2TN[7]
PCI Express
Switch
SerDes Output
...
Port 2
Port 2
...
PE4RP[0]
PE4RN[0]
PE4RP[7]
PE4RN[7]
PCI Express
Switch
SerDes Input
PE4TP[0]
PE4TN[0]
PE4TP[7]
PE4TN[7]
PCI Express
Switch
SerDes Output
...
Port 4
Port 4
...
PES24N3A
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
4
Slave
SMBus Interface
10 of 31 April 23, 2008
IDT 89HPES24N3A Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
AC Timing Characteristics
Parameter Description Min Typical Max Unit
RefclkFREQ Input reference clock frequency range 100 1251
1. The input clock frequency will be ei ther 100 or 125 MHz depending on signal REFCLKM.
MHz
RefclkDC2
2. ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
Duty cycle of input clock 40 50 60 %
TR, TFRise/Fall time of input clocks 0.2*RCUI RCUI3
3. RCUI (Reference Clock Unit Interval) refers to the reference clock period.
VSW Differential input voltage swing4
4. AC coupling required.
0.6 1.6 V
Tjitter Input clock jitter (cycle-to-cycle) 125 ps
RTTermination Resistor 110 Ohms
Table 9 Input Clock Requirements
Parameter Description Min1Typical1Max1Units
PCIe Transmit
UI Unit Interval 399.88 400 400.12 ps
TTX-EYE Minimum Tx Eye Width 0.7 .9 UI
TTX-EYE-MEDIAN-to-
MAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median 0.15 UI
TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps
TTX- IDLE-MIN Minimum time in idle 50 UI
TTX-IDLE-SET-TO-
IDLE
Maximum time to transition to a valid Idle after sending
an Idle ordered set 20 UI
TTX-IDLE-TO-DIFF-
DATA
Maximum time to transition from valid idle to diff data 20 UI
TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps
PCIe Receive
UI Unit Interval 399.88 400 400.12 ps
TRX-EYE (with jitter) Minimum Receiver Eye Width (jitte r tolerance) 0.4 UI
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
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IDT 89HPES24N3A Data Sheet
TRX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation 0.3 UI
TRX-IDLE-DET-DIFF-
ENTER TIME
Unexpected Idle Enter Detect Threshold Integration Time 10 ms
TRX-SKEW Lane to lane input skew 20 ns
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal Symbol Reference
Edge Min Max Unit Timing
Diagram
Reference
GPIO
GPIO[7:0]1
1. GPIO signals must meet the setup an d hold times if they are sy nch ronous o r the minimum pulse width if
they are asynchronous.
Tpw2
2. The values for this symbol were determined by calculation, not by testing.
None 50 — ns
Table 11 GPIO AC Timing Characteristics
Signal Symbol Reference
Edge Min Max Unit Timing
Diagram
Reference
JTAG
JTAG_TCK Tper_16a none 50.0 — ns See Figure 5.
Thigh_16a,
Tlow_16a 10.0 25.0 ns
JTAG_TMS1,
JTAG_TDI
1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occ ur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle stat e or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK risin g 2.4 — ns
Thld_16b 1.0 — ns
JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns
Tdz_16c2
2. The values for this symbol were determined by calculation, not by te sting.
—20ns
JTAG_TRST_N Tpw_16d2none 25.0 — ns
Table 12 JTAG AC Timing Characteristics
Parameter Description Min1Typical1Max1Units
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
12 of 31 April 23, 2008
IDT 89HPES24N3A Data Sheet
Figure 5 JTAG AC Timing Waveform
Recommended Operating Supply Voltages
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES24N3A, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the ne xt voltage in the sequence to en sure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power le vels. The power-down sequence must be in the reverse order of the
power-up sequence.
Symbol Parameter Minimum Typical Maximum Unit
VDDCORE Internal logic supp ly 0.9 1.0 1.1 V
VDDI/O I/O supply except for SerDes LVPECL/CML 3.0 3.3 3.6 V
VDDPE PCI Express Digital Power 0.9 1.0 1.1 V
VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V
VTTPE PCI Express Serial Data Transmit
Termination Voltage 1.425 1.5 1.575 V
VSS Common ground 0 0 0 V
Table 13 PES24N3A Operating Voltages
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
13 of 31 April 23, 2008
IDT 89HPES24N3A Data Sheet
Recommended Operating Temperature
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Thermal Considerations
This section describes thermal considerations for the PES24N3A (27mm2 BXG420 package). The data in Table 16 below contains information that
is relevant to the thermal performance of the PES24N3A switch.
Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance
can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective
θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card.
Grade Temperature
Commercial 0°C to +70°C Ambient
Table 14 PES24N3A Operating Temperatures
Number of active
Lanes per Port
Core Supply PCIe Digital
Supply PCIe Analog
Supply PCIe Termin-
ation Supply I/O Supply Total
Typ
1.0V Max
1.1V Typ
1.0V Max
1.1V Typ
1.0V Max
1.1V Typ
1.5V Max
1.575V Typ
3.3V Max
3.6V Typ
Power Max
Power
8/8/8 mA 705 928 1037 1247 415 455 520 617 1 1 2.9W 3.9W
Watts 0.705 1.02 1.037 1.37 0.415 0.50 0.78 0.97 0.003 0.004
8/4/4 mA 676 845 873 1004 409 434 360 408 1 1 2.5W 3.2W
Watts 0.676 0.93 0.873 1.104 0.41 0.477 0.36 0.643 0.003 0.004
Table 15 PES24N3A Power Consumption
Symbol Parameter Value Units Conditions
TJ(max) Junction Temperature 125 oCMaximum
TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products
θJA(effective) Effective Thermal Resistance, Junction-to-Ambient
10.6 oC/W Zero air flo w
8.5 oC/W 1 m/S air flow
7.6 oC/W 2 m/S air flow
θJB Thermal Resistance, Junction-to-Board 6.8 oC/W
θJC Thermal Resistance, Junction-to-Case 0.7 oC/W
P Power Dissipation of the Device 3.9 Watts Maximum
Table 16 Thermal Specifications for PES24N3A, 27x27 mm BXG420 Package
14 of 31 April 23, 2008
IDT 89HPES24N3A Data Sheet
Heat Sink
Table 17 lists heat sink requirements for the PES24N3A under three common usage scenarios. As shown in this table, a heat sink is not required
in most cases.
.
Thermal Usage Examples
The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surroundings in the absence of a
heat sink. The general formula to determine θJA is:
θ
JA = (TJ - TA)/P
Thermal reliability of a device is generally assured when the actual value of TJ in the specific system environment being considered is less than the
maximum TJ specified for the device. Using an ambient temperature of 70oC and assuming a system with 1m/S airflow, the actual value of TJ is:
TJ(actual) = TA + P *
θ
JA(eff) = 70oC + 3.9W * 8.5W/oC = 103oC
The actual TJ of 103oC is well below the maximum TJ of 125oC specified for the device (shown in Table 16). Therefore, no heat sink is needed in
this scenario. The formula is also useful from a system design perspective. It can be used to determine if a heat sink should be added to the device
based on some desired value of TJ. For example, if for reliability purposes the desired TJ is 100oC, then the maximum allowable TA is:
TA(allowed) = TJ(desired) - (P *
θ
JA(effective))
TA(allowed) = 100oC - (3.9W * 8.5W/oC) = 100oC - 33oC = 67oC
An appropriate level of increased air flow and/or a heat sink can be added to achieve this lower ambient temperature. Please contact
ssdhelp@idt.com for further assistance.
Air Flow Board Size Board Layers Heat Sink Requirement
Zero 3.9”x6.2” (ExpressModule form factor) or larger 10 or more No heat sink required
Zero Any 14 or more No heat sink required
1 m/S or more Any Any No heat sink required
Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics
15 of 31 April 23, 2008
IDT 89HPES24N3A Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type Parameter Description Min1Typ1Max1Unit Conditions
Serial Link PCIe Transmit
VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV
VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB
VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V
VTX-CM-ACP RMS AC peak common mode output volt-
age 20 mV
VTX-CM-DC-
active-idle-delta
Abs delta of DC common mode voltage
between L0 and idle 100 mV
VTX-CM-DC-line-
delta
Abs delta of DC common mode voltage
between D+ and D- 25 mV
VTX-Idle-DiffP Electrical idle diff peak output 20 mV
Serial Link
(cont.) VTX-RCV-Detect Voltage change during receiver detection 600 mV
RLTX-DIFF Transmitter Differential Return loss 12 dB
RLTX-CM Transmitter Common Mode Return loss 6 dB
ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω
ZOSE Single ended TX Impedance 40 50 60 Ω
Transmitter Eye
Diagram TX Eye Height (De-emphasized bits) 505 650 mV
Transmitter Eye
Diagram TX Eye Height (Transition bits) 800 950 mV
PCIe Receive
VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV
VRX-CM-AC Receiver common-mode voltage for AC
coupling 150 mV
RLRX-DIFF Receiver Differential Return Loss 15 dB
RLRX-CM Receiver Common Mode Return Loss 6 dB
ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω
ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω
ZRX-COMM-HIGH-
Z-DC
Powered down input common mode
impedance (DC) 200k 350k Ω
VRX-IDLE-DET-
DIFFp-p
Electrical idle detect threshold 65 175 mV
PCIe REFCLK
CIN Input Capacitance 1.5 — pF
Table 18 DC Electrical Characteristics (Part 1 of 2)
16 of 31 April 23, 2008
IDT 89HPES24N3A Data Sheet
Other I/Os
LOW Drive
Output IOL —2.5—mA V
OL = 0.4v
IOH —-5.5—mA V
OH = 1.5V
High Drive
Output IOL —12.0—mA V
OL = 0.4v
IOH —-20.0—mA V
OH = 1.5V
Schmitt Trig-
ger Input
(STI)
VIL -0.3 — 0.8 V —
VIH 2.0 — VDDIO +
0.5 V—
Input VIL -0.3 — 0.8 V —
VIH 2.0 — VDDIO +
0.5 V—
Capacitance CIN ——8.5pF —
Leakage Inputs — — + 10 μAV
DDI/O (max)
I/OLEAK W/O
Pull-ups/downs ——+ 10 μAV
DDI/O (max)
I/OLEAK WITH
Pull-ups/downs ——+ 80 μAV
DDI/O (max)
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1.
I/O Type Parameter Description Min1Typ1Max1Unit Conditions
Table 18 DC Electrical Characteristics (Part 2 of 2)
17 of 31 April 23, 2008
IDT 89HPES24N3A Data Sheet
Package Pinout — 420-BGA Signal Pinout for PES24N3A
The following table lists the pin numbers and signal names for the PES24N3A device.
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
A1 VSS B9 MSMBDAT C17 VDDIO D25 VSS
A2 VSS B10 SSMBADDR_2 C18 VSS D26 PEREFCLKN2
A3 VSS B11 SSMBADDR_5 C19 VDDIO E1 VSS
A4 JTAG_TDI B12 SSMBDAT C20 VSS E2 VSS
A5 JTAG_TMS B13 NC C21 VDDIO E3 VSS
A6 MSMBADDR_1 B14 SWMODE_0 C22 VSS E4 VSS
A7 MSMBADDR_3 B15 SWMODE_2 C23 VDDIO E5 VSS
A8 MSMBCLK B16 NC C24 VSS E6 VDDCORE
A9 SSMBADDR_1 B17 VDDIO C25 VSS E7 VDDCORE
A10 SSMBADDR_3 B18 GPIO_00 1 C26 PEREFCLKP2 E8 VSS
A11 SSMBCLK B19 GPIO_02 1 D1 PEREFCLKP1 E9 VDDCORE
A12 CCLKUS B20 GPIO_04 1 D2 VSS E10 VSS
A13 CCLKDS B21 GPIO_06 D3 VSS E11 VDDCORE
A14 NC B22 MSMBSMODE D4 VSS E12 VSS
A15 SWMODE_1 B23 REFCLKM D5 VDDCORE E13 VDDCORE
A16 SWMODE_3 B24 VDDIO D6 VDDCORE E14 VSS
A17 PERSTN B25 VSS D7 VSS E15 VDDCORE
A18 RSTHALT B26 VSS D8 VDDCORE E16 VSS
A19 GPIO_01 1 C1 PEREFCLKN1 D9 VSS E17 VDDCORE
A20 GPIO_03 C2 VSS D10 VDDCORE E18 VSS
A21 GPIO_05 C3 VSS D11 VSS E19 VDDCORE
A22 GPIO_07 1 C4 VDDCORE D12 VDDCORE E20 VDDCORE
A23 VSS C5 VDDIO D13 VDDCORE E21 VDDCORE
A24 VSS C6 VSS D14 VSS E22 VSS
A25 VSS C7 VDDIO D15 VDDCORE E23 VSS
A26 VSS C8 VSS D16 VSS E24 VSS
B1 VSS C9 VDDIO D17 VDDCORE E25 VSS
B2 VSS C10 VSS D18 VDDCORE E26 VSS
B3 VDDIO C11 VDDIO D19 VDDCORE F1 VDDCORE
B4 JTAG_TCK C12 VSS D20 VSS F2 VDDCORE
B5 JTAG-TDO C13 VDDIO D21 VDDCORE F3 VDDAPE
B6 JTAG-TRST_N C14 VDDCORE D22 VDDCORE F4 VSS
B7 MSMBADDR_2 C15 VDDIO D23 VSS F5 VSS
B8 MSMBADDR_4 C16 VDDCORE D24 VSS F22 VSS
Table 19 PES24N3A 420-pin Signal Pin-Out (Part 1 of 3)