Silicon SPDT Switch, Nonreflective, 100 MHz to 44 GHz ADRF5026 Data Sheet GND GND RF2 GND GND 19 18 17 16 20 GND FUNCTIONAL BLOCK DIAGRAM 1 15 VSS EN 50 2 14 RFC 3 DRIVER 13 GND 4 GND 5 9 GND GND 10 8 RF1 7 GND 50 GND 12 CTRL 11 VDD 16767-001 GND 6 Ultrawideband frequency range: 100 MHz to 44 GHz Nonreflective design Low insertion loss 1.2 dB to 18 GHz 1.7 dB to 26 GHz 2.4 dB to 40 GHz 3.8 dB to 44 GHz High isolation 55 dB to 18 GHz 53 dB to 26 GHz 50 dB to 40 GHz 45 dB to 44 GHz High input linearity P1dB: 27 dBm typical IP3: 53 dBm typical High power handling 24 dBm insertion loss path 24 dBm isolation path All off state control No low frequency spurious signals 0.1 dB RF settling time: 40 ns typical 20-terminal, 3 mm x 3 mm LGA package Pin compatible with ADRF5027, low frequency cutoff version GND FEATURES Figure 1. APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5026 is a nonreflective, single-pole, double-throw (SPDT) radio frequency (RF) switch manufactured in a silicon process. The ADRF5026 operates from 100 MHz to 44 GHz with better than 3.8 dB of insertion loss and 45 dB of isolation. The ADRF5026 features an all off control, where both RF ports are in an isolation state. The ADRF5026 has a nonreflective design and both of the RF ports are internally terminated to 50 . The ADRF5026 requires a dual-supply voltage of +3.3 V and -3.3 V. The device employs complimentary metal-oxide semiconductor/low-voltage transistor-transistor logic (CMOS/LVTTL) logic-compatible controls. Rev. 0 The ADRF5026 is pin-compatible with the ADRF5027 low frequency cutoff version, which operates from 9 kHz to 44 GHz. The ADRF5026 RF ports are designed to match a characteristic impedance of 50 . For ultrawideband products, impedance matching on the RF transmission lines can further optimize high frequency insertion loss and return loss characteristics. Refer to the Narrow-Band Impedance Matching section for an example of a matched circuit that achieves a flat insertion loss response of 2.4 dB from 28 GHz to 43 GHz. The ADRF5026 comes in a 20-terminal, 3 mm x 3 mm, RoHScompliant, land grid array (LGA) package and can operate from -40C to +105C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5026 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Interface Schematics .....................................................................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................7 Revision History ............................................................................... 2 Input Power Compressions and Third-Order Intercept ..........8 Specifications..................................................................................... 3 Theory of Operation .........................................................................9 Electrical Specifications ............................................................... 3 Applications Information .............................................................. 10 Absolute Maximum Ratings............................................................ 5 Evaluation Board ........................................................................ 10 Thermal Resistance ...................................................................... 5 Probe Matrix Board ................................................................... 11 Power Derating Curves ................................................................ 5 Outline Dimensions ....................................................................... 13 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 13 REVISION HISTORY 7/2018--Revision 0: Initial Version Rev. 0 | Page 2 of 13 Data Sheet ADRF5026 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V, VSS = -3.3 V, VCTRL/VEN = 0 V or VDD, and TCASE = 25C in a 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RF1/RF2 Symbol RETURN LOSS RFC and RF1/RF2 (On) RL Test Conditions/Comments Min 100 Typ Max 44,000 Unit MHz IL RF1/RF2 (Off ) ISOLATION Between RFC and RF1/RF2 Between RF1 and RF2 SWITCHING CHARACTERISTICS Rise and Fall Time On and Off Time RF Settling Time 0.1 dB 0.05 dB INPUT LINEARITY2 1 dB Compression Third-Order Intercept P1dB IP3 SUPPLY CURRENT Positive Negative IDD ISS tRISE, tFALL tON, tOFF 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz1 1.2 1.7 2.2 2.4 3.8 dB dB dB dB dB 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz1 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz1 22 12 9 10 7 23 23 21 13 12 dB dB dB dB dB dB dB dB dB dB 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 55 53 53 50 45 63 60 60 63 55 dB dB dB dB dB dB dB dB dB dB 10% to 90% of RF output 50% of triggered VCTRL to 90% of RF output 3 14 ns ns 50% of triggered VCTRL to 0.1 dB of final RF output 50% of triggered VCTRL to 0.05 dB of final RF output 100 MHz to 40 GHz 40 45 ns ns 27 53 dBm dBm 2 100 A A Two-tone input power = 12 dBm each tone, f = 1 MHz VDD and VSS pins Rev. 0 | Page 3 of 13 ADRF5026 Parameter DIGITAL CONTROL INPUTS Voltage Low High Current Low and High Current RECOMMENDED OPERATING CONDITONS Supply Voltage Positive Negative Digital Control Voltage RF Input Power3 Insertion Loss Path Data Sheet Symbol VINL VINH Min VDD VSS VCTRL, VEN PIN Typ 0 1.2 IINL, IINH Isolation Path Hot Switching Case Temperature Test Conditions/Comments CTRL and EN pins Max Unit 0.8 3.3 V V <1 3.15 -3.45 0 f = 100 MHz to 40 GHz, TCASE = 85C4 RF signal is applied to the RFC or through connected RF1/RF2 RF signal is applied to terminated RF1/RF2 RF signal is present at the RFC while switching between RF1 and RF2 TCASE -40 1 A 3.45 -3.15 VDD V V V 24 dBm 24 24 dBm dBm +105 C Impendence matching on RF transmission lines improves high frequency performance. Refer to the Applications Information section for more information. For input linearity performance vs. frequency, see Figure 11 and Figure 13. 3 For power derating vs. frequency, see Figure 2 and Figure 3. This power derating is applicable for insertion loss path, isolation path, and hot switching power specifications. 4 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. 2 Rev. 0 | Page 4 of 13 Data Sheet ADRF5026 ABSOLUTE MAXIMUM RATINGS For recommended operating conditions, see Table 1. POWER DERATING CURVES 2 Table 2. Rating -0.3 V to +3.6 V -3.6 V to +0.3 V -0.3 V to VDD +0.3 V 26 dBm 25 dBm 25 dBm 0 POWER DERATING (dB) Parameter Positive Supply Voltage Negative Supply Voltage Digital Control Input Voltage RF Input Power1 (100 MHz to 40 GHz at TCASE = 85C2) Insertion Loss Path Isolation Path Hot Switching Temperature Junction, TJ Storage Range Reflow Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) RFC, RF1, RF2 Pins Digital Pins Charged Device Model (CDM) -4 -6 -8 -10 -14 10k 100k 1M 10M 100M 1G 10G 100G FREQUENCY (Hz) 16767-002 -12 135C -65C to +150C 260C Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85C 2 500 V 2000 V 1250 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. 32 34 36 38 40 42 44 46 48 50 Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85C ESD CAUTION Table 3. Thermal Resistance C/W C/W -8 FREQUENCY (GHz) JC is the junction to case bottom (channel to package bottom) thermal resistance. 423 241 -6 -12 30 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Unit -4 -10 THERMAL RESISTANCE JC -2 16767-003 For power derating vs. frequency, see Figure 2 and Figure 3. This power derating is applicable for insertion loss path, isolation path, and hot switching power specifications. 2 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. POWER DERATING (dB) 0 1 Package Type CC-20-3 Through Path Terminated Path -2 Rev. 0 | Page 5 of 13 ADRF5026 Data Sheet GND GND 18 17 16 GND 1 15 VSS GND 2 14 EN RFC 3 13 GND GND 4 12 CTRL GND 5 11 VDD ADRF5026 6 7 8 9 10 GND GND RF1 GND GND TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND OF THE PCB. 16767-004 20 19 RF2 GND GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 2, 4, 5, 6, 7, 9, 10, 13, 16, 17, 19, 20 3 Mnemonic GND Description Ground. These pins must be connected to the RF and dc ground of the PCB. RFC 8 RF1 11 12 14 15 18 VDD CTRL EN VSS RF2 RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. Positive Supply Voltage. Control Input Voltage. See Table 5 for the truth table. See Figure 6 for the interface schematic. Enable Input Voltage. See Table 5 for the truth table. See Figure 6 for the interface schematic. Negative Supply Voltage. RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB. EPAD INTERFACE SCHEMATICS VDD 16767-005 RFC, RF1, RF2 VDD CTRL, EN 16767-006 Figure 5. RFC, RF1, RF2 Interface Schematic Figure 6. CTRL, EN Interface Schematic Rev. 0 | Page 6 of 13 Data Sheet ADRF5026 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, AND ISOLATION VDD = 3.3 V, VSS = -3.3 V, VCTRL/VEN = 0 V or VDD, and TCASE = 25C in a 50 system, unless otherwise noted. Insertion loss and return loss are measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins. Signal coupling between the probes limits the isolation performance of ADRF5026. Isolation is measured on the ADRF5026-EVALZ evaluation board. See the Applications Information section for details on the ADRF5026-EVALZ evaluation board and probe matrix board. -1 -1 INSERTION LOSS (dB) -2 -3 -4 -5 -3 -4 -5 -6 -7 -7 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) -8 -5 -10 -10 -20 ISOLATION (dB) 0 -25 -30 10 15 20 25 30 35 40 45 50 RFC TO RF1/RF2 RF1 TO RF2 -30 -40 -50 -60 RFC RF1/RF2 ON RF1/RF2 OFF 0 5 10 15 20 25 30 35 FREQUENCY (GHz) 40 45 -70 50 16767-010 -35 -40 5 Figure 9. Insertion Loss vs. Frequency over Temperature 0 -20 0 = +105C = +85C = +25C = -40C FREQUENCY (GHz) Figure 7. Insertion Loss vs. Frequency at Room Temperature for RF1 and RF2 -15 TCASE TCASE TCASE TCASE Figure 8. Return Loss vs. Frequency -80 0 5 10 15 20 25 30 35 FREQUENCY (GHz) Figure 10. Isolation vs. Frequency Rev. 0 | Page 7 of 13 40 45 50 16767-008 -8 RETURN LOSS (dB) -2 -6 16767-009 INSERTION LOSS (dB) 0 RF1, TCASE = 25C RF2, TCASE = 25C 16767-007 0 ADRF5026 Data Sheet INPUT POWER COMPRESSIONS AND THIRD-ORDER INTERCEPT 30 28 28 26 26 24 24 22 20 18 16 20 18 16 14 14 12 12 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) 10 10k 55 55 50 50 INPUT IP3 (dBm) 60 45 40 35 35 25 20 25 30 FREQUENCY (GHz) 35 40 16767-012 25 15 1G 40 30 10 100M 45 30 5 10M Figure 13. Input P1dB vs. Frequency (Low Frequency Detail) 60 0 1M FREQUENCY (Hz) Figure 11. Input P1dB vs. Frequency 20 100k Figure 12. Input IP3 vs. Frequency 20 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 14. Input IP3 vs. Frequency (Low Frequency Detail) Rev. 0 | Page 8 of 13 1G 16767-014 10 INPUT IP3 (dBm) 22 16767-013 INPUT P1dB (dBm) 30 16767-011 INPUT P1dB (dBm) VDD = 3.3 V, VSS = -3.3 V, VCTRL/VEN = 0 V or VDD, and TCASE = 25C in a 50 system, unless otherwise noted. All of the large signal performance parameters are measured on the ADRF5026-EVALZ evaluation board. Data Sheet ADRF5026 THEORY OF OPERATION The ADRF5026 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to filter high frequency noise. All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V, and no dc blocking capacitors are required at the RF ports when the RF potential is equal to 0 V. The RF ports are internally matched to 50 . Therefore, external matching networks are not required. Impedance matching on the RF transmission lines can improve insertion loss and return loss performance at high frequencies. The ADRF5026 integrates a driver to perform logic function internally and to provide the advantage of a simplified control interface. The driver features two digital control input pins, CTRL and EN. When the EN pin is logic low, the logic level applied to the CTRL pin determines which RF port is in insertion loss state and which RF port is in isolation state. The ADRF5026 supports an all off state control. When the EN pin is logic high, both the RF1 to RFC path and the RF2 to RFC path are in an isolation state, regardless of the logic state of the CTRL pin. The RF1 and RF2 ports are terminated to internal 50 resistors, and the RFC port becomes open reflective (see Table 5). The ADRF5026 design is bidirectional with equal power handling capabilities. An RF input signal (RFIN) can be applied to the RFC port or the RF1 or RF2 port. The isolation path provides high loss between the unselected RFx port and the insertion loss path. The power-up sequence is as follows: 1. 2. 3. 4. 5. Power up GND. Power up VDD. Power up VSS. Power up the digital control inputs. The relative order of the logic control inputs is not important. Powering up the digital control inputs before the VDD supply can inadvertently forward bias and damage the internal ESD protection structures. Apply an RF input signal. The power-down sequence is the reverse order of the power-up sequence. Table 5. Control Voltage Truth Table EN Low Low High High Digital Control Input CTRL Low High Low High RF1 to RFC Isolation (off ) Insertion loss (on) Isolation (off ) Isolation (off ) Rev. 0 | Page 9 of 13 RF Paths RF2 to RFC Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) ADRF5026 Data Sheet APPLICATIONS INFORMATION 0 EVALUATION BOARD G = 7mil W = 14mil 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) RO4003 T = 2.2mil H = 8mil -2 -3 -4 -5 -6 0.5oz Cu (0.7mil) THRU LOSS EMBEDDED IL DEEMBEDDED IL TOTAL THICKNESS ~62mil -7 -8 0 5 10 15 20 25 30 35 40 16767-017 1.5oz Cu (2.2mil) -1 INSERTION LOSS (dB) The ADRF5026-EVALZ evaluation board is a 4-layer evaluation board. The outer copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil) and are separated by dielectric materials. Figure 15 shows the ADRF5026-EVALZ evaluation board stack up. 45 FREQUENCY (GHz) Figure 17. Insertion Loss vs. Frequency 1.5oz Cu (2.2mil) 16767-015 0.5oz Cu (0.7mil) Figure 15. Evaluation Board Stack Up All RF and dc traces are routed on the top copper layer, whereas the inner and bottom layers are ground planes that provide a solid ground for the RF transmission lines. The top dielectric material is 8 mil Rogers RO4003, which offers optimal high frequency performance. The middle and bottom dielectric materials provide mechanical strength. The overall board thickness is 62 mil, which allows 2.4 mm RF launchers to be connected at the board edges. Two power supply ports are connected to the VDD and VSS test points, and the ground reference is connected to the GND test point. On the supply traces, VDD and VSS, a 100 pF bypass capacitor filters high frequency noise. Additionally, unpopulated component positions are available for applying extra bypass capacitors. Two control ports are connected to the EN and CTRL test points. There are provisions for the resistor capacitor (RC) filter to eliminate dc-coupled noise, if needed by the application. The ADRF5026-EVALZ evaluation board schematic is shown in Figure 18. The thru calibration line, THRU CAL, can calibrate out the board loss effects from the ADRF5026-EVALZ evaluation board measurements to determine the device performance at the pins of the IC. Figure 17 shows the typical board loss for the ADRF5026-EVALZ evaluation board at room temperature, the embedded insertion loss, and the de-embedded insertion loss for the ADRF5026. Rev. 0 | Page 10 of 13 GND RF2 ADRF5026 3 13 4 12 5 11 6 RF1 GND 14 7 8 9 EN GND CTRL R3 0 EN R4 0 CTRL VDD VDD C10 100pF 10 GND GND 2 VSS THRU_CAL Figure 18. Simplified Evaluation Board Schematic 16767-018 The RF input and output ports (RFC, RF1, and RF2) are connected through 50 transmission lines to the 2.4 mm launchers (J1, J2, and J3, respectively). These high frequency RF launchers are connected by contact and are not soldered to the board. RFC GND 16 15 GND The RF transmission lines are designed using a coplanar waveguide (CPWG) model with a width of 14 mil and a ground spacing of 7 mil, and have a characteristic impedance of 50 . For optimal RF and thermal grounding, as many plated through vias as possible are arranged around transmission lines and under the exposed pad of the package. 17 GND RFC 18 RF1 Figure 16. Evaluation Board Layout GND 19 VSS C7 100pF 1 GND 16767-016 20 GND GND GND RF2 ADRF5026 16767-025 Data Sheet Figure 19. Evaluation Board Component Placement Table 6. Evaluation Board Components Component RF1_A, RFC_A, RF2_A VDD_A, VSS_A, CTRL_A, EN_A, GND_A C7, C10 R3, R4 U2 Description End launch connectors, 2.4 mm Through-hole mount test points 100 pF capacitors, 0402 package 0 resistors, 0402 package ADRF5026 SPDT switch PROBE MATRIX BOARD The probe matrix board is a 4-layer board. This board also uses an 8 mil Rogers RO4003 dielectric. The outer copper layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil). The RF transmission lines were designed using a CPWG model with a width of 14 mil and a ground spacing of 7 mil to have a characteristic impedance of 50 . G = 7mil W = 14mil 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) RO4003 T = 2.2mil The ADRF5026-EVALZ evaluation board is used for making isolation measurements. RF traces for a through-reflect-line (TRL) calibration are designed on the probe matrix board. Board loss is compensated for by using a nonzero line length at calibration. The actual board duplicates the same layout in matrix form, which allows multiple devices to assemble at once. Insertion loss and return loss measurements are made on this board, while isolation measurements are made on the ADRF5026-EVALZ evaluation board. RF2 H = 8mil TOTAL THICKNESS ~62mil 0.5oz Cu (0.7mil) RFC VSS EN CTRL VDD EPAD RF1 Figure 20. Probe Matrix Board Stack Up Figure 20 and Figure 21 show the stack up and the layout, respectively, of the probe matrix board. Measurements are made using GSG probes at close proximity to the RF pins. Probing reduces the reflections caused by mismatch arising from connectors, cables, and board layout, resulting in a more accurate measurement of insertion loss and return loss. Signal coupling between the RF probes limits the isolation measurement. Rev. 0 | Page 11 of 13 7mil 14mil 10mil 8mil 7mil 16767-020 1.5oz Cu (2.2mil) 16767-019 0.5oz Cu (0.7mil) Figure 21. Probe Matrix Board Layout ADRF5026 Data Sheet 0 Narrow-Band Impedance Matching 5G mmWave Frequencies -1 INSERTION LOSS (dB) -2 -3 -4 Table 7, Figure 23, Figure 24, and Figure 25 show the measured performance of ADRF5026 on the impedance matched circuit on the probe matrix board. -5 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) 16767-022 Narrow-band impedance matching on the RF transmission lines can improve return loss and insertion loss for a targeted frequency range. The impedance matched circuit, highlighted in Figure 22, achieves a flat insertion loss response of 2.4 dB from 28 GHz to 43 GHz (see Figure 23). The dimensions of the 50 lines are 14 mil trace width and a 7 mil gap. To implement this impedance matched circuit, an 8 mil trace with a width of 5 mil is inserted between the pin pad and the 50 trace. Figure 23. Insertion Loss vs. Frequency, with Impedance Matching RF2 0 -5 14mil 8mil 10mil 5mil -20 -25 -30 RFC RF1/RF2 ON RF1/RF2 OFF -35 7mil 16767-021 -40 Return Loss RFC and RF1/RF2 (On) RF1/RF2 (Off) 10 15 20 25 30 0 40 45 RFC TO RF1/RF2 RF1 TO RF2 -10 Typ 35 Figure 24. Return Loss vs. Frequency, with Impedance Matching Table 7. Impedance Matched Parameters -20 Unit -30 1.3 2.0 2.4 2.4 2.5 dB dB dB dB dB 17 10 7 9 15 dB dB dB dB dB 18 17 18 12 7 dB dB dB dB dB ISOLATION (dB) Test Condition See Figure 23 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz See Figure 24 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz See Figure 24 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 5 FREQUENCY (GHz) Figure 22. Impedance Matched Circuit Parameter Insertion Loss Between RFC and RF1/RF2 0 16767-023 7mil -15 Rev. 0 | Page 12 of 13 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 25 30 35 40 45 FREQUENCY (GHz) Figure 25. Isolation vs. Frequency, with Impedance Matching 16767-024 RF1 -10 RETURN LOSS (dB) EPAD 8mil RFC VSS EN CTRL VDD Data Sheet ADRF5026 OUTLINE DIMENSIONS 3.10 3.00 2.90 16 CHAMFERED PIN 1 (0.3 x 45) 20 1 15 1.60 REF SQ 0.40 BSC TOP VIEW 0.776 0.726 0.676 SIDE VIEW 1.70 1.60 SQ 1.50 EXPOSED PAD 11 5 10 6 0.13BOTTOM VIEW REF 0.530 REF 0.236 0.196 0.156 PKG-004908 0.70 REF FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 05-25-2016-B PIN 1 CORNER AREA 0.25 0.20 0.15 0.30 0.25 0.20 Figure 26. 20-Terminal Land Grid Array [LGA] 3 mm x 3 mm Body and 0.726 mm Package Height (CC-20-3) Dimensions shown in millimeters ORDERING GUIDE Model1 ADRF5026BCCZN ADRF5026BCCZN-R7 ADRF5026-EVALZ 1 Temperature Range -40C to +105C -40C to +105C Package Description 20-Terminal Land Grid Array [LGA] 20-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16767-0-7/18(0) Rev. 0 | Page 13 of 13 Package Option CC-20-3 CC-20-3 Marking Code 026 026