Datasheet January 2000 MB86061 Version 1.0 12-Bit 400MSa/s Digital to Analog Converter The Fujitsu MB86061 is a high performance 12-bit 400MSa/s digital to analog converter (DAC). Use of novel techniques for the converter architecture delivers high speed operation consistent with BiCMOS or bipolar devices but at the low power of CMOS. Fujitsu's proprietary architecture is the subject of several patent applications. Excellent SFDR performance coupled with high speed conversion rate and low power make this device particularly suitable for high performance communication systems, graphics and test/instrumentation equipment applications. FME/MS/SFDAC1E/DS/4271 PLASTIC PACKAGE QFP-64 Features * 12-bit 400MSa/s Digital to Analog converter (FPT-64P-M09) * True ECL digital interface (-2V supply) * 85dBc SFDR @ 10MHz, 200MSa/s * Low power, 3.3V and -2V operation (308mW @ 300MSa/s) PIN ASSIGNMENT D9 VEE D8 DVDD D6 DVSS D7 DVDD D5 VEE DVSS D3 D4 D1 * Industrial temperature range (-40 C to +85 C) VEE D2 * 0.35m CMOS technology with Triple Well * Plastic Package, 64-pin QFP Applications * Test & instrumentation equipment * Communication systems * High performance graphics D0 VTH VSS VDD TWOC N/C VSS VDD DSUB ASUB SHUF0 SHUF1 RVSS BGAP VREF RREF D10 D11 VSS VDD N/C N/C VSS VDD DSUB CSUB RESETB CVDD CVSS CLK CVEE CLKB MB86061 AVSS AVDD CVDD CVSS AVSS IOUT IOUT AVDD AVDD AVDD AVSS IOUTB IOUTB AVSS RVSS RVDD Pin #1 This product has Patents applied for in the US and elsewhere including GB2333191A, EP0935345A, JP11-274934A, GB2333171A, EP0930717A, JP11-274935A, GB2333190A, EP0929158A, JP11-243339A, GB2335097A, EP0940923A, JP11-317667A, GB2335076A, EP0940852A, JP11-251530A. Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 1 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter Contents 1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1.1 Segment Shuffling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3.1 Analog Output Reference Resistor . . . . . . . . . . . . . . . . . . . .5 1.3.2 Analog Output Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3.3 Analog Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.4 Digital Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.5 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5.1 Substrate Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.5.2 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2 Digital Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.4 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6 Typical Performance Characterisation Graphs . . . . . . . . . . . . . . . .13 4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.1 Power & Ground Plane Regions . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.2 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.4 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.5 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.2 Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.3 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.3.1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6 Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Page 2 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 1 Functional Description The MB86061 is a high performance 12-bit 400MSa/s digital to analog converter. Versatile interfacing via the 12-bit true ECL data input allows existing system requirements to be accommodated, using either offset binary or 2's complement data formats. The device requires an external clock. A 1.25V bandgap reference is provided on-chip, which may be overdriven where an external reference is to be used. A power-down mode is enabled during device reset, with the current output drive and reference circuitry disabled. The device is manufactured in a 0.35m advanced CMOS process with Triple Well extension giving improved isolation between analog blocks and digital-analog. A functional block diagram is shown in Figure 1. Clock Buffer CLK CLKB 12 ECL Data In DAC Output DAC ECL Threshold 2 Data Format Bandgap Reference Reset FML Mixed Signal Bandgap Shuffle Control RRef VRef Figure 1 MB86061 Functional Block Diagram 1.1 Operating Modes The DAC core incorporates a number of novel design aspects that are subject to patent applications. Key to its operation are the current sources where segmented, common centroid, interleaved techniques for the most significant bits, as well as load matching ensure good linearity and low distortion to at least the 12-bit level. In the switch elements tracking capacitance is minimised to improve settling, while controlled rise and fall times improve SFDR performance. Finally the digital decoding uses a 3-dimensional addressing approach to minimise propagation delays from latch to element. Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 3 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 1.1.1 Segment Shuffling The DAC core incorporates a proprietary segment shuffling capability which is provided to further improve linearity, and hence improve SFDR. This feature reduces any signal level dependent effects on linearity as the same code can be generated by the same number of MSB cells but taken from any quarter of the MSB segments. Segment shuffling can be selected to operate every 4, 8 or 16 updates of the DAC output using a random shuffle sequence between the four segments A, B, C and D. The effect of segment shuffling is to produce a spread noise spectrum, raising the overall noise floor, but reducing the distortion. For minimum distortion when generating low frequency signals, it is recommended that the shuffling clock rate is no more than 25MHz (FDAC / Segment Shuffling setting). See Table 1. However, low shuffle clock rates give reduced spreading out of distortion components. A B C D Table 1 Segment Shuffling Control Mode SHUF1 SHUF0 Segment Shuffling Note 0 0 0 Segment Shuffling disabled Lowest noise 1 0 1 Random - every 4 cycles FDAC 100 MSa/s 2 1 0 Random - every 8 cycles 100 FDAC 200 MSa/s 3 1 1 Random - every 16 cycles 200 FDAC MSa/s 1.2 Voltage Reference A 1.25V bandgap reference is provided on-chip, although this may be bypassed where an external reference is to be used. To use the internal bandgap reference pins BGAP and VREF should be linked via a 50 resistor, or smaller if better rejection of reference noise is required. VREF should be decoupled to Reference Ground (RVSS) with a 100nF capacitor. For maximum accuracy an external voltage reference is recommended. 1.3 Analog Output The DAC output is a differential current type. A termination resistor should be used appropriate for the maximum allowable output swing. A power down control places the analog circuitry in a low power state, Page 4 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter switching off the current output drive and reference circuitry. When power down mode is selected the device enters its reset state setting the input data code to +1/2 in 2's complement, or 0 in unsigned binary. Table 2 Full Scale Code Representation 2's Complement Code IOUT +2047 0111 1111 1111 : : 0 0000 0000 0000 : : -2048 1.3.1 Unsigned Binary 1000 0000 0000 65 /64.IFS IOUTB 1 /64.IFS 4095 1111 1111 1111 : : : 33 /64.IFS : 1 /64.IFS IOUT /64.IFS : 33 Code : 65 /64.IFS 2048 1000 0000 0000 : : 0 0000 0000 0000 65 /64.IFS IOUTB 1 /64.IFS : 33 /64.IFS : 33 : 1 /64 .IFS /64.IFS : 65 /64.IFS Analog Output Reference Resistor From the voltage reference a control loop defines the current through an external resistor, Rref, where the current in the reference resistor is 4 times the internal segment current, and the full scale output current is defined as, 63 Vref IOP = 63 ------ x -------------------- 16 Iref 64 4 x Rref therefore, 16 x Vref R ref = --------------------I OP e.g. Using a 1.25V Vref., to give a 20mA full scale output => R Ref = 1k 1.3.2 Analog Output Scaling Power savings can be made by reducing the full scale analog output current (IOP) by increasing Rref. However, to maintain the specified performance, IOP should be programmed to 20mA, and the digital data should be pre-scaled to achieve full scale deflection at an output current lower than full scale (IOP). 1.3.3 Analog Output Pins The analog outputs, IOUT and IOUTB, are each connected to two pins to reduce output inductance. These pins should be directly connected together on the PCB. 1.4 Digital Data Interface 12-bit digital data is input through pins D[11:0]. D11 is the MSB. Data may be presented in either Unsigned Binary or 2's Complement format, depending upon the setting of the TWOC pin. See Table 3. Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 5 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter Table 3 Digital Data Format Control Pin Function TWOC Digital Data Format 0 Unsigned Binary 1 2's Complement Note: The Digital Data interface has true ECL inputs. The voltage levels of the input data must not exceed the specifications in section 3.2. 1.5 Power Supplies Separate power and ground supplies are used for the digital data, digital control, analog, reference and clock circuits. A low jitter supply, free from data dependent signals is required by the clock domain. A supply with low clock and data noise is required for the analog domain. The clock, digital control, analog and reference circuitry are all implemented using Fujitsu's Triple-Well extension to the standard CMOS process to provide the necessary electrical isolation. Individual substrate connections are provided to analog, digital control and clock domains. 1.5.1 Substrate Connections Connections to the analog, digital control, and clock block substrates are provided. These pins would typically be directly connected to the main digital ground (VSS), so as to direct any noise that has been collected by the substrates away from the analog blocks. 1.5.2 Power Dissipation The power dissipation, PD, is dependant on specific operating conditions: supply voltage (V DD), full scale output current (IOP), DAC output update rate (FDAC) and input data waveform. Equations for calculating power dissipation are given in section 3.3. Depending on these factors, applications requiring high FDAC frequencies and/or extended lifetime at ambient temperatures >70oC may need additional cooling. 1.6 Reset A RESETB pin is provided, which when taken low allows the device to be reset and placed in a low power state. There is a two cycle latency requiring the device to be clocked in order to reset the device. On power up the device must be reset before it is operational. Configuration changes require a device reset to be performed. Page 6 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 2 Timing Diagrams thi tsl tlo Data CLK tdatasu Data In tdatah DN-1 DN DN+1 to Analog Out DN-3 DN-2 DN-1 Figure 2 Input Data Timing Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 7 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 3 Electrical Specifications 3.1 Absolute Maximum Ratings Ratings Parameter Notes Symbol Units Min. Supply voltage Input voltage Typ. Max. 1 VDD 3.0 3.3 3.6 V 1 VEE -2.2 -2.0 -1.8 V 2 VIL VDD+0.5 V mA VEE -0.2 Output current O TST 3 Storage Temperature V +2 +20 +21 -40 25 +125 o C TOP (min) to TOP(max), VDD = RVDD = AVDD = CVDD = +3.3V, VSS = RVSS = AVSS = CVSS = 0V, VEE = CVEE = -2V, IFS=20mA, Differential Transformer coupled output, 50 doubly terminated, unless otherwise specified. 1. V DD to VEE must not exceed 5.5V max. (beyond which device life maybe impared) 2. IOUT & IOUTB VSS - 1.0 to VDD + 0.5 3. For 1 second per pin (at max.) CAUTION ELECTROSTATIC DISCHARGE SENSITIVE DEVICE High electrostatic charges can accumulate in the human body and discharge without detection. Ensure proper ESD procedures are followed when handling this device. Page 8 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 3.2 Digital Interface Specifications Ratings Parameter Notes Symbol Units Min. Typ. Max. CMOS inputs High-level input voltage VIH 2.3 VDD Low-level input voltage VIL VSS 1.0 V High-level input current IIH -10 +10 A Low-level input current IIL -10 +10 A V 5 Input capacitance pF CMOS outputs High-level output voltage VOH 2.9 VDD V Low-level output voltage VOL VSS 0.4 V ECL inputs VETH VETH - 0.15 -1.3 VETH + 0.15 V High-level input voltage VEIH VETH + 0.15 VETH + 0.45 VDD V Low-level input voltage VEIL VEE VETH - 0.45 VETH - 0.15 V High-level input current IIH -10 +10 A Low-level input current IIL -10 +10 A Input threshold 1 Input capacitance 5 pF Setup time tdatasu -0.2 ns Hold time tdatah 1.2 ns TOP (min) to TOP(max), VDD = RVDD = AVDD = CVDD = +3.3V, VSS = RVSS = AVSS = CVSS = 0V, VEE = CVEE = -2V, IFS=20mA, Differential Transformer coupled output, 50 doubly terminated, unless otherwise specified. 1. Applied to VTH pin. Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 9 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 3.3 DC Specifications Ratings Parameter Notes Symbol Units Min. Typ. Max. DC Accuracy Integral Non Linearity, (Shuffle Off) INL 10 20 LSB12 Differential Non Linearity DNL 5 10 LSB12 Analog output OP 20 mA Output resistance 100 k Output capacitance 15 Full scale output current -1 Gain error -1 Output voltage (compliance) 1 6 to CLK In to Analog Out delay pF +1 %FS V ns Bandgap Reference Reference voltage VBG 1.19 Reference output current IBG 5 VREF 1.19 IBG -1 1.25 1.31 V 20 mA Reference Input Reference voltage Reference input current 1.25 1.31 V +1 A Power Supply VDD, RVDD, AVDD, CVDD 3.0 3.3 3.6 V VEE, CVEE -2.2 -2.0 -1.8 V Power Dissipation PD 100MSa/s input 1 218 mW 300MSa/s input 1 308 mW Maximum power dissipation 352 mW Power down current <1 mA Operating Temperature TOP -40 25 +85 o C TOP (min) to TOP(max), VDD = RVDD = AVDD = CVDD = +3.3V, VSS = RVSS = AVSS = CVSS = 0V, VEE = CVEE = -2V, IFS=20mA, Differential Transformer coupled output, 50 doubly terminated, unless otherwise specified 1. Nominal power dissipation PD = 174 + (44.5 per 100MSa/s) (mW) approx. Page 10 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 3.4 AC Specifications Ratings Parameter Notes Symbol Units Min. Signal to Noise Ratio Typ. Max. SNR Range DC to 50MHz, F DAC = 400 MSa/s 2MHz tone, Segment Shuffling - Off 90 dB 2MHz tone, Segment Shuffling - On 80 dB 2MHz tone, Segment Shuffling - Off 80 dB 2MHz tone, Segment Shuffling - On 90 dB 20MHz tone, Segment Shuffling - Off 65 dB 20MHz tone, Segment Shuffling - On 76 dB 2MHz tone, Segment Shuffling - Off 83 dBc 2MHz tone, Segment Shuffling - On 93 dBc Total Harmonic Distortion THD Range DC to 50MHz Spurious Free Dynamic Range SFDR Single Tone at -1dBFS, F DAC = 200MSa/s, range DC to 100MHz 15MHz tone, Segment Shuffling - Off 15MHz tone, Segment Shuffling - On 70 dBc 79 dBc Spurious tone at 19.5MHz, Segment Shuffling - Off 88 dBFS Spurious tone at 19.5MHz, Segment Shuffling - On 95 dBFS Spurious tones 17.5 - 21.5MHz, Segment Shuffling - Off 89 dBFS Spurious tones 17.5 - 21.5MHz, Segment Shuffling - On 97 dBFS 4-tones at -15dBFS, FDAC = 200MSa/s, range DC to 100MHz 19.1, 19.3, 19.7, & 19.9MHz tones, missing centre tone TOP (min) to TOP(max), VDD = RVDD = AVDD = CVDD = +3.3V, VSS = RVSS = AVSS = CVSS = 0V, VEE = CVEE = -2V, IFS=20mA, Differential Transformer coupled output, 50 doubly terminated, unless otherwise specified Spurious Free Dynamic Range (SFDR) is defined as the highest spurious product (harmonic or non-harmonically related) within a defined bandwidth while generating a test tone or tones (multi-tone test). SFDR varies with amplitude and frequency of the test tone(s) and should either be quoted as the difference between the tone and highest spurious component (dBc) or referenced to full scale (dBFS). In both cases the test tone amplitude and frequency should be quoted as well as the measurement bandwidth. The measurement bandwidth is typically regarded as DC to Nyquist but occasionally systems will specify an appropriate narrow band. Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 11 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 3.5 Clock Specifications Ratings Parameter Notes Symbol Units Min. Typ. Max. Maximum DAC Conversion rate VDD < 3.3V VDD 3.3V FDAC 350 MSa/s 400 MSa/s Clock in ns Low time tLO 1 High time tHI 1 ns Slew rate for minimum wide-band jitter tSL 0.5 V/ns Vcm Common mode input voltage Signal level (differential) 0 VDD - 1.25 100 1 V mV TOP (min) to TOP(max), VDD = RVDD = AVDD = CVDD = +3.3V, VSS = RVSS = AVSS = CVSS = 0V, VEE = CVEE = -2V, IFS=20mA, Differential Transformer coupled output, 50 doubly terminated, unless otherwise specified 1. Ensure that slew rate specifications are observed Page 12 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 3.6 Typical Performance Characterisation Graphs 95 Single Tone Spurious Free Dynamic Range 90 Shuffle On 200MSa/s DAC Rate Amplitude = -1dBFS (dBc) SFDR 85 80 Shuffle Off 75 70 65 60 0 10 20 30 40 Figure 3 Single Tone SFDR Performance Generated Frequency (MHz) 0 Multi-tone test, 4 tones, 200kHz channel spacing, missing centre tone 200MSa/s Input Data Rate Shuffle On 4 Tones each at -15dBFS -20 (dBFS) Amplitude -40 -60 -80 -100 -120 17 18 19 20 21 Generated Frequency 22 Figure 4 Multi-tone Performance (MHz) Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 13 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 4 Application Notes 4.1 Power & Ground Plane Regions The following guidelines are suggested to obtain the specified performance. Any departure from these recommendations should be investigated to confirm that performance in the application is acceptable. The device should be used with at least a four layer PCB utilizing separate power and ground planes. Critical analog signals should be routed on the external layer adjacent to the ground plane, typically layer 1. The power and ground planes should be split to isolate digital, clock, reference and analog regions of the circuitry. These separated regions should be connected at a star point located underneath the device, which should be used as the connection point to the PSU. These regions should only extend as far as necessary, and avoid other sections of the application circuit that could introduce noise. Signal regions such as the Analog out and Clock in can be separated from the remainder of the application circuit by introducing a transformer as an isolator. The connection to the PSU should also be arranged as a star point, with all other sections of the application circuit joined at this point. Tracks to this point should be made as wide as possible, and if they are located in the ground plane layer, should be positioned under static pins. No connection to the supply tracks should be made midway. See Figure 5. DVSS VSS CVSS Application Circuit PSU Star Point Device Star Point AVSS PSU RVSS Figure 5 Power Supply Distribution Through Star Points The DVDD and VDD, and DVSS and VSS pins can be connected to the same region, but normally the Digital supply and ground plane regions should be split further to isolate the Digital control and Digital data blocks. The Digital data region will normally extend into the application circuit, and as such will be subject to significant noise. Page 14 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter Another main reason for splitting the digital data ground plane from the main digital ground is that when using a remote data generator (e.g. a benchtop pattern or data generator) there is a tendency for noise to be injected on the data ground by the equipment. This is significant because the data rate is high, the data bus is wide, and it is correlated with the signal so can cause spurious tones which degrade SFDR. The coupling mechanism is from the fast-slewing data inputs via the capacitance of the input pins/pads/ protection diodes into the internal circuits. The transient currents through these parasitics can be several hundred milliamps. For this reason, it is recommended that this region is not connected to the device star point but to the PSU star point directly. The input data bus and supplies are only used for the input section of the device, so noise in this region cannot couple into the DAC core. The main digital supply connects to the digital circuits inside the DAC, including those inside the DAC core. The control inputs can use this supply because they toggle more slowly (if at all) and are not correlated with the data. The analog sections (Analog, Clock and Reference) have separate supply connections as transition dependant currents from the digital sections will cause delay modulation in the clock path, and amplitude modulation in the analog output section. Each supply should be decoupled, producing a low impedance shunt at high frequency. The Digital, Analog, Clock and Reference sections can be connected directly to the device star point, but preferably through a small inductor. If a fully split power (VDD) plane is not desired, then as a minimum only the ground plane need be split as described. However it is very important to isolate the I/O supply (DVDD) from all other supplies in some way, possibly feeding the supply through a low-R resistor or ferrite bead. This will help to filter out noise. If the data (signal) and control lines are coming from the same device (e.g. an ASIC), then generally this would have been designed to support separate supply and ground pins for the digital data bus anyway. The ground plane at the generating device then becomes the "star point" for the data, requiring cuts in the ground/supply planes on either side of the data bus, and looping under the DAC. The digital data decoupling at the DAC should also be inside this loop. This gives a "U" shaped cut in the planes with the open end at the data source (with decoupling) and the closed end at the DAC (with decoupling). All the data return currents will then be confined inside this "U", and so none of them can couple into the analog ground planes to degrade SFDR. It may be advisable to bury the digital data bus tracks on an internal layer, with data ground planes above, below and either side of the tracks (the ground layers connected together with a row of vias) to shield against RF radiation. Figure 6 shows these principles applied to the ground plane of an application board. The pad on the left represents the PSU star point, and the pad in the center represents the device star point. These points could be realized with a via, so that the connection from the PSU out to other star points could be made on another layer if necessary. The positioning of the plane breaks are also shown. The breaks in the planes between each section should mark the boundary of that section. It is very important to ensure that there are no tracks crossing these boundaries, or any splits in the planes that tracks must cross, as this will create current loops within the plane itself. The power supply track regions, PSU and Opt. PSU are shown extending to either side of the device for reference purposes. Only one track region would normally be used. If the PSU region is not required, then the region should be merged with the Digital region. Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 15 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter PS U region D0 VTH VSS VDD TWOC N/C VSS VDD DSUB ASUB SHUF0 SHUF1 RVSS BGAP VREF RREF D6 DVSS D7 D8 DVDD D9 VEE D1 VEE D2 DVSS D3 D4 DVDD D5 VEE D igital D ata region D10 D11 VSS VDD N/C N/C VSS VDD DSUB CSUB RESETB CVDD CVSS CLK CVEE CLKB D igital region Opt. PSU region RVSS RVDD AVDD AVSS IOUTB IOUTB AVSS AVDD AVDD AVSS IOUT IOUT AVSS AVDD CVDD CVSS Pin #1 A nalog region R ef. R egion C lock region Application region Figure 6 Recommended Ground Plane Splits 4.2 Power Supplies Only one clean low-impedance power supply is required. Power distribution should be organized as shown in Figure 5, with a main star point at the PSU supplying the data (DVDD/DVSS) block, with a secondary device star point supplying the Digital, Analog, Clock and Reference blocks. If this supply is used to supply any other circuits, they must not introduce any modulation onto the supply, or SFDR will be degraded. If the impedance of the supply is not low enough to prevent modulation by the currents drawn by the data block, then a separate supply for the Data block should be used. If the Digital, Analog, Clock and Reference block supply is still not low enough impedance to prevent power supply modulation being introduced by the Digital block, then a further supply for the Analog block alone must be introduced. Bulk decoupling of around 100uF at the power supply star point is recommended to remove any low frequency ripple. Smaller value decoupling of around 0.1 to 1uF at the device star point is recommended to apply a low impedance shunt at high frequency. Page 16 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter Power supply tracks should be kept as short and wide as possible. The ground and supply tracks should run adjacent to each other for as far as possible, whilst avoiding all signal tracks that may couple noise into the supply. 4.3 Decoupling D6 DVSS D7 D8 DVDD D9 VEE VEE D2 DVSS D3 D4 DVDD D5 VEE D1 All supplies and references should be decoupled to the appropriate ground plane using surface mount 100nF capacitors, placed as close as possible to the device. For each pair of VDD/VSS pins it is recommended that the capacitor is located on the reverse of the PCB, immediately under the device, with vias to the supply and ground planes as close as physically possible to the device and capacitor. This layout minimizes the total length of track, including the plated through hole, and hence keeps loop inductance to a minimum. An example of the recommended layout, using 0603 format surface mount capacitors and a four layer PCB is illustrated in Figure 7. DVSS D0 VTH VSS VDD TWOC N/C VSS VDD DSUB ASUB SHUF0 SHUF1 RVSS BGAP VREF RREF DVSS DVSS Layer 1 pads D10 D11 VSS VDD N/C N/C VSS VDD DSUB CSUB RESETB CVDD CVSS CLK CVEE CLKB Layer 4 pads AVSS AVDD CVDD CVSS AVDD AVDD AVSS IOUT IOUT AVDD AVSS IOUTB IOUTB AVSS RVSS RVDD Pin #1 N.B. Not to scale. All vias connect to the appropriate Ground or Power plane. Figure 7 Recommended Supply Decoupling Layout Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 17 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 4.4 Analog Output To provide a differential analog output which is both isolated form the analog ground plane, and which gives good common mode rejection, a two stage transformer circuit can be used. The recommended devices are Mini-Circuits (http://www.minicircuits.com) ADTT1-1, 1:1 transformer, and ADTL1-12 transmission line transformer. The primary of the ADTL1-12 is connected to IOUT and IOUTB, (terminated as shown in Figure 8) and the secondary is connected to the ends of the secondary of the ADTT1-1. The center tapping of the secondary of the ADTT1-1 will be linked to the analog ground plane. The primary of the ADTT1-1 will be terminated as required by the application circuit. See Figure 8. For optimum performance the transformer should be positioned as close to the device as physically possible, and should be connected to the analog output pins IOUT and IOUTB with 50 tracks. The connections to the analog ground plane should be made through the same vias as the decoupling capacitors, which are shown in Figure 7 as being on the outside of the device pad pattern, so that the track length and hence loop inductance can be kept to a minimum. IO UT ADTT1-1 50 50 ADTL1-12 100 AVS S AGND 50 Analog out 22pF IO U TB AGND MB86061 0.1% Precision resistors Figure 8 Analog Out Transformer Coupling 4.5 Clock Input The clock input can be connected in a number of ways, depending on the clock source used. For optimum performance the MB86061 should have ground plane isolation from the source by the use of a coupling transformer. An ECL level differential clock generator can be directly connected to the CLK and CLKB pins, and connected to the same ground plane as long as it is a low noise source. The ECL buffer should be terminated to the -2V supply plane region with 50 resistors, and AC coupled with 100nF capacitors. The PCB tracks should be 50 tracks. See Figure 9a. If a common, system wide logic level clock source is to be used, this should be transformer coupled to remove common mode noise and isolate the clock ground plane region. The recommended 1:1 transformer Page 18 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter is a Mini-Circuits, ADT1-1. The secondary will be connected to the differential clock inputs CLK and CLKB, and terminated with a 100 resistor. The PCB tracks to the device should be 50 tracks. The primary of the transformer will be connected between the digital clock source and the digital clock source ground. A 100 source resistor is used, and the PCB tracks to the clock source should be 100 . See Figure 9b. For connection to a low noise RF source, a transmission-line transformer should be used. The recommended transformer is a Mini-Circuits ADTL1-12. The secondary terminals should be connected through a 100nF capacitor to the differential clock inputs CLK and CLKB. The clock inputs should be terminated with a 50 resistor. The primary dot should be connected to the RF signal with a 50 PCB track, and the other primary connection should be connected to RF ground. The primary ground may be connected to clock ground if necessary. See Figure 9c. This configuration would allow for a RF signal level of between -6dBm and +24dBm, giving a differential signal level of up to 5V pk-pk at CLK and CLKB. 100nF CLK CLK EC L Buffer MB86061 CLKB CGND CLKB 50 50 100nF -2V Supply A: Using an ECL buffered differential clock source 100nF ADTT1-1 CLK 100 S ystem clock 100 MB86061 R F Source CLK ADTL1-12 50 CLKB System Ground CLK B 100nF RF Ground B: Using a common system clock source MB86061 C: Using an RF source Figure 9 Clock Input Configurations Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 19 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 5.1 Pin Assignment VEE D2 DVSS D3 D4 DVDD D5 VEE Pin Description D1 5 D0 VTH VSS VDD TWOC N/C VSS VDD DSUB ASUB SHUF0 SHUF1 RVSS BGAP VREF RREF D6 DVSS D7 D8 DVDD D9 VEE MB86061 12-Bit 400MSa/s Digital to Analog Converter D10 D11 VSS VDD N/C N/C VSS VDD DSUB CSUB RESETB CVDD CVSS CLK CVEE CLKB MB86061 Page 20 of 26 AVDD AVDD AVSS IOUT IOUT AVSS AVDD CVDD CVSS AVDD AVSS IOUTB IOUTB AVSS RVDD RVSS Pin #1 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 5.2 Pin Definition Digital Interface Pin No. Pin Name Input/ Output 31, 32, 34, 36, 37, 39, D[11:0] I 41, 43, 44, 46, 48, 49 Description Input data [MSB = D11] Connect unused inputs to VEE via a 50 resistor 50 VTH - Data interface voltage threshold, -1.3V 35, 42 DVDD - Data interface supply, +3.3V 38, 45 DVSS - Data interface ground, 0V 33, 40, 47 VEE - Data interface supply, -2V Pin No. Pin Name Input/ Output 59, 60 SHUF[0:1] I Segment Shuffling control. See Table 1 53 TWOC I Input data format selection, `1' = 2's Complement Digital & Control Description 22 RESETB I Device reset ='0' 27, 28, 54 N/C - No connection. Do not connect 25, 29, 52, 56 VDD - Digital supply, +3.3V 26, 30, 51, 55 VSS - Digital ground, 0V 24, 57 DSUB - Digital substrate. Link to VSS Control lines should be linked to VDD or VSS according to the function setting required Clock Input/ Output Description Pin No. Pin Name 17, 19 CLKB, CLK I Differential input clock 15, 21 CVDD - Clock supply, +3.3V 16, 20 CVSS - Clock ground, 0V 18 CVEE - Clock supply, -2V 23 CSUB - Clock substrate. Link to VSS Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 21 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter Analog Pin No. Pin Name Input/ Output Description 5, 6 IOUTB O DAC output (inverting) 11, 12 IOUT O DAC output (non-inverting) 3, 8, 9, 14 AVDD - Analog supply, +3.3V 4, 7, 10, 13 AVSS - Analog ground, 0V 58 ASUB - Analog substrate. Link to VSS Pin No. Pin Name Input/ Output 62 BGAP O Reference Description Bandgap reference 63 VREF I Voltage reference input 64 RREF O Output reference resistor. See section 1.3.1 2 RVDD - Reference supply, +3.3V 1, 61 RVSS - Reference ground, 0V Page 22 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 5.3 Package Data 14.000.20(.551.008)SQ 48 33 12.000.10(.472.004)SQ +0.20 1.50 -0.10 +.008 .059 -.004 (Mounting height) 32 49 9.75 (.384) REF 13.00 (.512) NOM 1 PIN INDEX 64 17 LEAD No. 1 0.65(.0256)TYP Details of "A" part 16 0.300.10 (.012.004) "A" 0.13(.005) M +0.05 0.127 -0.02 0.100.10 (STAND OFF) (.004.004) +.002 .005 -.001 0.10(.004) 0 C 10 0.500.20 (.020.008) 1994 FUJITSU LIMITED F64018S-1C-2 All dimensions in millimetres (inches) 5.3.1 Thermal Characteristics * JA = 65oC/W, JC = 15 oC/W Figures assume mounting on a 4-layer pcb mounted in free air. 5.4 Ordering Information The following reference should be used when ordering devices, * MB86061PFQ For further assistance please contact your sales representative. Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 23 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter 6 Development Kit A development kit, reference DK86061, is available for the MB86061 12-Bit 400MSa/s Digital to Analog Converter. The kit includes an evaluation board that enables simple and effective evaluation of the device. The board provides a complete evaluation environment for the DAC. A transformer coupled differential output interface is provided to simplify integration into target applications and development environments. An RF clock source can be connected via the transformer coupled input, and 12-bit data via a 40-way IDC header. The development kit includes, * Evaluation board with MB86061 device fitted * Spare MB86061 for customer development * User Manual For further assistance, including price and delivery of the development kit, please contact your sales representative. Page 24 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter Notes: Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH Page 25 of 26 January 2000 Version 1.0 FME/MS/SFDAC1E/DS/4271 MB86061 12-Bit 400MSa/s Digital to Analog Converter Worldwide Headquarters Japan Fujitsu Limited Asia Fujitsu Microelectronics Asia Pte Limited Tel: +81 44 754 3753 Fax: +81 44 754 3329 1015 Kamikodanaka 4-1-1 Nakahara-ku Kawasaki-shi Kanagawa-ken 211-88 Japan Tel: Fax: 151 Lorong Chuan #05-08 New Tech Park Singapore 556741 http://www.fujitsu.co.jp/ +65 281 0770 +65 281 0220 http://www.fmap.com.sg/ USA Fujitsu Microelectronics Inc Europe Fujitsu Microlectronics Europe GmbH Tel: +1 408 922 9000 Fax: +1 408 922 9179 3545 North First Street San Jose CA 95134-1804 USA Tel: +49 6103 6900 Fax: +49 6103 690122 Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: +1 800 866 8608 Fax: +1 408 922 9179 Customer Response Center Mon-Fri: 7am-5pm (PST) http://www.fujitsu-fme.com/ http://www.fujitsumicro.com/ The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such ailures f by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. FME/MS/SFDAC1E/DS/4271 - 1.0 Page 26 of 26 Copyright (c) 2000 Fujitsu Microelectronics Europe GmbH