M48T35AV 3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER(R) SRAM Features Integrated, ultra low power SRAM, real-time clock, power-fail control circuit and battery BYTEWIDETM RAM-like clock access BCD coded year, month, day, date, hours, minutes, and seconds Battery low flag (BOK) Frequency test output for real-time clock Automatic power-fail chip deselect and WRITE protection WRITE protect voltage (VPFD = power-fail deselect voltage): - M48T35AV: VCC = 3.0 to 3.6 V; 2.7 V VPFD 3.0 V 1 PCDIP28 battery/crystal CAPHATTM SNAPHAT(R) battery/crystal Self-contained battery and crystal in the CAPHATTM DIP package SOIC package provides direct connection for a SNAPHAT(R) housing containing the battery and crystal SNAPHAT(R) housing (battery and crystal) is replaceable Pin and function compatible with JEDEC standard 32 Kbit x 8 SRAMs RoHS compliant - Lead-free second level interconnect June 2011 28 28 1 SOH28 Doc ID 6845 Rev 9 1/29 www.st.com 1 Contents M48T35AV Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/29 Doc ID 6845 Rev 9 M48T35AV List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PCDIP28 - 28-pin plastic DIP, battery CAPHATTM, pack. mech. data . . . . . . . . . . . . . . . . 22 SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT(R), pack. mech. data. . 23 SH - 4-pin SNAPHAT(R) housing for 48 mAh battery & crystal, pack. mech. data . . . . . . . 24 SH - 4-pin SNAPHAT(R) housing for 120 mAh battery & crystal, pack. mech. data . . . . . . 25 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SNAPHAT(R) battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Doc ID 6845 Rev 9 3/29 List of figures M48T35AV List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. 4/29 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PCDIP28 - 28-pin plastic DIP, battery CAPHATTM, package outline . . . . . . . . . . . . . . . . . 22 SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT(R), package outline . . . 23 SH - 4-pin SNAPHAT(R) housing for 48 mAh battery & crystal, pack. outline . . . . . . . . . . . 24 SH - 4-pin SNAPHAT(R) housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . 25 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 6845 Rev 9 M48T35AV 1 Description Description The M48T35AV TIMEKEEPER(R) RAM is a 32 Kbit x 8 non-volatile static RAM and real-time clock. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution. The M48T35AV is a non-volatile pin and function equivalent to any JEDEC standard 32 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600 mil DIP CAPHATTM houses the M48T35AV silicon with a quartz crystal and a long-life lithium button cell in a single package. The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT(R) housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery/crystal package part numbers are M4T28-BR12SH1 (48 mAh lithium battery SNAPHAT), M4T32-BR12SH1 (120 mAh lithium battery SNAPHAT), and M4T32-BR12SH6 (120 mAh lithium battery SNAPHAT, -40 to +85 C crystal). Figure 1. Logic diagram VCC 15 8 A0-A14 DQ0-DQ7 W M48T35AV E G VSS Doc ID 6845 Rev 9 AI02797B 5/29 Description M48T35AV Table 1. Signal names A0-A14 Address inputs DQ0-DQ7 Data inputs / outputs E Chip enable G Output enable W WRITE enable VCC Supply voltage VSS Ground Figure 2. DIP connections A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48T35AV 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI02798B Figure 3. SOIC connections A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48T35AV 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI02799 6/29 Doc ID 6845 Rev 9 M48T35AV Figure 4. Description Block diagram OSCILLATOR AND CLOCK CHAIN 8 x 8 BiPORT SRAM ARRAY 32,768 Hz CRYSTAL A0-A14 POWER 32,760 x 8 SRAM ARRAY LITHIUM CELL DQ0-DQ7 E VOLTAGE SENSE AND SWITCHING CIRCUITRY W VPFD VCC G VSS Doc ID 6845 Rev 9 AI01623 7/29 Operation modes 2 M48T35AV Operation modes As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the M48T35AV are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 7FF8h-7FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM READ/WRITE memory cells. The M48T35AV includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T35AV also has its own power-fail detect circuit. The control circuitry constantly monitors the single 3 V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the battery backup switchover voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2. Operating modes Mode VCC E Deselect WRITE READ 3.0 to 3.6 V READ Deselect VSO to VPFD Deselect (min)(1) VSO(1) G W DQ0-DQ7 Power VIH X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active X X X High Z CMOS standby X X X High Z Battery backup mode 1. See Table 11 on page 21 for details. Note: X = VIH or VIL; VSO = Battery backup switchover voltage. 2.1 READ mode The M48T35AV is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the 15 address inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (tELQV) or output enable access time (tGLQV). 8/29 Doc ID 6845 Rev 9 M48T35AV Operation modes The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. Figure 5. READ mode AC waveforms tAVAV VALID A0-A14 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI00925 Note: WRITE enable (W) = High. Table 3. READ mode AC characteristics M48T35AV Symbol Parameter(1) -100 Min Unit Max tAVAV READ cycle time tAVQV Address valid to output valid 100 ns tELQV Chip enable low to output valid 100 ns tGLQV Output enable low to output valid 50 ns tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX 100 ns Chip enable low to output transition 10 ns Output enable low to output transition 5 ns Chip enable high to output Hi-Z 50 ns Output enable high to output Hi-Z 40 ns Address transition to output transition 10 ns 1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 3.0 to 3.6 V (except where noted). 2. CL = 5 pF. Doc ID 6845 Rev 9 9/29 Operation modes 2.2 M48T35AV WRITE mode The M48T35AV is in the WRITE mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 6. WRITE enable controlled, WRITE mode AC waveform tAVAV VALID A0-A14 tAVWH tAVEL tWHAX E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI00926 Figure 7. Chip enable controlled, WRITE mode AC waveforms tAVAV A0-A14 VALID tAVEH tELEH tAVEL tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI00927 10/29 Doc ID 6845 Rev 9 M48T35AV Operation modes Table 4. WRITE mode AC characteristics M48T35AV Parameter(1) Symbol Unit Min Max tAVAV WRITE cycle time 100 ns tAVWL Address valid to WRITE enable low 0 ns tAVEL Address valid to chip enable low 0 ns tWLWH WRITE enable pulse width 80 ns tELEH Chip enable low to chip enable high 80 ns tWHAX WRITE enable high to address transition 10 ns tEHAX Chip enable high to address transition 10 ns tDVWH Input valid to WRITE enable high 50 ns tDVEH Input valid to chip enable high 50 ns tWHDX WRITE enable high to input transition 5 ns tEHDX Chip enable high to input transition 5 ns tWLQZ(2)(3) WRITE enable low to output Hi-Z 50 ns tAVWH Address valid to WRITE enable high 80 ns tAVEH Address valid to chip enable high 80 ns WRITE enable high to output transition 10 ns tWHQX(2)(3) 1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 3.0 to 3.6 V (except where noted). 2. CL = 5 pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 2.3 Data retention mode With valid VCC applied, the M48T35AV operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window (see Figure 13, Table 10, and Table 11 on page 21). All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T35AV may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T35AV for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to processor stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). Doc ID 6845 Rev 9 11/29 Operation modes M48T35AV Also, as VCC rises, the battery voltage is checked. If the voltage is less than approximately 2.5 V, an internal battery not OK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 8 illustrates how a BOK check routine could be structured. For more information on battery storage life refer to the application note AN1012. Figure 8. Checking the BOK flag status POWER-UP READ DATA AT ANY ADDRESS WRITE DATA COMPLEMENT BACK TO SAME ADDRESS READ DATA AT SAME ADDRESS AGAIN IS DATA COMPLEMENT OF FIRST READ? (BATTERY OK) YES NO (BATTERY LOW) NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED) WRITE ORIGINAL DATA BACK TO SAME ADDRESS CONTINUE AI00607 12/29 Doc ID 6845 Rev 9 M48T35AV Clock operations 3 Clock operations 3.1 Reading the clock Updates to the TIMEKEEPER(R) registers (see Table 5) should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the control register 7FF8h. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' 3.2 Setting the clock Bit D7 of the control register 7FF8h is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER(R) registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (seeTable 5). Resetting the WRITE bit to a '0' then transfers the values of all time registers 7FF9h-7FFFh to the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. After the WRITE bit is reset, the next clock update will occur within one second. See the application note AN923, "TIMEKEEPER(R) rolling into the 21st century" for information on century rollover. 3.3 Stopping and starting the oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T35AV is shipped from STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T35AV oscillator starts within 1 second. Doc ID 6845 Rev 9 13/29 Clock operations Table 5. M48T35AV Register map Data Address D7 D6 7FFEh 0 0 0 7FFDh 0 0 10 date 7FFCh 0 FT 7FFBh 0 0 7FFAh 0 7FF9h ST 7FF8h W 7FFFh D5 D4 D3 D2 10 years D1 D0 Function/range BCD format Year Year 00-99 Month Month 01-12 Date Date 01-31 Century/day 00-01/01-07 Hours Hours 00-23 10 minutes Minutes Minutes 00-59 10 seconds Seconds Seconds 00-59 10 M. CEB CB 0 Day 10 hours R S Calibration Control Keys: S = SIGN bit FT = FREQUENCY TEST bit (must be set to '0' upon power for normal operation) R = READ bit W = WRITE bit ST = STOP bit 0 = Must be set to '0' CEB = CENTURY ENABLE bit CB = CENTURY bit Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0,' CB will not toggle. The WRITE bit does not need to be set to write to CEB. 3.4 Calibrating the clock The M48T35AV is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T35AV improves to better than +1/-2 ppm at 25C. The oscillation rate of any crystal changes with temperature (see Figure 9 on page 16). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome "trim" capacitors. The M48T35AV design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 10 on page 16. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits (D4-D0) in the control register 7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the SIGN bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration 14/29 Doc ID 6845 Rev 9 M48T35AV Clock operations occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T35AV may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the FREQUENCY TEST (FT) bit, the seventh-most significant bit in the day register is set to a '1,' and D7 of the seconds register is a '0' (oscillator running), DQ0 will toggle at 512 Hz during a READ of the seconds register. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (WR001010) to be loaded into the calibration byte for correction. Note: Setting or changing the calibration byte does not affect the frequency test output frequency. The FT bit MUST be reset to '0' for normal clock operations to resume. The FT bit is automatically reset on power-down. For more information on calibration, see application note AN934, "TIMEKEEPER(R) Calibration." 3.5 Century bit Bit D5 and D4 of clock register 7FFCh contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Note: The WRITE bit must be set in order to write to the CENTURY bit. Doc ID 6845 Rev 9 15/29 Clock operations M48T35AV Figure 9. Crystal accuracy across temperature ppm 20 0 -20 -40 F = -0.038 ppm (T - T )2 10% 0 F C2 -60 T0 = 25 C -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C AI02124 Figure 10. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 16/29 Doc ID 6845 Rev 9 M48T35AV 3.6 Clock operations VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A bypass capacitor value of 0.1 F (as shown in Figure 11) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 11. Supply voltage protection VCC VCC 0.1F DEVICE VSS AI02169 Doc ID 6845 Rev 9 17/29 Maximum ratings 4 M48T35AV Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol TA TSTG Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) TSLD(1)(2)(3) Lead solder temperature for 10 seconds Value Unit 0 to 70 C -40 to 85 C 260 C VIO Input or output voltages -0.3 to 4.6 V VCC Supply voltage -0.3 to 4.6 V IO Output current 20 mA PD Power dissipation 1 W 1. For DIP package, soldering temperature of the IC leads is to not exceed 260 C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. 2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal. 3. For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 C (the time above 255 C must not exceed 30 seconds). Caution: Negative undershoots below -0.3 V are not allowed on any pin while in the battery backup mode. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT(R) sockets. 18/29 Doc ID 6845 Rev 9 M48T35AV 5 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions Parameter Supply voltage (VCC) Ambient operating temperature (TA) Unit 3.0 to 3.6 V 0 to 70 C Load capacitance (CL) 50 pF Input rise and fall times 5 ns 0 to 3 V 1.5 V Input pulse voltages Input and output timing ref. voltages Note: M48T35AV Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC measurement load circuit DEVICE UNDER TEST CL = 50pF (or 5pF) 1.75V CL includes JIG capacitance Table 8. Capacitance Parameter(1)(2) Symbol CIN COUT(3) AI02586 Min Max Unit Input capacitance - 10 pF Output capacitance - 10 pF 1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25 C, f = 1 MHz. 3. Outputs deselected. Doc ID 6845 Rev 9 19/29 DC and AC parameters Table 9. M48T35AV DC characteristics Symbol M48T35AV Test condition(1) Parameter Unit Min ILI ILO(2) Input leakage current Output leakage current ICC Supply current ICC1 Supply current (standby) TTL ICC2 Supply current (standby) CMOS (3) Max 0 V VIN VCC 1 A 0 V VOUT VCC 1 A Outputs open 30 mA E = VIH 2 mA E = VCC - 0.2 V 2 mA Input low voltage -0.3 0.8 V VIH Input high voltage 2.2 VCC + 0.3 V VOL Output low voltage IOL = 2.1 mA 0.4 V VOH Output high voltage IOH = -1 mA VIL 2.4 V 1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 3.0 to 3.6 V (except where noted). 2. Outputs deselected. 3. Negative spikes of -1 V allowed for up to 10 ns once per cycle. Figure 13. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tR tFB tDR tPD INPUTS tRB RECOGNIZED trec DON'T CARE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI01168C 20/29 Doc ID 6845 Rev 9 M48T35AV Table 10. DC and AC parameters Power down/up AC characteristics Parameter(1) Symbol tPD E or W at VIH before power down tF(2) tFB(3) Min Max Unit 0 s VPFD (max) to VPFD (min) VCC fall time 300 s VPFD (min) to VSS VCC fall time 150 s tR VPFD (min) to VPFD (max) VCC rise time 10 s tRB VSS to VPFD (min) VCC rise time 1 s trec VPFD (max) to inputs recognized 40 200 ms 1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 11. Power down/up trip points DC characteristics Parameter(1)(2) Symbol VPFD Power-fail deselect voltage VSO Battery backup switchover voltage tDR(3) Expected data retention time Min Typ Max Unit 2.7 2.9 3.0 V VPFD -100mV 10(4) V Years 1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. All voltages referenced to VSS. 3. At 25 C, VCC = 0 V. 4. CAPHATTM and M4T32-BR12SH1 SNAPHAT(R) only, M4T28-BR12SH1 SNAPHAT(R) top tDR = 7 years (typ). Doc ID 6845 Rev 9 21/29 Package mechanical data 6 M48T35AV Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 14. PCDIP28 - 28-pin plastic DIP, battery CAPHATTM, package outline A2 A1 B1 B A L C e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 12. PCDIP28 - 28-pin plastic DIP, battery CAPHATTM, pack. mech. data mm inches Symb Typ Min Max A 8.89 A1 Min Max 9.65 0.350 0.380 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 22/29 33.02 Typ 1.3 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 28 Doc ID 6845 Rev 9 28 M48T35AV Package mechanical data Figure 15. SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT(R), package outline A2 A C B eB e CP D N E H A1 L 1 SOH-A Note: Drawing is not to scale. Table 13. SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT(R), pack. mech. data mm inches Symb Typ Min A Max Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 - - - - eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 a 0 8 0 8 N 28 e CP 1.27 0.050 28 0.10 Doc ID 6845 Rev 9 0.004 23/29 Package mechanical data M48T35AV Figure 16. SH - 4-pin SNAPHAT(R) housing for 48 mAh battery & crystal, pack. outline A1 A2 A3 A eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 14. SH - 4-pin SNAPHAT(R) housing for 48 mAh battery & crystal, pack. mech. data mm inches Symb Typ Min A Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 24/29 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 Doc ID 6845 Rev 9 M48T35AV Package mechanical data Figure 17. SH - 4-pin SNAPHAT(R) housing for 120 mAh battery & crystal, pack. outline A1 A2 A3 A eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 15. SH - 4-pin SNAPHAT(R) housing for 120 mAh battery & crystal, pack. mech. data mm inches Symb Typ Min A Max Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 Doc ID 6845 Rev 9 25/29 Part numbering 7 M48T35AV Part numbering Table 16. Ordering information scheme Example: M48T 35AV -10 MH 1 E Device type M48T Supply voltage and write protect voltage 35AV = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.0 V Speed -10 = 100 ns (35AV) Package PC = PCDIP28 MH(1) = SOH28 Temperature range 1 = 0 to 70C Shipping method For SOH28: E = Lead-free package (ECOPACK(R)), tubes F = Lead-free package (ECOPACK(R)), tape & reel For PCDIP28: blank = tubes 1. The SOIC package (SOH28) requires the SNAPHAT(R) battery package which is ordered separately under the part number "M4TXX-BR12SHx" in plastic tubes (see Table 17). Caution: Do not place the SNAPHAT(R) battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 17. 26/29 SNAPHAT(R) battery table Part number Description Package M4T28-BR12SH1 M4T32-BR12SH1 M4T32-BR12SH6 Lithium battery (48 mAh) SNAPHAT(R) Lithium battery (120 mAh) SNAPHAT(R) Lithium battery (120 mAh) SNAPHAT(R), -40 to +85 C crystal SH SH SH Doc ID 6845 Rev 9 M48T35AV 8 Environmental information Environmental information Figure 18. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Doc ID 6845 Rev 9 27/29 Revision history 9 M48T35AV Revision history Table 18. 28/29 Document revision history Date Revision Changes Nov-1999 1 First issue From preliminary data to datasheet 21-Apr-2000 2 29-May-2000 2.1 20-Jul-2001 3 20-May-2002 3.1 31-Mar-2003 4 v2.2 template applied; data retention condition updated (Table 11) 01-Apr-2004 5 Reformatted; updated with lead-free package information (Table 6, 16) 21-Nov-2007 6 Reformatted document; added lead-free second level interconnect information to cover page and Section 6: Package mechanical data, updated Table 16, 17; removed M48T35AY and all references. 23-Mar-2009 7 Updated Table 6, Section 6: Package mechanical data; added Section 8: Environmental information; minor formatting changes. 21-Oct-2010 8 Updated Section 4, Table 12; reformatted document. 24-Jun-2011 9 Updated footnote 1 of Table 6: Absolute maximum ratings; updated Features and Section 8: Environmental information. tFB change (Table 10) Reformatted; temp./voltage info. added to tables (Table 8, 9, 3, 4, 10, 11); add century bit text Modify reflow time and temperature footnotes (Table 6) Doc ID 6845 Rev 9 M48T35AV Please Read Carefully: Information in this document is provided solely in connection with ST products. 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