2ED020I06-FI - Infineon Technologies AG

2ED020I06-FI

Dual IGBT Driver IC

Power Managment & Drives

Datasheet, April 2010

Never stop thinking.

April 2010

Edition 2010-04-20

Published by Infineon Technologies AG,

Am Campeon 1-12,

D-85579 Neubiberg

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2ED020I06-FI

Revision History: 2010-04-20 Datasheet

Previous Version:

Page Subjects (major changes since last revision)

Type Ordering Code Package Packaging

2ED020I06-FI PG-DSO-18-2 Tape&Reel

2ED020I06-FI

Datasheet 3 April 2010

PG-DS O-18-2

Dual IGBT Driver IC

2ED020I06-FI

Product Highlights

• Fully opera tional to ±650V

• Power supply operating range from 14 to 18 V

• Gate drive currents of +1 A / –2 A

• Matched propagation delay for both channels

• High dV/dt immunity

• Low power consumption

Features

• Floating high side driver

• Undervoltage lockout for both channels

•3.3 V and 5 V TTL compatible inputs

• CMOS Schmitt-triggered inputs with pull-down

• Non-inverting inputs

• Interlocking inputs

• Dedicated shutdown input with pull-up

• RoHS compliant

High and Low Side Driver

2ED020I06-FI

Overview

Datasheet 4 April 2010

1 Overview

The 2ED020I06-FI is a high voltage, high speed power MOSFET and IGBT driver with

interlocking high and low side referenced outputs. The floating high side driver may be supplied

directly or by means of a bootstrap diode and capacitor. In addition to the logic input of each

driver the 2ED020I06-FI is equipped with a dedicated shutdown input. All logic inputs are

compatible with 3.3 V and 5 V TTL. The output drivers feature a high pulse current buffer stage

designed for minimum driver cross-conduction. Propagation delays are matched to simplify use

in high frequency applications. Both drivers are designed to drive an N-channel power MOSFET

or IGBT which operate up to 650V.

High and Low Side Driver

2ED020I06-FI

Pin Configuration and Functionality

Datasheet 5 April 2010

2 Pin Configuration and Functionality

2.1 Pin Configuration

VSH

GNDH

OutL

VSL

P-DSO-18-2 (300 mil)

2ED020I06-FI

GND

OutHInL

InH

GNDH

GNDL

GND

Figure 1 Pin Configuration (top view)

2.2 Pin Definitions and Functions

Pin Symbol Function

1InH Logic input for high side driver

2InL Logic input for low side driver

3SD Logic input for shutdown of both drivers

4GND Common ground

5GND Connect to GND

6GND Connect to GND

7GND Connect to GND

8n.c. Do not connect, Pin must stay open

Table 1Pin Description

High and Low Side Driver

2ED020I06-FI

Pin Configuration and Functionality

Datasheet 6 April 2010

9GND Connect to GND

10 GND Connect to GND

11 GNDL Low side power ground 1)

12 OutL Low side gate driver output

13 VSL Low side supply voltage

14 n.c. (not connected)

15 n.e. (not existing)

16 n.e. (not existing)

17 GNDH High side (power) ground

18 VSH High side supply voltage

19 OutH High side gate driver output

20 GNDH High side (power) ground

1) Please note : GNDL has to be connected directly to GND

Pin Symbol Function

Table 1 Pin Description (cont’d)

High and Low Side Driver

2ED020I06-FI

Block Diagram

Datasheet 7 April 2010

3Block Diagram

Low Side

High Side

InH

Input

Logic

RX Logic

UVLO

Voltage

Supply

UVLO

Voltage

Supply

CLT

InL

GND

VSH

OutH

GNDH

OutL

VSL

2ED020I06-FI

GNDL

+5V

Figure 2 Block Diagram

High and Low Side Driver

2ED020I06-FI

Functional Description

Datasheet 8 April 2010

4 Functional Description

4.1 Power Supply

The power supply of both sides, “VSL” and “VSH”, is monitored by an undervoltage lockout

block (UVLO) which enables operation of the corresponding side when the supply voltage

reaches the “on” threshold. Afterwards the internal voltage reference and the biasing circuit are

enabled. When the supply voltage (VSL, VSH) drops below the “off” threshold, the circuit is

disabled.

4.2 Logic Inputs

The logic inputs InH, InL and SD are fed into Schmitt-Triggers with thresholds compatible to

3.3V and 5V TTL. When SD is enabled (low), InH and InL are disabled. If InH is high (while InL

is low), OutH is enabled and vice versa. However, if both signals are high, they are internally

disabled until one of them gets low again. This is due to the interlocking logic of the device. See

Figure 3 (section 4.7).

4.3 Gate Driver

2ED020I06-FI features two hard-switching gate drivers with N-channel output stages capable to

source 1A and to sink 2A peak current. Both drivers are equipped with active-low-clamping

capability. Furthermore, they feature a large ground bounce ruggedness in order to compensate

ground bounces caused by a turn-off of the driven IGBT.

4.4 Coreless Transformer (CLT)

In order to enable signal transmission across the isolation barrier between low-side and high-side

driver, a transformer based on CLT-Technology is employed. Signals, that are to be transmitted,

are specially encoded by the transmitter and correspondingly restored by the receiver. In this way

EMI due to variations of GNDH (dVGNDH/dt) or the magnetic flux density (dΗ/dt) can be

suppresed.To compensate the additional propagation delay of transmitter, level shifter and

receiver, a dedicated propagation delay is introduced into the low-side driver.

High and Low Side Driver

2ED020I06-FI

Functional Description

Datasheet 9 April 2010

4.5 Diagrams

InH

InL

/SD

OutH

OutL

Figure 3 Input/Output Timing Diagram

High and Low Side Driver

2ED020I06-FI

Electrical Parameters

Datasheet 10 April 2010

5 Electrical Parameters

5.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead

to destruction of the integrated circuit. Unless otherwise noted all parameters refer to

GND.

Parameter Symbol Limit Values Unit Remarks

min. max.

High side ground GNDH – 650 650 V

High side supply voltage VSH – 0.3 20 V 1)

1) With reference to high side ground GNDH.

High side gate driver output OutH – 0.3 VSH + 0.3 V1)

Low side ground GNDL – 0.3 5.3 V

Low side supply voltage VSL – 0.3 20 V 2)

2) With respect to both GND and GNDL.

Low side gate driver output OutL – 0.3 VSL + 0.3 V3)

3) With respect to GNDL.

Logic input voltages

(InH, InL, SD)

VIN – 0.3 5.3 V

High side ground, voltage

transient

dVGNDH /dt – 50 50 V/ns

ESD Capability VESD — 2 kV 4)

4) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor).

Human

Body Model

Package power disipation @TA

= 25°C

PD—1.4 W5)

5) Considering Rth(both chips active)=90K/W

Thermal resistance (both chips

active), junction to ambient

RTHJA — 90 K/W 6)

Thermal resistance (high side

chip), junction to ambient

RTHJA(HS) — 110 K/W 6)

Thermal resistance (low side

chip), junction to ambient

RTHJA(LS) — 110 K/W 6)

Junction temperature TJ— 150 °C

Storage temperature TS– 55 150 °C

High and Low Side Driver

2ED020I06-FI

Electrical Parameters

Datasheet 11 April 2010

5.2 Operating Range

Note: Within the operating range the IC operates as described in the functional

description.Unless otherwise noted all parameters refer to GND.

Parameter Symbol Limit Values Unit Remarks

min. max.

High side ground GNDH – 650 650 V

High side supply voltage VSH 14 18 V 1)

1) With reference to high side ground GNDH.

Low side supply voltage VSL 14 18 V 2)

2) With respect to both GND and GNDL.

Logic input voltages

(InH, InL, SD)

VIN 0 5 V

Junction temperature TJ– 40 105 °C Industrial

applications,

useful lifetime

87600h

Junction temperature TJ– 40 125 °C Other

applications,

useful lifetime

15000h

5.3 Electrical Characteristics

Note: The electrical characteristics involve the spread of values for the supply voltages, load and

junction temperature given below. Typical values represent the median values, which are

related to production processes. Unless otherwise noted all voltages are given with

respect to ground (GND). VSL = VSH – GNDH = 15 V, CL = 1 nF, TA = 25 °C. Positive

currents are assumed to be flowing into pins.

6) Device soldered to reference PCB without cooling area

Voltage Supply

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

High side

leakage current

IGNDH — 0 — µAGNDH = 1.2 kV

GNDL = 0 V

High and Low Side Driver

2ED020I06-FI

Electrical Parameters

Datasheet 12 April 2010

High side quiescent supply

current

IVSH —2.4 3.2 mA VSH = 15 V1)

—2.3 3.2 mA VSH = 15 V1)

TJ = 125 °C

High side undervoltage

lockout, upper threshold

VVSH

1) 10.9 12.2 13.5 V

High side undervoltage

lockout, lower threshold

VVSH

1) —11.2 — V

High side undervoltage

lockout hysteresis

∆VVSH 0.7 11.3 V

Low side quiescent supply

current

IVSL —3.9 5.0 mA VSL = 15 V

3.9 5.5 mA VSL = 15 V

TJ = 125 °C

Low side undervoltage

lockout, upper threshold

VVSL 10.7 12 13.3 V

Low side undervoltage

lockout, lower threshold

VVSL — 11 — V

Low side undervoltage

lockout hysteresis

∆VVSL 0.7 11.3 V

1) With reference to high side ground GNDH.

Logic Inputs

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

Logic “1” input voltages

(InH, InL, SD)

VIN 2 — — V

Logic “0” input voltages

(InH, InL, SD)

VIN — — 0.8 V

Logic “1” input currents

(InH, InL)

IIN — 40 55 µA VIN = 5 V

Logic “0” input currents

(InH, InL)

IIN — 0 — µA VIN = 0 V

Voltage Supply (cont’d)

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

High and Low Side Driver

2ED020I06-FI

Electrical Parameters

Datasheet 13 April 2010

Logic “1” input currents

(SD)

IIN — 0 — µA VIN = 5 V

Logic “0” input currents

(SD)

IIN –60 –40 — µA VIN = 0 V

Gate Drivers

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

High side high level output

voltage

VVSH –

VOutH

—1.4 1.7 V IOutH = –1mA

VInH = 5V

High side low level output

voltage

VOutH

1) With reference to high side ground GNDH.

— — 0.1 V IOutH = 1mA

VInH = 0V

Low side high level output

voltage

VVSL –

VOutL

—1.4 1.7 V IOutL = –1mA

VInL = 5V

Low side low level output

voltage

VOutL — — 0.1 V IOutL = 1mA

VInL = 0V

Output high peak current

(OutL, OutH)

IOut — — – 1 A VIN = 5 V

VOut = 0 V

Output low peak current

(OutL, OutH)

IOut 2 — — A VIN = 0 V

VOut = 15 V

High side active low

clamping

VOutH

1) —2.6 3 V InH =0V, VSH open

IOutH =200mA

—2.7 3.2 VInH =0V, VSH open

IOutH =200mA

TJ = 125 °C

Low side active low

clamping

VOutL —2.6 3 V InL =0V, VSL open

IOutL =200mA

—2.7 3.2 VInL =0V, VSL open

IOutL =200mA

TJ = 125 °C

Logic Inputs (cont’d)

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

Dynamic Characteristics

Parameter Symbol Limit Values Unit Test Condition

min. typ max.

Turn-on propagation delay tON — 85 105 ns GNDH = 0 V

20% Vout

— 95 120 ns GNDH = 0 V

20% Vout

TJ = 125 °C

Turn-off propagation delay tOFF — 85 115 ns 80% Vout

— 100 130 ns 80% Vout

TJ = 125 °C

Shutdown propagation

delay

tSD — 85 115 ns 80% Vout

— 100 130 ns 80% Vout

TJ = 125 °C

Turn-on rise time tr— 20 40 ns 20% to 80% Vout

— 30 50 ns 20% to 80% Vout

TJ = 125 °C

Turn-off fall time tf— 20 35 ns 80% to 20% Vout

— 25 40 ns 80% to 20% Vout

TJ = 125 °C

Delay mismatch (high &

low side turn-on/off)

∆t — 15 25 ns TJ = 25°C

see Figure 6

— 15 30 ns TJ = 125°C

see Figure 6

Minimum turn-on input

(InH, InL) pulse width

tpON — 50 75 ns 1)

1) InH-Pulses shorter than the “minimum turn-on(off) input pulse width” are prolonged to 50ns (See Figure 7). InL-Input

doesn´t have this feature.

— 55 80 ns 1) TJ = 125°C

Minimum turn-off input

(InH, InL) pulse width

tpOFF — 50 75 ns 1)

— 55 80 ns 1) TJ = 125 °C

High and Low Side Driver

2ED020I06-FI

Electrical Parameters

Datasheet 14 April 2010

High and Low Side Driver

2ED020I06-FI

Package Outline

Datasheet 15 April 2010

6 Package Outline

Note: dimensions are given in mm.

6.1 Soldering Profile

The soldering profile qualified for 2ED020I06-FI (according to the standard IPC/JEDEC J-STD-

020C) is moisture sensitivity level 3. The peak reflow temperature for its package (volume < 350

mm3) is 260 +0/-5 °C.

High and Low Side Driver

2ED020I06-FI

Diagrams

Datasheet 16 April 2010

7 Diagrams

0.8V

80% 80%

20% 20%

InH/L

OutH/L

tON

tOFF

Figure 4 Switching Time Waveform Definition

/SD

OutH/L

tSD

0.8V

80%

Figure 5 Shutdown Waveform Definition

InL

InH

OutL

OutH

0.8V

80% 80%

20% 20%

tOFFL

tONH

tOFFH

tONL

High and Low Side Driver

2ED020I06-FI

Diagrams

Datasheet 17 April 2010

∆t = max (|tONH - tOFFL| , |tOFFH - tONL|)

Figure 6 Delay Matching Waveform Definitions

InH

OutH

50ns 50ns

Figure 7 Short InH-Pulses Prolongation

High and Low Side Driver

2ED020I06-FI

Application Advices

Datasheet 18 April 2010

8 Application Advices

8.1 Power Supply

a) The connection of a capacitor (>10nF) as close as possible to the supply pins VSH, VSL is

recommended for avoiding that possible oscillations in the supply voltage can cause erroneous

operation of the output driver stage. Total value of capacitance connected to the supply terminals

has to be determined by taking into account gatecharge, peak current, supply voltage and kind of

power supply.

b) If a bootstrap power supply for the high side driver is applied, a resistor of 10Ω minimum in

series with the bootstrap diode is required.

High and Low Side Driver

2ED020I06-FI

Application Advices

Datasheet 19 April 2010

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