64 x 4 Cascadable FIFO
64 x 5 Cascadable FIFO
CY7C401/CY7C403
CY7C402/CY7C404
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 9 5 1 3 4 • 408- 943-2600
March 1986 – Revised April 1995
1CY7C40 2
Features
• 64 x 4 (CY7C401 and CY7C403)
64 x 5 (CY7C402 and CY7C404)
High-speed first-in first -out memory (FIFO)
• Processed with high-speed CMOS for optimum
speed/power
• 25-MHz data rates
• 50-ns bubble-t hrough ti me—25 MHz
• Ex pandable in word width and/or length
• 5-volt power supply ± 10% tolerance , both commercial
and mil it a ry
• Independent a synchronous inputs and outputs
• TTL-compatible interface
• Output enable function available o n CY7C403 and
CY7C404
• Capable of withstanding greater t han 2001V electro-
static discharge
• Pin compatible with MMI 67401A/67402A
Functional Descrip tion
The CY7C401 and CY7C403 are asynchronous first-in
first-out (FIFOs) organized as 64 four-bit words. The CY7C402
and CY7C404 are similar FIFOs organized as 64 five-bit
words. Both the CY7C403 and CY7C404 have an output en-
able (OE) function.
The devices accept 4- or 5-bit words at th e data input (DI0 –
DIn) under the control of the shift in (SI) input. The stored
words stack up at the output (DO0 – DOn) in the order they
were entered. A read command on the shift out (SO) input
causes the nex t to last word to move to the output and all data
shifts down once in the stack. The input ready (IR) s ignal acts
as a flag to indicate when th e input is ready to ac cept new data
(HIGH), to indicate when the FIFO is full (LOW), and to provide
a signal for a cascading. The output ready (OR) signal is a flag
to indicate the output contains valid data (HIGH), to indicate
the FIFO is empty (LOW), and to pro vide a signal for cascad-
ing.
Parallel expansion for wider words is accomp lishe d by lo gical-
ly ANDing the IR and OR signals to form c omposit e signals.
Serial expansion is accomplished by tying the data inputs of
one device to the data outputs of the pre vious device. The I R
pin of the receiving device is connected to the SO pi n of the
sending device, and the OR pin of the sending de vice is con-
nected to the SI pin of the receiving device.
Reading and writing op erations are completely asynchronous,
allowing the FIFO t o be used as a buffer between two digital
machines of widely differing operating frequencies. The
25-MHz operation makes these FIFOs ideal for high-speed
communication and controller applications.
CY7C402
CY7C404
Logic Block Diagram Pin Configurations
C401–1
C401–2
C401–3
1
2
3
4
5
6
7
8
12
11
10
9
13
16
15
14
(CY7C401) NC
(CY7C403) OE
IR
SI
DI0
DI1
VCC
SO
OR
DO 0
DO 1
DO 3
MR
DO 2
DI2
DI3
GND
20
4
5
6
7
8
321 19
910111213
18
17
16
15
14
SI
DI 0
DI 1
DI 2DO 0
DO 1
NC
DO 2
OR
NC
INPUT
CONTROL
LOGIC
SI
IR
DATAIN
DI0
DI1
DI2
DI3
(DI4)
MASTER
RESET
MR
WRITE MULTIPLEXER
WRITEPOINTER
READ MULTIPLEXER
READ POINTER
MEMORY
ARRAY
OUTPUT
CONTROL
LOGIC
DATAIN
OUTPUT
ENABLE OE
DO0
DO1
DO2
DO3
(DO4)
SO
OR
1
2
3
4
5
6
7
8
14
13
12
11
15
18
17
16
IR
SI
DI 0
DI 1
VCC
SO
OR
DO0
DO1
DO3
DO4
DO2
DI 2
DI 3
DI 4
CY7C401
CY7C403
(CY7C402) NC
(CY7C404) OE
910 MRGND
CY7C401
CY7C403
C401–4
20
4
5
6
7
8
321 19
910111213
18
17
16
15
14
C401–5
SI
DI 0
DI 1
DI 2
DO 0
DO 1
DO 2
OR
DO 3
DI 3
CY7C402
CY7C404
LCC
DIP
LCC
DIP
Selec tion Gu ide
7C401/2–5 7C40X–10 7C40X–15 7C40X–25
Operating Fr equency (MHz) 5 10 15 25
Maximum Operat i ng
Cur rent (mA) Commercial 75 75 75 75
Military 90 90 90
CY7C401/CY7C403
CY7C402/CY7C404
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ......... ........................–65°C to +150°C
Ambient Temperature with
Power Applied.................. ...........................–55°C to +125°C
Supply Volta ge to Gro und Pot ential............... –0.5V to +7.0V
DC Voltage Applied to Output s
in High Z State................................ ..... ..... ..... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Power Dissipation.................................... ......................1.0W
Output Current, into Outputs (LO W) .. ............ ....... ....... 20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current........................ .............................>200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Military[1] –55°C to +125°C 5V ±10%
Electrical Characteristics Over the Operating Range ( Unless Otherwise Noted)[2]
7C40X–10 , 15, 25
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 6.0 V
VIL Input LOW Voltage –3.0 0.8 V
IIX In put Leakage Current G ND ≤ VI ≤ VCC –10 +10 µA
VCD[3] Input Diode Clamp Voltage[3]
IOZ Outp ut Leakage Current G ND ≤ VOUT ≤ VCC, VCC = 5.5V
Output Disabled (CY7C403 and CY7C404) –50 +50 µA
IOS Output Short Circuit Current[4] VCC = Max., VOUT = GND –90 mA
ICC Power Supply Current VCC = Max., IOUT = 0 mA Commercial 75 mA
Military 90 mA
Capacitance[5]
Parameter Description Test Condit ions Max. Unit
CIN Input Capaci tance TA = 25°C, f = 1 MHz,
VCC = 4.5V 5pF
COUT Output Capaci tance 7 pF
Notes:
1. TA is the “instant on” case temperature.
2. See the last page of this specification for Group A su bgroup testing information.
3. The CMOS process does not provide a clamp diode. However, the FIFO is insensitive to –3V dc input levels and –5V undershoot pulses of less than 10 ns
(measured at 50% output).
4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
5. Tested ini tially and after any design or process changes that may affect these parameters.
CY7C401/CY7C403
CY7C402/CY7C404
3
AC Test Loads and Waveforms
C401–6 C401–7
90%
10%
3.0V
GND
90%
10%
ALL INPUT PUL SES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤5ns ≤5ns
OUTPUT 1.73V C401–8
R1 437Ω
R2
272ΩR2
272Ω
R1 437Ω
167Ω
Equivalent to: THÉ VENIN EQUIVALENT
Switching Characteristics Over the Operating Range [2 , 6]
Test
Conditions
7C401–5
7C402–5 7C40X–10 7C40X–15 7C40X–25[7]
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
fOOperating Frequency Note 8 5 10 15 25 MHz
tPHSI SI HIGH Ti me 20 20 20 11 ns
tPLSI SO LOW Time 45 30 25 20 ns
tSSI Data Set-Up to SI Note 9 0 0 0 0 ns
tHSI Data Hold fr om SI Note 9 60 40 30 20 ns
tDLIR Delay, SI HIGH to IR LOW 75 40 35 21/22 ns
tDHIR Delay, SI LOW to IR HIGH 75 45 40 28/30 ns
tPHSO SO HIGH Time 20 20 20 11 ns
tPLSO SO LOW Time 45 25 25 20 ns
tDLOR Delay, SO HIGH to OR LOW 75 40 35 19/21 ns
tDHOR Delay, SO LOW to OR HIGH 80 55 40 34/37 ns
tSOR Data Set-Up to OR HIGH 0 0 0 0 ns
tHSO Data Hold fr om SO LOW 5 5 5 5 ns
tBT Bubble-Through Tim e 200 10 95 10 65 10 50/60 ns
tSIR Data Set-Up to I R Note 10 5 5 5 5 ns
tHIR Data Hold from IR Note 10 30 30 30 20 ns
tPIR Input R eady Pul se H IGH 20 20 20 15 ns
tPOR Output Ready Pulse HIGH 20 20 20 15 ns
tPMR MR Pulse Width 40 30 25 25 ns
tDSI MR HIGH to SI HIGH 40 35 25 10 ns
tDOR MR LOW to OR LO W 85 40 35 35 ns
tDIR MR LOW to IR HIGH 85 40 35 35 ns
tLZMR MR LOW to Output LOW Note 11 50 40 35 25 ns
tOOE Output Valid from OE LOW — 35 30 20 ns
tHZOE Output High Z from OE HIGH Note 12 — 30 25 15 ns
Notes:
6. Test con dit ions ass u me signal transi ti on tim e of 5 ns or less, timing refere nce le ve ls of 1.5V an d outpu t load ing of the speci fie d IOL/IOH and 30-pF load
capacitance, as in part (a) of AC Test Loads and Waveforms.
7. Commercial/Military
8. I/fO > tPHSI + tDHIR, I/fO > tPHSO + tDHOR
9. tSSI and tHSI ap ply when memory is not full.
10. tSIR an d tHIR apply wh en mem ory is full, S I is high and mi nimu m bubb le-thr ough (tBT) conditions exist.
11. All data outputs will be at LOW level after reset goes HIGH unti l data is entered into the FIFO.
12. HIGH-Z transitions are referenced to the steady-state VOH –500 m V and VOL +500 mV levels on the output. tHZOE is tested with 5-pF load capacitance as
in part (b) of AC Test Loads and Waveforms.
CY7C401/CY7C403
CY7C402/CY7C404
4
Operational Descrip tion
Concept
Unlike traditional FI FO s, these devices are designed usi ng a
dual-port memory, read and write pointer, and control logic.
The read and write pointers are inc remented by the SO and SI
respe ctively. The availability of a n empty space to shift in data
is indicated by the IR signal, while the presence of data at the
output is indicated by th e OR signal. The con ventional concept
of bubble-through is absent. Inst ead, t he delay for input data
to appear at the output is the time required t o move a pointer
and propagate an OR signal. The output enable (OE) sig nal
provides the capability to OR tie multiple FIFOs together on
a co mm o n b u s.
Resetti ng the FI FO
Upon power-up, the FIFO must be reset with a master reset
(MR) signal. This caus es th e FIFO to enter an empty condition
signified by the OR signal being LOW at the same time the IR
signal is HIGH. In this condition, the data outputs (DO0 – DOn)
will be in a LOW s tate.
Shifting D ata In
Data is shifted in on the rising edge of the SI signal. This loads
inpu t data into the first word location of the F IFO. On the falling
edge of the SI signal, the write pointer is moved to the next
word position and the IR signal goes HIGH, indicating the
readiness to accept new data. If the FIFO is full, the IR will
remain LOW until a word of data is shifted out.
Shifting D ata Out
Data is shifted out of the FIFO on the falling edge of the SO
sign al. This cause s the internal read pointer to be advanced t o
the next word location. If data is present, valid d ata will a ppear
on the outputs and the OR signal will go HIGH. If data is not
present, the OR signal will stay LOW indicating the FIFO is
empty. Upon the rising edge of SO, the OR signal goes LOW.
The data outputs of the FIFO should be sampled with
edge-sensitive ty pe D flip-f lops (or eq ui val ent), u si ng the SO
signal a s the clock input to the flip-flop.
Bubble-Through
Two bubble-through condit ions exist. The first is when the de-
vice is empty. After a word is sh ifted into an empty dev ice, the
data pr opagates to the output. After a delay, the OR flag goes
HIGH, indicating valid data at the output.
The second bubble-through condition occurs whe n the device
is full. Shif ting data out create s an empty location th at propa-
gates to the input. After a delay, the IR flag goes HIGH. If the
SI signal is HIGH at this time, data on the input will be shift ed
in.
Possible Minimum Pulse Width Violation at the Boundary
Conditions
If the handshaking signals IR an d OR are not properly used to
generate the SI and SO signals, it is possible to violate the
minimum (effective) SI and SO positive pulse widths at the full
and em pty boundarie s.
When this violation occurs, the operation of the FIFO is unp re-
dictable. It must t h en be reset, and all dat a is l ost.
Application of the 7C403–25/7C404–25 at 25 MHz
Application of the CY7C403 or CY7C404 Cypress CMOS
FIFOs requires knowledge of characteristics that are not easily
specified i n a datasheet, but which are necessary for reliable
operation under all condit ions, so we will specify them here.
When a n empty FIFO is fi lled with initial i nformation at maxi-
mum “shift in” S I f requency, fo llowed by immediate shifting out
of the data also at maximum “ shift out” SO fr equency, the de-
signer must be aware of a window of time which follows the
initial r ising edge of the OR signal , d uring which time the S O
signal is not recognized. This condition exists only at
high-speed operation where more than one SO may be gen-
erated inside the prohibited window. This condition does not
inhibit the operation of the FIFO at full-frequency operation,
but rather dela ys t he full 25-MHz operation until after the win-
dow has passed.
There are several implementation techniques for managing
the window so that all SO signals are recognized:
1. The first involves delaying SO op eration such that it does
not occur in the critical window. This c an be accomplished
by causing a fixed delay o f 4 0 ns “initiated by the SI signal
only when t he FIFO is empty” to i nhibit or gate the SO ac-
tivity. However, this requires th at t he SO operation be at
least temporarily synchronized with the i nput SI operation.
In synchronous applications this may well be possible and
a valid solution.
2. Another sol ution not uncommon in synchronous appli ca-
tions is to on ly begin sh ifting data out of the FIFO when it is
more than half full. This is a common method of FI FO ap-
plicat ion, as ear lier FIFOs could not be operated at maxi-
mum frequency when near full or empty. Although Cypress
FIFO s do not have this limi tation, an y s ystem d esi gned i n
this manner will n ot encounter the window condition de-
scribed above.
3. The windo w may also be managed b y not allowing the f irst
SO s ign al t o occur until the window in question has pass ed.
This can be accom plished by delaying the SO 40 ns from
the rising edge of the initial OR signal. This however in-
volves the requirement that this only occurs on the first oc-
curren ce of data being loaded into the FIFO from an empty
condition and therefore requires th e knowledge of IR and
SI conditions as well as SO.
4. Handshaking w ith the OR signal is a third method of avoid-
ing the window i n questio n. W ith this technique the rising
edge of SO, or the fact t hat SO signal is HIGH, will cause
the OR signal to go LOW. The SO signal is no t taken LOW
again, advancin g the internal pointer to the next data, until
the OR signal goes LOW. This ensur es that the SO pulse
that is initiated in the window will be automatically extended
long enough to be recognized.
5. There r emains the decision as to what signal will be used
to latch the data from the output o f the FIFO into the receiv-
ing source. The leading ed ge of t he SO signal is most ap-
propriate because data is guaranteed to be sta ble prior to
and after the SO le ading edge f or each FIFO. This is a
solution for a ny number of FIFOs in parallel.
Any of the above solutions will ensure the correct operation o f
a Cypress FIFO at 25 MHz. The specific implementation is left
to the designer and is dependent on the specific application
needs.
CY7C401/CY7C403
CY7C402/CY7C404
5
Switching Waveforms
Data In Timing Diagram
Data Out TimingDiagram
Bubble Through, Data Out To Data In Diagram
C401–9
C401–10
C401–11
SHIFT IN
I/fOI/fO
tPHSI tPLSI tDHIR
tDLIR
INPUT READY
tHSI
tSSI
DATA IN
SHIFT OUT
I/fOI/fO
tPHSO tPLSO tDHOR
tDLOR
OUTPUT READY
tHSO
DATA OUT
tSOR
SHIFT IN
INPUT READY
DATA IN
SHIFT OUT
tBT
tPIR
tHIR
tSIR
CY7C401/CY7C403
CY7C402/CY7C404
6
Switching Waveforms (continued)
tHZOE
Bubble Through, Data In To Data Out Diagram
Master Reset Timing Diagram
Output Enable Timing Diagram
C401–12
C401–13
C401–14
SHIFT OUT
OUTPUT READY
DATA OUT
S HIFT IN
tBT tPOR
tSOR
INPUT READY
DATA OUT
SHIFT IN
tPMR
MASTER RESET tDIR
OUTPUT READY
tDOR
tDSI
tLZMR
OUT PUT ENABL E
DATA OUT
tOOE
NOTE 10
CY7C401/CY7C403
CY7C402/CY7C404
7
Typical DC and AC Characteristics
1.2
1.0
0.6
0.4
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
–55 25 125
–55 25 125
1.4
1.0
0.8
60
50
40
30
20
10
0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED FREQUENCY
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENTTEMPERATURE (°C) OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.8
1.3
1.2
1.1
1.0
0.9
0.8
4.0 4.5 5.0 5.5 6.0
NORMALIZED FREQUENCY
vs. SUPPLY VOLTAGE 140
120
60
40
20
0.0 1.0 2.0 3.0 4.0
0
80
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.0
VCC =5.0V
TA=25°C
0.60.7
0
1.6
1.4
1.2
0 200 400 600 800
CAPACITANCE (pF)
TYPICAL FREQUENCY CHANGE
vs. OUTPUT LOADING
0153035
FREQUENCY (MHz)
NORMALIZED ICC
vs. FREQUENCY
1.0 1000 0.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)
VCC =5.5V
VIN =5.0V
0.8
0.7
VIN =5.0V
TA=25°C
VCC =5.0V
TA=25°C
1.2
100
1.5
1.3
1.1
0.9
1.1
1.0
510 2025 C401–15
CY7C401/CY7C403
CY7C402/CY7C404
8
FIFO Expans ion[13, 14, 15, 16, 17]
Notes:
13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles through to the output.
However, OR will remain LOW, indicating data at the output is not valid.
14. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW befor e there is any change in output data, and stays LOW
until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid, stable data on the outputs.
15. If SO is held HIGH while the memory is empty and a word is written into the input, that word will ripple through the memory to the output. OR will go HIGH
for one internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO,
they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.
16. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the master reset goes HIGH,
then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset
is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.
17. All Cypress FIFOs will cascade with other Cypress FIFOs. However, hey may not cascade with pin-compatible FIFOs from other manufacturers.
18. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
19. FIFOs are exp andable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready
flags. This need is due to the v ariation of delays of the FIFOs.
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
OUTPUT READYSHIFT IN SHIFT OUTINPUT READY
DATA IN DATA OUT
MR C401–16
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
COMPOSITE
OUTPUT READY
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SO
ORSI
IR
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
MR
SHIFT OUT
MR
COMPOSITE
INPUT READY
SHIFT IN
C401–17
128 x 4 A pplicatio n[18]
192 x 12 Applicat ion[19]
CY7C401/CY7C403
CY7C402/CY7C404
9
Orde rin g Inf orm a tio n
Speed
(MHz) O rderi n g Code Package
Name Package Type Operating
Range
5 CY7C401–5PC P1 16-L ead (300-Mil) Molded DIP Commercial
10 CY7C401–10DC D2 16-Lead (300-Mil) CerDIP Commercial
CY7C401–10PC P1 16-L ead (300-Mil) Molded DIP
CY7C401–10DMB D2 16-Lead (300- Mil) Cer DIP Military
CY7C401–10LMB L61 2 0-Pin Square Leadless Chip Carrier
15 CY7C401–15DC D2 16-Lead (300-Mil) CerDIP Commercial
CY7C401–15PC P1 16-L ead (300-Mil) Molded DIP
CY7C401–15DMB D2 16-Lead (300- Mil) Cer DIP Military
CY7C401–15LMB L61 2 0-Pin Square Leadless Chip Carrier
25 CY7C401–25DC D2 16-Lead (300-Mil) CerDIP Commercial
CY7C401–25PC P1 16-L ead (300-Mil) Molded DIP
CY7C401–25DMB D2 16-Lead (300- Mil) Cer DIP Military
CY7C401–25LMB L61 2 0-Pin Square Leadless Chip Carrier
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
5 CY7C402–5PC P3 18-L ead (300-Mil) Molded DIP Commercial
10 CY7C402–10DC D4 18-Lead (300-Mil) CerDIP Commercial
CY7C402–10PC P3 20-Pin Square Leadless Chip Carrier
CY7C402–10DMB D4 18-Lead (300- Mil) Cer DIP Military
CY7C402–10LMB L61 2 0-Pin Square Leadless Chip Carrier
15 CY7C402–15DC D4 18-Lead (300-Mil) CerDIP Commercial
CY7C402–15PC P3 18-L ead (300-Mil) Molded DIP
CY7C402–15DMB D4 18-Lead (300- Mil) Cer DIP Military
CY7C402–15LMB L61 2 0-Pin Square Leadless Chip Carrier
25 CY7C402–25DC D4 18-Lead (300-Mil) CerDIP Commercial
CY7C402–25PC P3 18-L ead (300-Mil) Molded DIP
CY7C402–25DMB D4 18-Lead (300- Mil) Cer DIP Military
CY7C402–25LMB L61 2 0-Pin Square Leadless Chip Carrier
CY7C401/CY7C403
CY7C402/CY7C404
10
Orde rin g Inf orm a tio n (continued)
Speed
(MHz) O rderi n g Code Package
Name Package Type Operating
Range
10 CY7C403–10DC D2 16-Lead (300-Mil) CerDIP Commercial
CY7C403–10PC P1 16-L ead (300-Mil) Molded DIP
CY7C403–10DMB D2 16-Lead (300- Mil) Cer DIP Military
CY7C403–10LMB L61 2 0-Pin Square Leadless Chip Carrier
15 CY7C403–15DC D2 16-Lead (300-Mil) CerDIP Commercial
CY7C403–15PC P1 16-L ead (300-Mil) Molded DIP
CY7C403–15DMB D2 16-Lead (300- Mil) Cer DIP Military
CY7C403–15LMB L61 2 0-Pin Square Leadless Chip Carrier
25 CY7C403–25DC D2 16-Lead (300-Mil) CerDIP Commercial
CY7C403–25PC P1 16-L ead (300-Mil) Molded DIP
CY7C403–25DMB D2 16-Lead (300- Mil) Cer DIP Military
CY7C403–25LMB L61 2 0-Pin Square Leadless Chip Carrier
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
10 CY7C404–10DC D4 18-Lead (300-Mil) CerDIP Commercial
CY7C404–10PC P3 18-L ead (300-Mil) Molded DIP
CY7C404–10DMB D4 18-Lead (300- Mil) Cer DIP Military
CY7C404–10LMB L61 2 0-Pin Square Leadless Chip Carrier
15 CY7C404–15DC D4 18-Lead (300-Mil) CerDIP Commercial
CY7C404–15PC P3 18-L ead (300-Mil) Molded DIP
CY7C404–15DMB D4 18-Lead (300- Mil) Cer DIP Military
CY7C404–15LMB L61 2 0-Pin Square Leadless Chip Carrier
25 CY7C404–25DC D4 18-Lead (300-Mil) CerDIP Commercial
CY7C404–25PC P3 18-L ead (300-Mil) Molded DIP
CY7C404–25DMB D4 18-Lead (300- Mil) Cer DIP Military
CY7C404–25LMB L61 2 0-Pin Square Leadless Chip Carrier
CY7C401/CY7C403
CY7C402/CY7C404
11
MIL ITARY SP EC IFICATIONS
Group A Subgroup Testing
Document #: 38–00040–H
DC Characteristics
Parameters Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL Max. 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
IOS 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameters Subgroups
fO7, 8, 9, 10, 11
tPHSI 7, 8, 9, 10, 11
tPLSI 7, 8, 9, 10, 11
tSSI 7, 8, 9, 10, 11
tHSI 7, 8, 9, 10, 11
tDLIR 7, 8, 9, 10, 11
tDHIR 7, 8, 9, 10, 11
tPHSO 7, 8, 9, 10, 11
tPLSO 7, 8, 9, 10, 11
tDLOR 7, 8, 9, 10, 11
tDHOR 7, 8, 9, 10, 11
tSOR 7, 8, 9, 10, 11
tHSO 7, 8, 9, 10, 11
tBT 7, 8, 9, 10, 11
tSIR 7, 8, 9, 10, 11
tHIR 7, 8, 9, 10, 11
tPIR 7, 8, 9, 10, 11
tPOR 7, 8, 9, 10, 11
tPMR 7, 8, 9, 10, 11
tDSI 7, 8, 9, 10, 11
tDOR 7, 8, 9, 10, 11
tDIR 7, 8, 9, 10, 11
tLZMR 7, 8, 9, 10, 11
tOOE 7, 8, 9, 10, 11
tHZOE 7, 8, 9, 10, 11
CY7C401/CY7C403
CY7C402/CY7C404
12
Package Diagrams
16-Lead (300-Mil) CerDIP D2
MIL-STD-1835 D-2 Con fig .A 18-Lead (300-Mil) CerDIP D4
MIL-STD-1835 D-8 Config.A
20-Pin Square Leadless Chip Carrier L61
MIL -STD-1 835 C–2A
CY7C401/CY7C403
CY7C402/CY7C404
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semicondu ctor product. Nor does it convey or imply an y li cense under patent or other rights. Cypress Semicondu ctor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in s ignificant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes al l risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continu ed)
16-Lead (300-Mil) Molded DIP P1
18-Lead (300-Mil) Molded DIP P3
