28C256 SEEQ Timer E? Technelogye neorporsies 256K Electrically Erasable PROM August 1992 Features @ Military, Extended and Commercial @ Power Up/Down Protection Circuitry Temperature Range ; 200 ns Maximum Access Time -55C to +125C Operation (Military) +-40C to +85C Operation (Extended) JEDEC Approved Byte Wide Pinout 0C to +70C Operation (Commercial) m@ CMOS Technology Description B Low Power p j F + 60 mA Active SEEQ's 28C256 is a CMOS SV only, 32K x 8 Electrically Erasable Programmable Read Only Memory (EEPROM). +250 uA Standby It is manufactured using SEEQ's advanced 1.25 micron Page Write Mode CMOS Process and is available in most popular thru hole 64 Byte Page and surface mount package options as listed under Or- 160 ps Average Byte Write Time dering Information. The 28C256 is ideal for applications @ Byte Write Mode which require low power consumption, non-volatility andin system reprogrammability. The endurance, the number of m Write Cycle Completion Indication times a byte can be written, is specified at 10,000 cycles DATAPolling m@ On Chip Timer . . . + Automatic Erase Before Write Pin Configuration M High Endurance DUAL-IN-LINE LEADLESS CHIP CARRIER + 10,000 Cycles/Byte TOP VIEW TOP VIEW 10 Year Data Retention A Hl MIL-STD-883 Class B Compliant a 5962 SMD Compliant Ay - PARI! Sis Block Diagram s s Xi = 126 a es 02s ROW Ack ADDRESS LATCHES Se ee Sts 5, COLUMN ADDRESS LATCHES hos) Note: The PLCC package has the same pin configuration as the LCC except pin 1 and pin 17 are dont connects. . = Pin Names We A,-A, ADDRESSES ~ COLUMN A,-A,, ADDRESSES ROW 3 _vOBUFFERY CE CHIP ENABLE DATA POLLING OE OUTPUT ENABLE WE WRITE ENABLE vO DATA INPUT (WRITEVDATA Wo7 OUTPUT (READ) - SEEQ Technology, Incorporated 4-59 MD400099/Aper byte and, is typically 1,000,000 cycles per byte. The extraordinary high endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and it's innovative Q Cell design. System reliability, in all applications, is higher because of the low failure rate of the Q Cell. The 28C256 has an internal timer which automatically times out the write time. The on-chip timer, along with input latches free the microprocessor for other tasks once the write cycle has been initiated. The 28C256's write cycle time is 10 ms maximum. An automatic byte erase is per- formed before each byte/page write. The DATA polling feature of the 28C256 can be used to determine the end of a write cycle. Once the write cycle has been completed, data can be read in a maximum of 200 ns. Data retention is greater than 10 years. Device Operation Operational Modes There are five operational modes (see Table 1} and, except for the chip erase mode, only TTL inputs are required. A write can only be initiated under the conditions shown. Any other conditions for CE, OE, and WE will inhibit writing and the VO lines will either be in a high impedance state or have data, depending on the state of aforementioned three input lines. Mode Selection (Table 1) Mode CE | OE | WE vo Read It Vie Vin Dour Standby Vig xX Xx High Z Write Vi Vin Vi Dy Write X xX Vu High Z/D,., Inhibit Xx Vi xX High Z/D,,, Chip Erase | V,, Vi Vin X X: Any TTL level V,,: High Voltage Reads A read is typically accomplished by presenting the ad- dresses of the desired byte to the address inputs. Once the address is stable, CE is brought to a TTL low in order to enable the chip. The WE pin must be at a TTL high during the entire read cycle. The output drivers are made active by bringing Output Enable (OE) to a TTL low. During read, the addresses, CE, OE, and input data latches are transparent. Q Cell is a trademark of SEEQ Technology, Inc. 28C256 Writes To write into a particular location, the address must be valid and a TTL low applied to the Write Enable (WE) pin of a selected (CE low) device. This combined with Output Enable (OE) being high initiates a write cycle. During a byte write cycle, all inputs except data are latched on the falling edge of WE or CE, whichever occurred last. Write enable needs to be ata TTL low only for the specified le time. Data is latched on the rising edge of WE or CE whichever occurred first. An automatic erase is performed before data is written. The 28C256 can write both bytes and a page of up to 64 bytes. The write mode is discussed below. Write Cycle Control Pins For system design simplification, the 28C256 is designed such that either the CE or WE pin can be used to initiate a write cycle. The device uses the latest high-to-low transi- tion of either CE or WE signal to latch addresses and the earliest low-to-high transition to latch the data. Address and OE set up and hold are with respect to the later of CE or WE; data setup and hold is with respect to the earlier of WE or CE. To simplify the following discussion, the WE pinis used as the write cycle control pin throughout the rest of this data sheet. Timing diagrams of both write cycles are included in the AC Characteristics. Write Mode One to 64 bytes of data can be randomly loaded into the device. The part latches row addresses, A6-A14, during the first byte write. These addresses are latched on the falling edge of the WE signal and are ignored after that until the end of t,,. This will eliminate any false write into another page if different row addresses are applied and the page boundary is crossed. The column addresses, A0-AS, which are used to select different locations of the page, are latched every time a new write is initiated, These addresses and the OE state (high) are latched on the falling edge of WE signal. For proper write initiation and latching, the WE pin has to stay low for a minimum of ty, ns. Data is latched on the rising edge of WE, allowing easy microprocessor interface. Upon a low to high WE transition, the 28C256 latches data and starts the internal page load timer. The timer is reset on the falling edge of the WE signal if another write is SEEG Technology, Incorporated 1-60 MD400099/A SEEQ initiated before the timer has timed out. The timer stays reset while the WE pin is kept low. If no additional write cycles have been initiated within t,, , after the last WE low to high transition, the part terminates the page load cycle and starts the internal write. During this time which takes a maximum of 10 ms, the device ignores any additional write attempts. The part can now be read to determine the end of write cycle (DATA Polling). Extended Page Load In order to take advantage of the page mode's faster average byte write time, data must be loaded at the page load cycle time (t,,,). Since some applications may not be able to sustain transfers at this minimum rate, the 28C256 permits an extended page load cycle. To do this, the write cycle must be stretched by maintaining WE low, assuming a write enable-controlled cycle, and leaving all other control inputs (CE, OE) in the proper page load cycle state. Since the page load timer is reset onthe falling edge of WE, keeping this signal low will inhibit the page load timer. When WE returns high, the input datais latched and the page load cycle timer begins. In CE controlled write the sameis true, with CE holding the timer resetinstead of WE. DATA Polling The 28C256 has a maximum write cycle time of 10 ms. Typically though, a write will be completed in less than the specified maximum cycle time. DATA polling is a method . of minimizing write times by determining the actual end- point of a write cycle. Ifa read is performed to any address 28C256 while the 28C256 is still writing, the device will present the ones-complement of the last byte written. When the 28C256 has completed its write cycle, aread from the last address written will resultin valid data. Thus, software can simply read from the part until the last data byte written is read correctly. A DATA polling read should not be done until a minimum of t,, microseconds after the last byte is written. Timing for a DATA polling read is the same as a normal read once the t,, specification has been met. Chip Erase Certain applications may require all bytes to be erased simultaneously. This feature, which requires high voltage, is optional and timing specifications are available from SEEQ. Power Up/Down Considerations There is internal circuitry to minimize a false write during power up or power down. This circuitry prevents writing under any one of the following conditions. 1. Voge is less than V,, V. __ 2. A high to low Write Enable (WE) transition has not occurred when the V,, supply is between V,, V and Veg With CE low and OE high. Writing will also be inhibited when WE, CE, or OE are in TTL logical states other than that specified for a byte write in the Mode Selection table. Technote gy, incorporated MD400099/A 1-61Absolute Maximum Stress Range* Temperature SHOPAGE a. eeesecsesssessesesessessssctsenescesess -65C to +150C Under Bias Military/Extended 65C to +135C Commercial Temperature .......0..... -10C to +80C D.C. Voltage applied to all Inputs or Outputs with respect tO QrOUN .....cccsccscsesesee +6.0Vto-O05V Undershoot pulse of less then 10 ns (measured at 50% point) applied to all inputs or outputs With raSPOCt [0 FOUN ...eecessesccessesssescesssersesseese -1.0V Recommended Operating Conditions 28C256 Overshoot pulse of less than 10 ns (measred at 50% point )applied to all inputs or outputs With respect 10 GrOUNG ......cseccscsseesesseresessecessers +7.0V COMMENT: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Thisisa stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied, Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. MD400099/A 28C256-200 28C256-250 28C256-300 28C256-350 Temperature Commercial 0C to +70C 0C to +70C 0C to +70C 0C to +70C Range Extended ~40C to +85C | 40C to +85C | 40C to +85C | -40C to +85C Military ~55C to +125C | -55C to +125C | -55C to +125C | -55C to +125C Voc Power Supply 5V+10% 5V+10% 5V+10% 5V+10% Endurance and Data Retention Symbol Parameter Value Units Condition N Minimum Endurance 10,000 Cycles/Byte MIL-STD 883 Test Method 1033 Tor Data Retention >10 Years MIL-STD 883 Test Method 1008 SEEQ Toahnolegy, neerporntad 1 -62DC Characteristics Read Operation (Over operating temperature and V,,. range, unless otherwise specified) Limits Symbol Parameter Min. Max. Units Test Condition lec Active V,,, Current 60 mA CE = OE = V,: All VO open; Other Inputs V.. Max. leas Standby V,, Current 2 mA CE = V,,, OE = V,,; All YO Open; (TTL Inputs) Other Inputs = V,, to V,, lope Standby V.,, Current (CMOS Inputs) Military / Industrial 250 pA CE = V,, -0.3 Other Inputs = V,, to V,, All /O Open Commercial 200 pA CE = V,, -0.3 Other Inputs = V,, to V,, All VO Open 1,2) Input Leakage Current 1 HA Vin = Veco Max. Io!) Output Leakage Current 10 HA Vout = Veg Max. Vi Input Low Voltage -0.3 0.8 Vv Vig Input High Voltage 2.0 6 Vv Vou Output Low Voltage 0.45 v ly = 2.1 mA Von Output High Voltage 2.4 Vv loys = 400 pA Voq Write Inhibit Voltage 3.8 v NOTES: 1. Characterized. Not tested. 2. Inputs only. Does not include l/O. 3. For I/O only. SEEQ Technelegy, Incerperated 1 -63 MD400099/ACapacitance ! 7, = 25C, { = 1 MHz 280256 A.C. Test Conditions SEE Symbol | Parameter Max. | Conditions Output Load: 1 TTL gate and C, = 100 pF C Input C it 6 oF V.- OV Input Rise and Fall Times: < 10 ns IN npur capacitance P NS Input Pulse Levels: 0.4 V to 2.4 V Cour Data (1/0) Capacitance | 12 pF Vig = OV Timing Measurement Reference Level: Inputs 0.8 V and 2 V Outputs 0.8 V and 2 V AC Characteristics Read Operation (Over operating temperature and Voce range, unless otherwise specified) Limits 28C256-200 | 28C256-250 | 28C256-300 | 28C256-350 Test Symbol | Parameter Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max.| Units | Conditions tae Read Cycle Time 200 250 300 350 ns |CE = OE =V, toe Chip Enable Access Time 200 250 300 350 | ns |OE=V, tae Address Access Time 200 250 300 350 | ns |CE=OE=V, tog Output Enable Access Time 80 90 90 90 | ns |CE=V, tor Output or Chip Enable High to o | 60 ; Oo | 60 | O | 80 } oO |} 80 | ns |CE=V, output in Hi-Z ton Output Hold from Address 0 0 0 0 ns |CE=OE=V, Change, Chip Enable, or Output Enable, whichever occurs first Read /DATA Polling Cycle tre ir ADDRESSES ADDRESSES A y x NEXT ADDRESS x }t t a, _> ____ ps CE te} ___ p OE \ btt DF lL tou TOE Tony HIGH Z //, > x DATA KK 072 vat q DATA VALID TAA NOTES: 1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance. 2. Characterized. Not tested. Technetegy, Incerperated MD400099/A 1-6428C256 AC Characteristics Write Operation (Over the operating temperature and V,, range, unless otherwise specified) Limits 28C256-200 | 28C256-250 | 28C256-300 | 28C256-350 Symbol | Parameter Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Units twe Write Cycle Time 10 10 10 10 ms tas Address Set-up Time 20 20 20 20 ns tay Address Hold Time (see note 1) | 150 150 150 150 ns tes Write Set-up Time 0 0 0 0 ns ton Write Hold Time 0 0 0 0 ns tow CE Pulse Width (note 2) 150 150 150 150 ns toes OE High Set-up Time 20 20 20 20 ns toen OE High Hold Time 20 20 20 20 ns twp WE Pulse Width (note 2) 150 150 150 150 ns tos Data Set-up Time 50 50 50 50 ns ton Data Hold Time 0 0 0 0 ns tac Byte Load Timer Cycle 0.2 | 200 | 0.2 | 200 | 0.2 | 200 | 0.2 | 200 pS (Page Mode Only) (note 3) tip Last Byte Loaded 650 650 650 650 us to DATA Polling Write Timing WE CONTROLLED WRITE CYCLE CE CONTROLLED WRITE CYCLE ADDRESSES CE WE toe = ol toy he ~ bw DATA DATA 2 __ DATA IN DATA NOTES: 1, Address hold time is with respect to the falling edge of the control signal WE or CE. 2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle. 3. t,,, min. is the minimum time before the next byte can be loaded. t,,, max. is the minimum time the byte load timer waits before initiating internal write cycle. - SEEQ Technelegy, Incorporated 1-65 MD400099/APage Write Timing 28C256 DATA HIGH Z DATA ? D2 *. DATA PAGE LOAD $e 5.9 ng anenece <$< N ft OE toes ADDRESSES VALID DONT SY Z 7 x tas [no tes baa feel _ _ We \ OT ~ ft ton tip tos-~) Ordering Information T PACKAGE TEMPERATURE TYPE RANGE D = CERAMIC DIP M =-55C to + 125C L=Lcc (MILITARY) F = FLATPACK E =-40C to +85C N= PLCC (EXTENDED) P = PLASTIC DIP Q=0C to +70C T=PGA (COMMERCIAL) UX = UNENCAPSULATED DIE 28C256 -250 /B | PART TYPE 32K x 8 EEPROM LH. ACCESS TIME 200 = 200 ns 250 = 250 ns 300 = 300 ns 350 = 350 ns SCREENING OPTION MIL 883 CLASS B SCREENED SEE Technology, Incerpersiod MD400099/A 1-66