IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
5/06/2010
1
2Mx18, 1Mx36
36Mb QUADP (Burst 2) Synchronous SRAM
(2.0 CYCLE READ LATENCY)
FEATURES
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with EARLY write
operation.
Double Data Rate (DDR) interface for read and
write input ports.
2.0 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
Data valid pin (QVLD).
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte Write capability.
Fine ball grid array (FBGA) package option:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
ODT (On Die Termination) feature is supported
optionally on data input, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options.
IS61QDP2B21M36A : No ODT
IS61QDP2B21M36A1 : Option1
IS61QDP2B21M36A2 : Option2
Refer to more detail description at page 6 for each
ODT option.
DESCRIPTION
The 36Mb IS61QDP2B21M36A/A1/A2 and
IS61QDP2B22M18A/A1/A2 are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the Timing Reference
Diagram for Truth Table for a description of the basic
operations of these QUADP (Burst of 2) SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Read and write performed in double data rate.
The following are registered internally on the rising edge of
the K clock:
Read address
Read enable
Write enable
Data-in for early writes
The following are registered on the rising edge of the K#
clock:
Write address
Byte writes
Data-in for second burst addresses
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered half a cycle
earlier than the write address. The first data-in burst is
clocked at the same time as the write command signal, and
the second burst is timed to the following rising edge of the
K# clock.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the second rising
edge of the K# clock (starting two cycles later after read
command). The data-outs from the second bursts are
updated with the third rising edge of the K clock. The K and
K# clocks are used to time the data-outs.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interface.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
ADVANCED INFORMATION
SEPTEMBER 2010
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
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Package ballout and description
x36 FBGA Ball Configuration (Top View)
1 2 3 4 5 6 7 8 9 10 11
A CQ# NC/SA1 NC/SA1 W# BW2# K# BW1# R# SA NC/SA1 CQ
B Q27 Q18 D18 SA BW3# K BW0# SA D17 Q17 Q8
C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8
D D28 D20 Q19 VSS V
SS V
SS V
SS V
SS Q16 D15 D7
E Q29 D29 Q20 VDDQ V
SS V
SS V
SS V
DDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ V
DD V
SS V
DD V
DDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ V
DD V
SS V
DD V
DDQ Q13 D13 D5
H Doff# VREF V
DDQ V
DDQ V
DD V
SS V
DD V
DDQ V
DDQ V
REF ZQ
J D31 Q31 D23 VDDQ V
DD V
SS V
DD V
DDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ V
DD V
SS V
DD V
DDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ V
SS V
SS V
SS V
DDQ D11 Q11 Q2
M D33 Q34 D25 VSS V
SS V
SS V
SS V
SS D10 Q1 D2
N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1
P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0
R TDO TCK SA SA SA ODT SA SA SA TMS TDI
Notes:
1. The following balls are reserved for higher densities: 3A for 72M, 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Ball Configuration (Top View)
1 2 3 4 5 6 7 8 9 10 11
A CQ# NC/SA1 SA W# BW1# K# NC/SA1R# SA NC/SA1 CQ
B NC Q9 D9 SA NC K BW0# SA NC NC Q8
C NC NC D10 VSS SA SA SA VSS NC Q7 D8
D NC D11 Q10 VSS V
SS V
SS V
SS V
SS NC NC D7
E NC NC Q11 VDDQ V
SS V
SS V
SS V
DDQ NC D6 Q6
F NC Q12 D12 VDDQ V
DD V
SS V
DD V
DDQ NC NC Q5
G NC D13 Q13 VDDQ V
DD V
SS V
DD V
DDQ NC NC D5
H Doff# VREF V
DDQ V
DDQ V
DD V
SS V
DD V
DDQ V
DDQ V
REF ZQ
J NC NC D14 VDDQ V
DD V
SS V
DD V
DDQ NC Q4 D4
K NC NC Q14 VDDQ V
DD V
SS V
DD V
DDQ NC D3 Q3
L NC Q15 D15 VDDQ V
SS V
SS V
SS V
DDQ NC NC Q2
M NC NC D16 VSS V
SS V
SS V
SS V
SS NC Q1 D2
N NC D17 Q16 VSS SA SA SA VSS NC NC D1
P NC NC Q17 SA SA QVLD SA SA NC D0 Q0
R TDO TCK SA SA SA ODT SA SA SA TMS TDI
Notes:
1. The following balls are reserved for higher densities: 10A for 72M, 2A for 144Mb, and 7A for 288Mb.
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
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Ball Description
Symbol Type Description
K, K# Input
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising
edges. These balls cannot remain VREF level.
CQ, CQ# Output
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals are free
running clocks and do not stop when Q tri-states.
Doff# Input
DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one clock read latency mode when the DLL is turned off. In this mode,
the device can be operated at a frequency of up to 167 MHz.
QVLD Output
Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ#.
SA Input
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
D0 - Dn Input
Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of
individual signals.
The x18 device uses D0~D17. D18~D35 should be treated as NC pin.
The x36 device uses D0~D35.
Q0 - Qn Output
Synchronous data outputs: Output data is synchronized to the respective CQ and CQ#, or to the
respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.
The x36 device uses Q0~Q35.
W# Input
Synchronous write: When low, this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
R# Input
Synchronous read: When low, this input causes the address inputs to be registered and a READ
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
BWx# Input
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and #K for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
VREF Input
reference HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
VDD Power Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
VDDQ Power
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and
Operating Conditions for range.
VSS Ground Ground of the device
ZQ Input
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum
impedance mode. This ball cannot be connected directly to VSS or left unconnected.
In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.
The ODT range is selected by ODT control input.
TMS, TDI, TCK Input IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG
function is not used in the circuit.
TDO Output
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not
used in the circuit.
NC N/A
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
ODT Input ODT control; Refer to SRAM features for the details.
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
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SRAM Features description
Block Diagram
Data
Register
Address
Register
Control
Logic
D (Data-In)
36 (18)
20 (21)
Address
4 (2)
R#
W#
BWx#
Clock
Generator
Doff#
K
K#
2M x 36
(4M x 18)
Memory Array
Write
Driver
Address Decoder
Sense Amplifiers
Select Output Control
Output
Register
19 (20)
72 (36) 72 (36)
72 (36)
72 (36)
72 (36)
72(36)
Output Select
36 (18)
Q (Data-out)
QVLD
CQ, CQ#
(Echo Clocks)
2
Output Driver
36 (18)
QVLD
CQ, CQ#
(Echo Clocks)
2
Note: Numerical values in parentheses refer to the x18 device configuration.
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R# in active low state
at the rising edge of the K clock. R# can be activated every other cycle because two full cycles are required to
complete the burst of two in DDR mode. A set of free-running echo clocks, CQ and CQ#, are produced internally with
timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
The data corresponding to the first address is clocked two cycles later by the rising edge of the K clock. The data
corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock.
A NOP operation (R# is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every rising edge of the K clock with first data whenever W# is low. The write
address is provided half cycle with second data later, registered by the rising edge of K#, so the write always occurs in
bursts of two.
The write data is provided in an ‘early write’ mode; that is, the data-in corresponding to the first address of the burst, is
presented half cycle before the rising edge of the following K clock. The data-in corresponding to the second write
burst address follows next, registered by the rising edge of K#.
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array
on the third write cycle. A read cycle to the last write address produces data from the write buffers. Similarly, a read
address followed by the same write address produces the latest write data. The SRAM maintains data coherency.
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
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During a write, the byte writes independently control which byte of any of the four burst addresses is written (see
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table).
Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250 results in a driver impedance of 50. The allowable range of RQ to guarantee
impedance matching is between 175 and 350 at VDDQ=1.5V. The RQ resistor should be placed less than two inches
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never be
connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances
value. The final impedance value is achieved within 1024 clock cycles.
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending
read and write transactions are always completed prior to deselecting the corresponding port.
Valid Data Indicator (QVLD)
A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with
the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle
before the final valid read data arrives.
Delay Locked Loop (DLL)
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with one clock cycle latency and a longer access time which is known in DDR-I or legacy
QUAD mode.
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
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ODT (On Die Termination)
On Die Termination (ODT) is a feature that allows a SRAM to change input resistive termination condition by ODT pin
which function can have three status, High, Low, and Floating. Each status can have different ODT termination value
that tracks the value of RQ (Refer to the table of Fig1) and ODT of QUADP is always turned on during the read and
write function after ODT level to connect with ODT resistor is forced.
Fig1. Functional representation of ODT
Notes
1. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175<RQ<350.
2. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175<RQ<250.
3. ODT control pin is connected to VDDQ through 3.5k. Therefore it is recommended to connect it to VSS
through less than 100 to make it low.
4. ODT control pin is connected to VSS through 3.5k. Therefore it is recommended to connect it to VDDQ
through less than 100 to make it high.
ODT PIN
For option1 case, low input level of ODT pin can select strong (RQ1) input termination range (175<RQ<350) and
high input level of ODT pin can select weak (RQ2) input termination range (175<RQ<250) with K, K#, D0 to Dn,
BWx# and if ODT pin is on floating condition, it set weak (RQ2) input termination range which ODT pin is connected by
pull-up resistor internally. For option2 case, high input level of ODT pin can select weak (RQ2) input termination
range (175<RQ<250) with D0 to Dn, BWx# and low input level or floating of ODT pin can select disable of the ODT
function.
R1 R2 R3
Option13 0.3x
RQ1
0.6x
RQ2
0.6x
RQ2
Option24 ODT
disable
0.6x
RQ2
ODT
disable
SRAM In/Out Buffer
PAD
ODT=L
ODT=L
ODT=H
ODT=H
ODT=Floating
ODT=Floating
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
R1x2
R1x2
R2x2
R2x2
R3x2
R3x2
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
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Power-Up and Power-Down Sequences
The recommendation of voltage apply sequence is : VDD VDDQ
1)VREF
2) VIN
Notes:
1) VDDQ can be applied concurrently with VDD.
2) VREF can be applied concurrently with VDDQ.
After power and clock signals are stabilized, device can be ready for normal operation after tKC-Lock cycles. In tKC-
lock cycle period, device initializes internal logics and locks DLL. Depending on /Doff status, locking DLL will be
skipped. The following timing pictures are possible examples of power up sequence.
Sequence1. /Doff is fixed low
After tKC-lock cycle of stable clock, device is ready for normal operation.
Power On stage Unstable Clock Period Stable Clock period Read to use
K
K#
VDD
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
Sequence2. /Doff is controlled and goes high after clock being stable.
Power On stage Unstable Clock Period Stable Clock period Read to use
K
K
#
Doff#
VDD
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
>tKC-lock for device initialization
>tKC-lock for device initialization
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Sequence3. /Doff is controlled but goes high before clock bein g stable.
Because DLL has a risk to be locked with the unstable clock, DLL needs to be reset and locked with the stable input.
a) K-stop to reset. If K or K# stays at VIH or VIL for more than 30nS, DLL will be reset and ready to re-lock. In tKC-
Lock period, DLL will be locked with a new stable value. Device can be ready for normal operation after that.
Power On stage Unstable Clock Period K-Stop Stable Clock period Read to use
K
K#
Doff#
VDD
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
a) /Doff Low to reset. If /Doff toggled low to high, DLL will be reset and ready to re-lock. In tKC-Lock period, DLL will
be locked with a new stable value. Device can be ready for normal operation after that.
Power On stage Unstable Clock Period Doff reset DLL Stable Clock period Read to use
K
K
#
Doff#
VDD
VDDQ
VREF
VIN
Note) Applying DLL reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off.
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
>30nS >tKC-lock for device initialization
>tDoffLowToReset
>tKC-lock for device
initialization
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
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Application Example
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
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State Diagram
Power-Up
Read NOP Write NOP
Load New Read
Address
Load New Write
Address
DDR Read DDR Write
Read# Write#
Read Write
Read Write
Always
(fixed)
Always
(fixed)
Write#Read#
Notes:
1. Internal burst counter is fixed as two-bit linear; that is when first address is A0+0, next internal burst addresses are A0+1.
2. Read refers to read active status with R# = LOW. Read# refers to read inactive status with R# = HIGH.
3. Write refers to write active status with W# = LOW. Write# refers to write inactive status with W# = HIGH.
4. The read and write state machines can be active simultaneously.
5. State machine control timing sequence is controlled by K.
IS61QDP2B22M18A/A1/A2
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Timing Reference Diagram for Truth Table
The Timing Reference Dia gram for Truth Table is helpful in understanding the Clock and Write Truth Table s, as it
shows the cycle relationship between clocks, address, data in, data out, and control signals. Read command is issued
at the beginning of cycle “t”. Write command is issued at the beginning of cycle “t+1”.
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Clock Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Mode Clock Controls Data In Data Out
K R# W# DB D
B+1 Q
A Q
A+1
Stop Clock Stop X X Previous State Previous State Previous State Previous State
No Operation (NOP) L H H H X X High-Z High-Z
Read A L H L X X X DOUT at K# (t+2.0) DOUT at K (t+2.5)
Write B L H X L DIN at K (t) DIN at K# (t+0.5) X X
Notes:
1. Internal burst counter is always fixed as two-bit.
2. X = “don’t care”; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R is active low
4. A write operation is started when control signal W is active low.
5. Before entering into stop clock, all pending read and write must be completed.
6. Consecutive read or write operations can be started only at every other K clock rising edge. If two read or write operations are issued in
consecutive K clock rising edges, the second one will be ignored.
7. If both R# and W# are active low after a NOP operation, the write operation will be ignored.
8. For timing definitions, refer to the AC Timing Characteristics table. Signals must meet AC specifications at timings indicated in parenthesis with
respect to switching clocks K, K#.
x18 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation K (t) K# (t+0.5) BW0# BW1# DB D
B+1
Write Byte 0 L H L H D0-8 (t)
Write Byte 1 L H H L D9-17 (t)
Write All Bytes L H L L D0-17 (t)
Abort Write L H H H Don't Care
Write Byte 0 L H L H D0-8 (t+0.5)
Write Byte 1 L H H L D9-17 (t+0.5)
Write All Bytes L H L L D0-17 (t+0.5)
Abort Write L H H H Don't Care
Notes:
1. Refer to the Timing Reference Diagram for Truth Table. Cycle time starts at n and is referenced to the K clock.
2. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
3. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
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x36 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation K (t) K# (t+0.5) BW0# BW1# BW2# BW3# DB D
B+1
Write Byte 0 L H L H H H D0-8 (t)
Write Byte 1 L H H L H H D9-17 (t)
Write Byte 2 L H H H L H D18-26 (t)
Write Byte 3 L H H H H L D27-35 (t)
Write All Bytes L H L L L L D0-35 (t)
Abort Write L H H H H H Don't Care
Write Byte 0 L H L H H H D0-8 (t+0.5)
Write Byte 1 L H H L H H D9-17 (t+0.5)
Write Byte 2 L H H H L H D18-26
(t+0.5)
Write Byte 3 L H H H H L D27-35
(t+0.5)
Write All Bytes L H L L L L D0-35 (t+0.5)
Abort Write L H H H H H Don't Care
Notes:
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
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Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Min Max Units
Power Supply Voltage VDD 0.5 2.9 V
I/O Power Supply Voltage VDDQ 0.5 2.9 V
DC Input Voltage VIN 0.5 VDD+0.3 V
Data Out Voltage VDOUT 0.5 2.6 V
Junction Temperature TJ - 110 °C
Storage Temperature TSTG 55 +125 °C
Note:
Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Operating Temperature Range
Temperature Range Symbol Min Max Units
Commercial TA 0 +70 °C
Industrial TA 40 +85 °C
DC Electrical Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%)
Paramete
r
Symbol Min Max Units Notes
x36 Average Power Supply Operating Current
(IOUT=0, VIN=VIH or VIL )
IDD30
IDD33
IDD40
1200
1100
1000
mA 1, 2
x18 Average Power Supply Operating Current
(IOUT=0, VIN=VIH or VIL )
IDD30
IDD33
IDD40
1150
1050
950
mA 1, 2
Power Supply Standby Current
(R#=VIH, W#=VIH. All other inputs=VIH or VIL, IIH=0)
ISB30
ISB33
ISB40
290
280
270
mA 1,2
Input leakage current
( 0 VINVDDQ for all input balls except VREF, ZQ, TCK,
TMS, TDI ball)
ILI 2 +2 µA 3,4
Output leakage current
(0 VOUT VDDQ for all output balls except TDO ball; Output
must be disabled.)
ILO 2 +2 µA
Output “high” level voltage (IOH=100uA, Nominal ZQ) VOH VDDQ
0.2 VDDQ V
Output “low” level voltage (IOH= 100uA, Nominal ZQ) VOL V
SS V
SS+0.2 V
Notes:
1. IOUT = chip output current.
2. The numeric suffix indicates the part operating at speed, as indicated in AC Timing Characteristics table (that is, IDD25 indicates 2.5ns cycle
time).
3. ODT must be disabled.
4. Balls with ODT and DOFF# do not follow this spec, ILI = ±5uA.
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Recommended DC Operating Conditions
(Over the Operating Temperature Range)
Parameter Symbol Min Typical Max Units Notes
Supply Voltage VDD 1.8–5% 1.8 1.8+5% V 1
Output Driver Supply Voltage VDDQ 1.4 1.5 VDD V 1
Input High Voltage VIH V
REF+0.1 - VDDQ+0.2 V 1, 2
Input Low Voltage VIL –0.2 - VREF –0.1 V 1, 3
Input Reference Voltage VREF 0.68 0.75 0.95 V 1, 5
Clock Signal Voltage VIN-CLK –0.2 - VDDQ+0.2 V 1, 4
Notes:
1. All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.
2. VIH(max) AC = See 0vershoot and Undershoot Timings.
3. VIL(min) AC = See 0vershoot and Undershoot Timings.
4. VIN-CLK specifies the maximum allowable DC excursions of each clock (K and K#).
5. Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.
Overshoot and Undershoot Timings
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Typical AC Input Characteristics
Parameter Symbol Min Max Units Notes
AC Input Logic HIGH VIH (AC) VREF+0.2 V 1, 2, 3, 4
AC Input Logic LOW VIL (AC) VREF–0.2 V 1, 2, 3, 4
Clock Input Logic HIGH VIH-CLK (AC) VREF+0.2 V 1, 2, 3
Clock Input Logic LOW VIL-CLK (AC) VREF–0.2 V 1, 2, 3
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. Performance is a function of VIH and VIL levels to clock inputs.
3. See the AC Input Definition diagram.
4. See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past
VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only.
AC Input Definition
K#
VREF
K
VRAIL
VIH(AC)
VREF
VIL(AC)
V-RAIL
Setup Time Hold Time
PBGA Thermal Characteristics
Parameter Symbol Rating Units
Thermal resistance from junction to ambient (airflow = 1m/s) RJA TBD °C/W
Thermal resistance from junction to pins RJB TBD °C/W
Thermal resistance from junction to case RJC TBD °C/W
1. Note: these parameters are guaranteed by design and tested by a sample basis only.
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Pin Capacitance
Parameter Symbol Test Condition Max Units
Input or output capacitance except D and Q pins CIN ,CO
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ =
1.5V
5 pF
D and Q capacitance (D0–Dx, Q0-Qx) CDQ 6 pF
Clocks Capacitance (K, K, C, C) CCLK 4 pF
2. Note: these parameters are guaranteed by design and tested by a sample basis only.
Programmable Impedance Output Driver DC Electrical Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter Symbol Min Max Units Notes
Output Logic HIGH Voltage VOH V
DDQ /2 -0.12 VDDQ /2 + 0.12 V 1, 3
Output Logic LOW Voltage VOL V
DDQ /2 -0.12 VDDQ /2 + 0.12 V 2, 3
Notes:
1. For 175 RQ 350:
5
RQ
2
V
|I|
DDQ
OH
2. For 175RQ 350:
5
RQ
2
V
|I|
DDQ
OL
3. Parameter Tested with RQ=250 and VDDQ=1.5V
AC Test Conditions
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter Symbol Conditions Units Notes
Output Drive Power Supply Voltage VDDQ 1.5/1.8 V
Input Logic HIGH Voltage VIH V
REF+0.5 V
Input Logic LOW Voltage VIL V
REF–0.5 V
Input Reference Voltage VREF 0.75/0.9 V
Input Rise Time TR 2 V/ns
Input Fall Time TF 2 V/ns
Output Timing Reference Level VREF V
Clock Reference Level VREF V
Output Load Conditions 1, 2
Notes:
1. See AC Test Loading.
2. Parameter Tested with RQ=250 and VDDQ=1.5V
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AC Test Loading
(a) Unless otherwise noted, AC test loading assume this condition.
(b) tCHQZ and tCHQX1 are specified with 5pF load capacitance and measured when transition occurs ±100mV from
the steady state voltage.
(c)TDO
VREF
Test Comparator
Output
50
20pF
50
VREF
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AC Timing Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter Symbol
25 (400MHz) 30 (330MHz) 33 (300MHz) 40 (250MHz) Units Notes
Min Max Min Max Min Max Min Max
Clock
Clock Cycle Time (K, K#) tKHKH 2.5 8.40 3.00 8.4 3.3 8.4 4.00 8.4 ns
Clock Phase Jitter (K, K#) tKC var 0.2 0.3 0.3 0.3 ns 4
Clock High Time (K, K#) tKHKL 0.4 0.4 0.4 0.4 cycle
Clock Low Time (K, K#) tKLKH 0.4 0.4 0.4 0.4 cycle
Clock to Clock# (K, K#) tKHK#H 1.13 1.35 1.50 1.80 ns
DLL Lock Time (K) tKC lock 2048 2048 2048 2048 cycles 5
Doff Low period to DLL reset tDoffLowToReset 5 5 5 5 ns
K static to DLL reset tKCreset 30 30 30 30 ns
Output Times
K, K# High to Output Valid tCHQV 0.45 0.45 0.45 0.45 ns
K, K# High to Output Hold tCHQX -0.45 -0.45 -0.45 -0.45 ns
K, K# High to Echo Clock Valid tCHCQV 0.45 0.45 0.45 0.45 ns
K, K# High to Echo Clock Hold tCHCQX -0.45 -0.45 -0.45 -0.45 ns
CQ, CQ# High to Output Valid tCQHQV 0.20 0.30 0.30 0.30 ns 6
CQ, CQ# High to Output Hold tCQHQX -0.20 -0.30 -0.30 -0.30 ns 6
K, High to Output High-Z tCHQZ 0.45 0.45 0.45 0.45 ns
K, High to Output Low-Z tCHQX1 -0.45 -0.45 -0.45 -0.45 ns
CQ, CQ# High to QVLD Valid tQVLD -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns
Setup Times
Address valid to K rising edge tAVKH 0.40 0.40 0.40 0.40 ns
R#,W# control inputs valid to K
rising edge tIVKH 0.40
0.40
0.40 0.40
ns 2
BWx# control inputs valid to K rising
edge tIVKH2 0.28
0.30
0.30 0.30
ns 2
Data-in valid to K, K# rising edge tDVKH 0.28 0.30 0.30 0.30 ns
Hold Times
K rising edge to address hold tKHAX 0.40 0.40 0.40 0.40 ns 2
K rising edge to R#,W# control
inputs hold tKHIX 0.40 0.40 0.40 0.40 ns 2
K rising edge to BWx# control inputs
hold tKHIX2 0.28 0.30 0.30 0.30 ns
K, K# rising edge to data-in hold tKHDX 0.28 0.30 0.30 0.30 ns
Notes:
1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R#, W#, BW0#, BW1# and (BW2#, BW3# for x36)
3. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70 C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
6. The data sheet parameters reflect tester guard bands and test setup variations.
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READ, WRITE, AND NOP TIMING DIAGRAM
K Clock
K# Clock
Address
(SA)
R#
W#
BWx#
Data-In
(D)
1234567
tKHKH
tKHKL
tKHK#H
tAVKH tKHAX
tIVKH tKHIX
Data-Out
(Q)
Undefined Don’t Care
READ WRITE NOP
READ WRITE READ WRITE WRITE
tIVKH tKHIX
D2-1 D2-2 D4-1 D4-2
tDVKH tKHDX
D6-1 D6-2 D7-1 D7-2
A1 A2 A3 A4 A5 A6 A7
B2-1 B2-2 B4-1 B4-2 B6-1 B6-2 B7-1 B7-2
CQ Clock
CQ# Clock
tQVLD
tQVLD
tCQHQV
tCHCQX
tCHCQV
tCQHQX
tCHQX1
tCHQV tCHQZ
Q1-3
Q1-2
Q1-1 Q1-4 Q3-2Q3-1
tCHQX
QVLD
Notes:
1. If address A1 = A2, data Q1-1 = D2-1 and data Q1-2 = D2-2. Write data is forwarded immediately as read results.
2. B2-1 and B2-2 refer to all BWx# byte controls for D2-1 and D2-2 respectively.
3. B4-1 and B4-2 refer to all BWx# byte controls for D4-1 and D4-2 respectively.
4. B6-1 and B6-2 refer to all BWx# byte controls for D6-1 and D6-2 respectively.
5. B7-1 and B7-2 refer to all BWx# byte controls for D7-1 and D7-2 respectively.
6. Outputs are disabled one cycle after a NOP.
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IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed circuit
board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal is
not required
Disabling the JTAG feature
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS)
to prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device
will come up in a reset state, which will not interfere with device operation.
Test Access Port Signal List:
1. Test Clock (TCK)
This signal uses VDD as a power supply. The test clock is used only with the TAP controller. All inputs are captured on
the rising edge of TCK. All outputs are driven from the falling edge of TCK.
2. Test Mode Select (TMS)
This signal uses VDD as a power supply. The TMS input is used to send commands to the TAP controller and is
sampled on the rising edge of TCK.
3. Test Data-In (TDI)
This signal uses VDD as a power supply. The TDI input is used to serially input test instructions and information into
the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen
by the instruction that is loaded into the TAP instruction register. TDI is connected to the most significant bit (MSB) of
any register. For more information regarding instruction register loading, please see the TAP Controller State Diagram.
4. Test Data-Out (TDO)
This signal uses VDDQ as a power supply. The TDO output ball is used to serially clock test instructions and data out
from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states. In all
other states, the TDO pin is in a High-Z state. The output changes on the falling edge of TCK. TDO is connected to the
least significant bit (LSB) of any register. For more information, please see the TAP Controller State Diagram.
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TAP Controller State and Block Diagram
TAP Controller State Machine
Test Logic
Reset
Select DR
Run Test
Idle
0
11
Capture
DR
0
1
0
0
1
0
1
1
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
1
1
Update
DR
0
Select IR 1
Capture
IR
0
1
0
0
1
0
1
Shift IR
Exit1 IR
Pause IR
Exit2 IR
1
1
Update IR
0
0 0
10 10
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Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the
TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
1. Instruction Register
This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as
described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs are loaded with a
binary “01” pattern to allow for fault isolation of the board-level serial test data path.
2. Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be
shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is
executed.
3. Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several balls are also
included in the scan register to reserved balls. The boundary scan register is loaded with the contents of the SRAM
Input and Output ring when the TAP controller is in the capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the shift-DR state. Each bit corresponds to one of the balls on the SRAM
package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
4. Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command
is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP
controller is in the shift-DR state.
Scan Register Sizes Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 109
TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP
Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be used.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
1. EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells
at output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first test
vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
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instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on, and the PRELOAD data is
driven onto the output balls.
2. IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places
the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when
the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-
up or whenever the TAP controller is given a test logic reset state.
3. SAMPLE Z
If the SAMPLE-Z instruction is loaded in the instruction register, all SRAM outputs are forced to an inactive drive state
(high-Z), moving the TAP controller into the capture-DR state loads the data in the SRAMs input into the boundary
scan register, and the boundary scan register is connected between TDI and TDO when the TAP controller is moved
to the shift-DR state.
4. SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the
capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the SRAM
clock operates significantly faster. Because there is a large difference between the clock frequencies, it is possible that
during the capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal
while in transition. This will not harm the device, but there is no guarantee as to the value that will be captured.
Repeatable results may not be possible. To ensure that the boundary scan register will capture the correct value of a
signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time. The
SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a
SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out
the data by putting the TAP into the shift-DR state. This places the boundary scan register between the TDI and TDO
balls.
6. BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass
register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a board.
7. PRIVATE
Do not use these instructions. They are reserved for future use and engineering mode.
JTAG DC Operating Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%)
Parameter Symbol Min Max Units Notes
JTAG Input High Voltage VIH1 1.3 VDD+0.3 V
JTAG Input Low Voltage VIL1 –0.3 0.5 V
JTAG Output High Voltage VOH1 1.4 - V |IOH1|=2mA
JTAG Output Low Voltage VOL1 - 0.4 V IOL1=2mA
JTAG Output High Voltage VOH2 1.6 - V |IOH2|=100uA
JTAG Output Low Voltage VOL2 - 0.2 V IOL2=100uA
JTAG Input Leakage Current ILIJTAG -5 +5 A 0 Vin VDD
JTAG Output Leakage Current ILOJTAG -5 +5 A 0 Vout VDD
Notes:
1. All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
2. In “EXTEST” mode and “SAMPLE” mode, VDDQ is nominally 1.5 V.
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JTAG AC Test Conditions
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter Symbol Conditions Units
Input Pulse High Level VIH1 1.3 V
Input Pulse Low Level VIL1 0.5 V
Input Rise Time TR1 1.0 ns
Input Fall Time TF1 1.0 ns
Input and Output Timing Reference Level 0.9 V
JTAG AC Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter Symbol Min Max Units
TCK cycle time tTHTH 50 – ns
TCK high pulse width tTHTL 20 – ns
TCK low pulse width tTLTH 20 – ns
TMS Setup tMVTH 5 – ns
TMS Hold tTHMX 5 – ns
TDI Setup tDVTH 5 – ns
TDI Hold tTHDX 5 – ns
TCK Low to Valid Data* tTLOV – 10 ns
Note: See AC Test Loading(c)
JTAG Timing Diagram
TCK
TMS
tTHTH
tTHTL tTLTH
tTHMX
tMVTH
TDI
TDO
tTLOV
tTHDX
tDVTH
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Instruction Set
Code Instruction TDO Output Notes
000 EXTEST Boundary Scan Register 2, 6
001 IDCODE 32-bit Identification Register
010 SAMPLE-Z Boundary Scan Register 1, 2
011 PRIVATE Do Not Use 5
100 SAMPLE(/PRELOAD) Boundary Scan Register 4
101 PRIVATE Do Not Use 5
110 PRIVATE Do Not Use 5
111 BYPASS Bypass Register 3
Notes:
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when
exiting the shift-DR state.
4. SAMPLE instruction does not place Qs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high, Q will be
updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is
loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.
ID Register Definition
Revision Number (31:29) Part Configuration (28:12) JEDEC Code (11:1) Start Bit (0)
000 00DEF0WX01PQLB0S0 00011010101 1
Part Configuration Definition:
1. DEF = 010 for 36Mb
2. WX = 11 for x36, 10 for x18
3. P = 1 for II+(QUADP/DDR-IIP), 0 for II(QUAD/DDR-II)
4. Q = 1 for QUAD, 0 for DDR-II
5. L = 1 for RL=2.5, 0 for RL≠2.5
6. B = 1 for burst of 4, 0 for burst of 2
7. S = 1 for Separate I/O, 0 for Common I/O
LIST OF IEEE 1149.1 STANDARD VIOLATIONS
7.2.1.b, e
7.7.1.a-f
10.1.1.b, e
10.7.1.a-d
6.1.1.d
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
5/06/2010
27
Boundary Scan Exit Order
ORDER Pin ID ORDER Pin ID ORDER Pin ID
1 6R 37 10D 73 2C
2 6P 38 9E 74 3E
3 6N 39 10C 75 2D
4 7P 40 11D 76 2E
5 7N 41 9C 77 1E
6 7R 42 9D 78 2F
7 8R 43 11B 79 3F
8 8P 44 11C 80 1G
9 9R 45 9B 81 1F
10 11P 46 10B 82 3G
11 10P 47 11A 83 2G
12 10N 48 10A 84 1H
13 9P 49 9A 85 1J
14 10M 50 8B 86 2J
15 11N 51 7C 87 3K
16 9M 52 6C 88 3J
17 9N 53 8A 89 2K
18 11L 54 7A 90 1K
19 11M 55 7B 91 2L
20 9L 56 6B 92 3L
21 10L 57 6A 93 1M
22 11K 58 5B 94 1L
23 10K 59 5A 95 3N
24 9J 60 4A 96 3M
25 9K 61 5C 97 1N
26 10J 62 4B 98 2M
27 11J 63 3A 99 3P
28 11H 64 2A 100 2N
29 10G 65 1A 101 2P
30 9G 66 2B 102 1P
31 11F 67 3B 103 3R
32 11G 68 1C 104 4R
33 9F 69 1B 105 4P
34 10F 70 3D 106 5P
35 11E 71 3C 107 5N
36 10E 72 1D 108 5R
109 Internal
Notes:
1. NC pins as defined on the FBGA Ball Assignments are read as ”Don’t Cares”.
2. State of internal pin (#109) is loaded via JTAG
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
5/06/2010
28
Ordering Information
Commercial Range: 0°C to +70°C
Speed Order Part No. Organization Package
333 MHz IS61QDP2B21M36A-333M3 1Mx36 165 FBGA (15x17 mm)
IS61QDP2B21M36A-333M3L 1Mx36 165 FBGA (15x17 mm), lead free
IS61QDP2B22M18A-333M3 2Mx18 165 FBGA (15x17 mm)
IS61QDP2B22M18A-333M3L 2Mx18 166 FBGA (15x17 mm), lead free
300 MHz IS61QDP2B21M36A-300M3 1Mx36 165 FBGA (15x17 mm)
IS61QDP2B21M36A-300M3L 1Mx36 165 FBGA (15x17 mm), lead free
IS61QDP2B22M18A-300M3 2Mx18 165 FBGA (15x17 mm)
IS61QDP2B22M18A-300M3L 2Mx18 165 FBGA (15x17 mm), lead free
250 MHz IS61QDP2B21M36A-250M3 1Mx36 165 FBGA (15x17 mm)
IS61QDP2B21M36A-250M3L 1Mx36 165 FBGA (15x17 mm), lead free
IS61QDP2B22M18A-250M3 2Mx18 165 FBGA (15x17 mm)
IS61QDP2B22M18A-250M3L 2Mx18 165 FBGA (15x17 mm), lead free
Commercial Range: 0°C to +70°C
Speed Order Part No. Organization Package
333 MHz IS61QDP2B21M36A-333B4 1Mx36 165 FBGA (13x15 mm)
IS61QDP2B21M36A-333B4L 1Mx36 165 FBGA (13x15 mm), lead free
IS61QDP2B22M18A-333B4 2Mx18 165 FBGA (13x15 mm)
IS61QDP2B22M18A-333B4L 2Mx18 166 FBGA (13x15 mm), lead free
300 MHz IS61QDP2B21M36A-300B4 1Mx36 165 FBGA (13x15 mm)
IS61QDP2B21M36A-300B4L 1Mx36 165 FBGA (13x15 mm), lead free
IS61QDP2B22M18A-300B4 2Mx18 165 FBGA (13x15 mm)
IS61QDP2B22M18A-300B4L 2Mx18 165 FBGA (13x15 mm), lead free
250 MHz IS61QDP2B21M36A-250B4 1Mx36 165 FBGA (13x15 mm)
IS61QDP2B21M36A-250B4L 1Mx36 165 FBGA (13x15 mm), lead free
IS61QDP2B22M18A-250B4 2Mx18 165 FBGA (13x15 mm)
IS61QDP2B22M18A-250B4L 2Mx18 165 FBGA (13x15 mm), lead free
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
5/06/2010
29
Industrial Range: -40°C to +85°C
Speed Order Part No. Organization Package
333 MHz IS61QDP2B21M36A-333M3I 1Mx36 165 FBGA (15x17 mm)
IS61QDP2B21M36A-333M3LI 1Mx36 165 FBGA (15x17 mm), lead free
IS61QDP2B22M18A-333M3I 2Mx18 165 FBGA (15x17 mm)
IS61QDP2B22M18A-333M3LI 2Mx18 165 FBGA (15x17 mm), lead free
300 MHz IS61QDP2B21M36A-300M3I 1Mx36 165 FBGA (15x17 mm)
IS61QDP2B21M36A-300M3LI 1Mx36 165 FBGA (15x17 mm), lead free
IS61QDP2B22M18A-300M3I 2Mx18 165 FBGA (15x17 mm)
IS61QDP2B22M18A-300M3LI 2Mx18 165 FBGA (15x17 mm), lead free
250 MHz IS61QDP2B21M36A-250M3I 1Mx36 165 FBGA (15x17 mm)
IS61QDP2B21M36A-250M3LI 1Mx36 165 FBGA (15x17 mm), lead free
IS61QDP2B22M18A-250M3I 2Mx18 165 FBGA (15x17 mm)
IS61QDP2B22M18A-250M3LI 2Mx18 165 FBGA (15x17 mm), lead free
Industrial Range: -40°C to +85°C
Speed Order Part No. Organization Package
333 MHz IS61QDP2B21M36A-333B4I 1Mx36 165 FBGA (13x15 mm)
IS61QDP2B21M36A-333B4LI 1Mx36 165 FBGA (13x15 mm), lead free
IS61QDP2B22M18A-333B4I 2Mx18 165 FBGA (13x15 mm)
IS61QDP2B22M18A-333B4LI 2Mx18 165 FBGA (13x15 mm), lead free
300 MHz IS61QDP2B21M36A-300B4I 1Mx36 165 FBGA (13x15 mm)
IS61QDP2B21M36A-300B4LI 1Mx36 165 FBGA (13x15 mm), lead free
IS61QDP2B22M18A-300B4I 2Mx18 165 FBGA (13x15 mm)
IS61QDP2B22M18A-300B4LI 2Mx18 165 FBGA (13x15 mm), lead free
250 MHz IS61QDP2B21M36A-250B4I 1Mx36 165 FBGA (13x15 mm)
IS61QDP2B21M36A-250B4LI 1Mx36 165 FBGA (13x15 mm), lead free
IS61QDP2B22M18A-250B4I 2Mx18 165 FBGA (13x15 mm)
IS61QDP2B22M18A-250B4LI 2Mx18 165 FBGA (13x15 mm), lead free
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
5/06/2010
30
Package drawing – 15x17x1.4 BGA
NOTE :
1. Controlling dimension : mm
Package Outline
12/10/2007
IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1/A2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
5/06/2010
31
Package drawing – 13x15x1.4 BGA
