KAD2708C-17Q68 - Intersil Corporation

FN6812.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

KAD2708C

8-Bit, 275/210/170/105MSPS A/D Converter

The KAD2708C is the industry’s lowest power, 8-bit,

275MSPS, high performance Analog-to-Digital converter. It

is designed with Intersil’s proprietary FemtoCharge™

technology on a standard CMOS process. The KAD2708C

offers high dynamic performance (49.2dBFS SNR @

fIN = 138MHz) while consuming less than 265mW. Features

include an over-range indicator and a selectable divide-by-2

input clock divider. The KAD2708C is one member of a

pin-compatible family offering 8 and 10-bit ADCs with

sample rates from 105MSPS to 350MSPS and LVCMOS or

LVDS-compatible outputs (Table 1). This family of products

is available in 68-pin RoHS-compliant QFN packages with

exposed paddle. Performance is specified over the full

industrial temperature range (-40°C to +85°C).

Features

• On-Chip Reference

• Internal Track and Hold

•1.5V

P-P Differential Input Voltage

• 600MHz Analog Input Bandwidth

• Two’s Complement or Binary Output

• Over-Range Indicator

• Selectable ÷2 Clock Input

• LVCMOS Outputs

Applications

• High-Performance Data Acquisition

• Portable Oscilloscope

• Medical Imaging

• Cable Head Ends

• Power-Amplifier Linearization

• Radar and Satellite Antenna Array Processing

• Broadband Communications

• Point-to-Point Microwave Systems

• Communications Test Equipment

Key Specifications

• SNR of 49.2dBFS at fS = 275MSPS, fIN = 138MHz

• SFDR of 66.6dBc at fS = 275MSPS, fIN = 138MHz

• Power Consumption ≤ 265mW at fS = 275MSPS

Pin-Compatible Family

Ordering Information

PART NUMBER

SPEED

(MSPS)

TEMP.

RANGE (°C) PACKAGE PKG. DWG. #

KAD2708C-27Q68 275 -40 to +85 68 Ld QFN L68.10x10B

KAD2708C-21Q68 210 -40 to +85 68 Ld QFN L68.10x10B

KAD2708C-17Q68 170 -40 to +85 68 Ld QFN L68.10x10B

KAD2708C-10Q68 105 -40 to +85 68 Ld QFN L68.10x10B

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-

free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS

compliant and compatible with both SnPb and Pb-free soldering

operations). Intersil Pb-free products are MSL classified at Pb-free

peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

2. For Moisture Sensitivity Level (MSL), please see device information

page for KAD2708C-10, KAD2708C-17, KAD2708C-21 and

KAD2708C-27. For more information on MSL please see techbrief

TB363.

LVCMOS

Drivers

1.21 V

Clock

Generation

S/H

INP

INN

8-bit

275MSPS

ADC

CLK_P

CLK_N

OVSS

AVSS

AVDD2

CLKOUT

D7 – D0

2SC

OVDD

CLKDIV

–

AVDD3

VREF

VREFSEL

VCM

TABLE 1. PIN-COMPATIBLE PRODUCTS

RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS

8 Bits 350MSPS KAD2708L-35

10 Bits 275MSPS KAD2710L-27 KAD2710C-27

8 Bits 275MSPS KAD2708L-27 KAD2708C-27

10 Bits 210MSPS KAD2710L-21 KAD2710C-21

8 Bits 210MSPS KAD2708L-21 KAD2708C-21

10 Bits 170MSPS KAD2710L-17 KAD2710C-17

8 Bits 170MSPS KAD2708L-17 KAD2708C-17

10 Bits 105MSPS KAD2710L-10 KAD2710C-10

8 Bits 105MSPS KAD2708L-10 KAD2708C-10

Data Sheet April 14, 2011

2FN6812.1

April 14, 2011

Table of Contents

Absolute Maximum Ratings ........................................ 3

Thermal Information ..................................................... 3

Electrical Specifications .............................................. 3

Digital Specifications ................................................... 4

Timing Diagram ............................................................ 6

Timing Specifications .................................................. 6

ESD ................................................................................ 6

Pin Descriptions ........................................................... 7

Pin Configuration ......................................................... 8

Typical Performance Curves ....................................... 9

Functional Description ................................................ 12

Reset ......................................................................... . 12

Voltage Reference ..................................................... . 12

Analog Input .............................................................. .12

Clock Input ................................................................. . 13

Jitter ........................................................................... . 13

Digital Outputs ........................................................... .14

Equivalent Circuits ....................................................... 14

Layout Considerations ................................................ 15

Split Ground and Power Planes ................................ . 15

Clock Input Considerations ........................................ . 15

Bypass and Filtering .................................................. . 15

LVCMOS Outputs ...................................................... . 15

Unused Inputs ........................................................... . 15

Definitions ..................................................................... 15

Package Outline Drawing ............................................ 16

KAD2708C

3FN6812.1

April 14, 2011

Absolute Maximum Ratings Thermal Information

AVDD2 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V

AVDD3 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V

OVDD2 to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V

Analog Inputs to AVSS. . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V

Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD2 + 0.3V

Logic Inputs to AVSS (VREFSEL, CLKDIV) -0.4V to AVDD3 + 0.3V

Logic Inputs to OVSS (RST, 2SC) . . . . . . . . -0.4V to OVDD2 + 0.3V

VREF to AVSS . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V

Analog Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Logic Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

CMOS Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Thermal Resistance (Typical, Notes 3, 4) θJA (°C/W) θJC (°C/W)

68 Ld QFN Package. . . . . . . . . . . . . . . 23 1.8

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,

OVDD = 1.8V, TA= -40°C to +85°C (typical specifications at +25°C), fSAMPLE = 275MSPS, 210MSPS, 170MSPS and

105MSPS, fIN = Nyquist at -0.5dBFS. Boldface limits apply over the operating temperature range, -40°C to

+85°C.

PARAMETER SYMBOL CONDITIONS

KAD2708C-27 KAD2708C-21 KAD2708C-17 KAD2708C-10

UNITS

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

DC SPECIFICATIONS

Analog Input

Full-Scale Analog

Input Range

VFS 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 VP-P

Full Scale Range

Tem p . D r ift

AVTC Full Temp 230 210 198 178 ppm/°C

Common-Mode

Output Voltage

VCM 860 860 860 860 mV

Power Requirements

1.8V Analog

Supply Voltage

AVDD2 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

3.3V Analog

Supply Voltage

AVDD3 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 V

1.8V Digital

Supply Voltage

OVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

1.8V Analog

Supply Current

IAVDD2 44 51 38 42 35 39 29 33 mA

3.3V Analog

Supply Current

IAVDD3 41 45 33 37 28 32 21 24 mA

1.8V Digital

Supply Current

IOVDD 26 30 25 28 24 27 23 26 mA

Power

Dissipation

PD261 294 222 248 199 224 163 185 mW

AC SPECIFICATIONS

Maximum

Conversion Rate

fS MAX 275 210 170 105 MSPS

KAD2708C

4FN6812.1

April 14, 2011

Minimum

Conversion Rate

fS MIN 50 50 50 50 MSPS

Differential

Nonlinearity

DNL -0.3 ±0.2 0.4 -0.3 ±0.2 0.4 -0.3 ±0.2 0.4 -0.3 ±0.2 0.4 LSB

Integral

Nonlinearity

INL -0.8 ±0.2 0.8 -0.8 ±0.2 0.8 -0.8 ±0.2 0.8 -0.8 ±0.2 0.8 LSB

Signal-to-Noise

Ratio

SNR fIN = 10MHz 49.5 49.5 49.5 49.5 dBFS

fIN = Nyquist 46.5 49.2 46.5 49.2 46.5 49.2 46.5 49.2 dBFS

fIN = 430MHz 49.0 49.1 49.1 49.1 dBFS

Signal-to-Noise

and Distortion

SINAD fIN = 10MHz 49.2 49.5 49.5 49.5 dBFS

fIN = Nyquist 46.5 49.2 46.5 49.2 46.5 49.2 46.5 49.2 dBFS

fIN = 430MHz 48.9 48.9 49.0 48.9 dBFS

Effective Number

of Bits

ENOB fIN = 10MHz 7.9 7.9 7.9 7.9 Bits

fIN = Nyquist 7.4 7.9 7.4 7.9 7.4 7.9 7.4 7.9 Bits

fIN = 430MHz 7.8 7.8 7.8 7.8 Bits

Spurious-Free

Dynamic Range

SFDR fIN = 10MHz 67.6 69.1 69.1 69.1 dBc

fIN = Nyquist 61 66.6 61 69.1 61 69.1 61 69.1 dBc

fIN = 430MHz 66.1 69.0 69.0 68.9 dBc

Two-Tone SFDR 2TSFDR fIN = 133MHz,

135MHz

63 65 65 65 dBc

Word Error Rate WER 10-12 10-12 10-12 10-12

Full Power

Bandwidth

FPBW 600 600 600 600 MHz

NOTE:

5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,

OVDD = 1.8V, TA= -40°C to +85°C (typical specifications at +25°C), fSAMPLE = 275MSPS, 210MSPS, 170MSPS and

105MSPS, fIN = Nyquist at -0.5dBFS. Boldface limits apply over the operating temperature range, -40°C to

+85°C. (Continued)

PARAMETER SYMBOL CONDITIONS

KAD2708C-27 KAD2708C-21 KAD2708C-17 KAD2708C-10

UNITS

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

Digital Specifications

PARAMETER SYMBOL CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

INPUTS

High Input Voltage (VREFSEL) VREFSEL VIH 0.8*AVDD3 V

Low Input Voltage (VREFSEL) VREFSEL VIL 0.2*AVDD3 V

Input Current High (VREFSEL) VREFSEL IIH VIN = AVDD3 0 1 10 µA

Input Current Low (VREFSEL) VREFSEL IIL VIN = AVSS 25 65 75 µA

High Input Voltage (CLKDIV) CLKDIV VIH 0.8*AVDD3 V

Low Input Voltage (CLKDIV) CLKDIV VIL 0.2*AVDD3 V

Input Current High (CLKDIV) CLKDIV IIH VIN = AVDD3 25 65 75 µA

Input Current Low (CLKDIV) CLKDIV IIL VIN = AVSS 0 1 10 µA

High Input Voltage (RST,2SC) RST,2SC VIH 0.8*OVDD2 V

Low Input Voltage (RST,2SC) RST,2SC VIL 0.2*OVDD2 V

Input Current High (RST,2SC) RST,2SC IIH VIN = OVDD 0 1 10 µA

KAD2708C

5FN6812.1

April 14, 2011

Input Current Low (RST,2SC) RST,2SC IIL VIN = OVSS 25 50 75 µA

Input Capacitance CDI 3pF

CLKP, CLKN P-P Differential

Input Voltage

VCDI 0.5 3.6 VP-P

CLKP, CLKN Differential Input

Resistance

RCDI 10 MΩ

CLKP, CLKN Common-Mode

Input Voltage

VCCI 0.9 V

LVCMOS OUTPUTS

Voltage Output High VOH 1.8 V

Voltage Output Low VOL 0V

Output Rise Time tR1.8 ns

Output Fall Time tF1.4 ns

NOTE:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Digital Specifications (Continued)

PARAMETER SYMBOL CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

KAD2708C

6FN6812.1

April 14, 2011

ESD

Electrostatic charge accumulates on humans, tools and

equipment and may discharge through any metallic package

contacts (pins, balls, exposed paddle, etc.) of an integrated

circuit. Industry-standard protection techniques have been

utilized in the design of this product. However, reasonable

care must be taken in the storage and handling of ESD

sensitive products. Contact Intersil for the specific ESD

sensitivity rating of this product.

Timing Diagram

FIGURE 1. LVCMOS TIMING DIAGRAM

INP

INN

CLKP

CLKN

CLKOUT

D[7:0]

tPID

tPCD

Data N-L

Sample N

Data N

invalid

tPH

Data N-L+1

Timing Specifications

PARAMETER SYMBOL

MIN

(Note 7) TYP

MAX

(Note 7) UNITS

Aperture Delay tA1.7 ns

RMS Aperture Jitter jA200 fs

Input Clock to Data Propagation Delay tPID 3.5 5.0 6.5 ns

Data Hold Time tPH -300 ps

Output Clock to Data Propagation Delay tPCD 2.8 3.7 ns

Latency (Pipeline Delay) L 28 cycles

Overvoltage Recovery tOVR 1cycle

NOTE:

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

KAD2708C

7FN6812.1

April 14, 2011

Pin Descriptions

PIN NUMBER NAME FUNCTION

1, 14, 18, 20 AVDD2 1.8V Analog Supply

2, 7, 10, 19, 21, 24 AVSS Analog Supply Return

3 VREF Reference Voltage Out/In

4 VREFSEL Reference Voltage Select (0:Int 1:Ext)

5 VCM Common-Mode Voltage Output

6, 15, 16, 25 AVDD3 3.3V Analog Supply

8, 9 INP, INN Analog Input Positive, Negative

11-13, 29-36, 37, 39, 42, 46, 48,

50, 52, 54, 56, 58, 62, 63, 67

DNC Do Not Connect

17 CLKDIV Clock Divide by Two (Active Low)

22, 23 CLKN, CLKP Clock Input Complement, True

26, 45, 61 OVSS Output Supply Return

27, 41, 44, 60 OVDD2 1.8V CMOS Supply

28 RST Power On Reset (Active Low)

38 D0 LVCMOS Bit 0 (LSB) Output

40 D1 LVCMOS Bit 1 Output

43 CLKOUT LVCMOS Clock Output

47 D2 LVCMOS Bit 2 Output

49 D3 LVCMOS Bit 3 Output

51 D4 LVCMOS Bit 4 Output

53 D5 LVCMOS Bit 5 Output

55 D6 LVCMOS Bit 6 Output

57 D7 LVCMOS Bit 7 Output

59 OR Over-Range

64-66 Connect to OVDD2

68 2SC Two’s Complement Select (Active Low)

Exposed Paddle AVSS Analog Supply Return

KAD2708C

8FN6812.1

April 14, 2011

Pin Configuration

2SC

DNC

OVDD2

DNC

OVSS

OVDD2

DNC

AVDD2

AVSS

AVDD2

AVSS

CLKN

CLKP

AVSS

AVDD3

OVSS

OVDD2

RST

DNC

AVDD2

AVSS

VREF

VREFSEL

VCM

AVDD3

AVSS

INP

INN

AVSS

DNC

AVDD2

AVDD3

CLKDIV

KAD2708C

Top V iew

N o t to Sc a le

DNC

OVSS

OVDD2

CLKOUT

DNC

OVDD2

DNC

68 Q FN

FIGURE 2. PIN CONFIGURATION

KAD2708C

9FN6812.1

April 14, 2011

Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,

AIN = -0.5dBFS unless noted.

FIGURE 3. SNR AND SFDR vs fIN FIGURE 4. HD2 AND HD3 vs fIN

FIGURE 5. SNR AND SFDR vs AIN FIGURE 6. HD2 AND HD3 vs AIN

FIGURE 7. SNR AND SFDR vs fSAMPLE FIGURE 8. HD2 AND HD3 vs fSAMPLE

5 105 205 305 405 505

fIN (M Hz)

SNR(dBFS), SFDR(d

SFDR

SNR

(dBc)

-90

-85

-80

-75

-70

-65

-60

-55

-50

5 10 5 205 305 405 505

fIN(MHz)

HD2, HD3(dB

HD3

HD2

(dBc)

-30 -25 -20 -15 -10 -5 0

AIN (dBFS)

SNR (dBFS), SFDR (

SFDR

SNR

(dBc)

-80

-70

-60

-50

-40

-30

-20

-30-25-20-15-10 -5 0

Input Amplitude (dBFS)

HD2, HD3 dB

HD3

HD2

(dBc)

50 100 150 200 250 300 350

fSA MP LE (fS) (MSPS)

SNR(dBFS), SFDR (dBc)

SFDR

SNR

-90

-85

-80

-75

-70

-65

50 100 150 200 250 300 350

fSAMPLE

(MHz)

HD2, HD3(dBc)

HD3

HD2

KAD2708C

10 FN6812.1

April 14, 2011

FIGURE 9. POWER DISSIPATION vs fSAMPLE FIGURE 10. DIFFERENTIAL NONLINEARITY vs OUTPUT CODE

FIGURE 11. INTEGRAL NONLINEARITY vs OUTPUT CODE FIGURE 12. NOISE HISTOGRAM

FIGURE 13. OUTPUT SPECTRUM @ 9.865MHz FIGURE 14. OUTPUT SPECTRUM @ 133.805MHz

Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,

AIN = -0.5dBFS unless noted. (Continued)

100

120

140

160

180

200

220

240

260

280

50 100 150 200 250 300

fSAMPLE (fS) (MSPS)

Power Dissipation (PD) (mW)

032 64 96 128 160 192 224 255

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

CODE

DNL (LSBs)

032 64 96 12 8 160 192 224 255

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

CODE

INL (L SBs)

124 125 126 127 128 129 130

5,000

10,000

15,000

20,000

25,000

30,000

35,000

40,000

45,000

50,000

CODE

CODE COUNT

020 40 60 80 100 120

-120

-100

-80

-60

-40

-20

FREQUENC Y (M Hz)

AMPLITUDE (dB)

Ain = -0.47dBFS

SNR = 49.4dBFS

SFDR = 68.4dBc

SINAD = 49.3dBFS

HD2 = -86dBc

HD3 = -69dBc

020 40 60 80 100 120

-120

-100

-80

-60

-40

-20

FREQUENCY (MHz)

AMPLITUDE (dB)

Ain = -0.47dBFS

SNR = 49.4dBFS

SFDR = 69.2dBc

SINAD = 49.4dBFS

HD2 = -81dBc

HD3 = -91dBc

KAD2708C

11 FN6812.1

April 14, 2011

FIGURE 15. OUTPUT SPECTRUM @ 299.645MHz FIGURE 16. TWO-TONE SPECTRUM @ 69MHz, 70MHz

FIGURE 17. TWO-TONE SPECTRUM @ 140MHz, 141MHz FIGURE 18. TWO-TONE SPECTRUM @ 300MHz, 305MHz

FIGURE 19. SNR AND SFDR vs TEMPERATURE FIGURE 20. CALIBRATION TIME vs fS

Typical Performance Curves AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,

AIN = -0.5dBFS unless noted. (Continued)

020 40 60 80 100 120

-120

-100

-8 0

-6 0

-4 0

-2 0

FREQUENCY (MHz)

AMPL ITUDE (dB)

Ain = -0.48dBFS

SNR = 49.3dB FS

SFDR = 63dBc

SINAD = 49.1dBFS

HD2 = - 63 dB c

HD3 = - 67 dB c

020 40 60 80 10 0 12 0

-120

-100

-8 0

-6 0

-4 0

-2 0

FREQUENCY (MHz)

AMPLITUDE (dB)

Ain = -7.1dBFS

2TSFDR = 67dBc

IMD3 = -74dBF S

020 40 60 80 100 12 0

-120

-100

-80

-60

-40

-20

FREQUENCY (MHz)

AMPLITUDE (dB)

Ain = -7dBFS

2TSFDR = 73dBc

IMD3 = -8 1dBFS

020 40 60 80 100 120

-120

-100

-8 0

-6 0

-4 0

-2 0

FREQUENCY (MHz)

AMPLITUDE (dB)

A in = -7dBFS

2TSFDR = 63dBc

IMD3 = -76dBFS

-40-200 20406080

AMBIENT TEMPERATURE, C

SNR(dBFS), SFDR(dBc

)

SFDR

SNR

200

300

400

500

600

700

800

100 125 150 175 200 225 250 27

fSAMPLE (fS) (MSPS)

tCAL (ms)

KAD2708C

12 FN6812.1

April 14, 2011

Functional Description

The KAD2708 is an 8-bit, 275MSPS A/D converter in a

pipelined architecture. The input voltage is captured by a

sample & hold circuit and converted to a unit of charge.

Proprietary charge domain techniques are used to compare

the input to a series of reference charges. These

comparisons determine the digital code for each input value.

The converter pipeline requires 24 sample clocks to produce

a result. Digital error correction is also applied, resulting in a

total latency of 28 clock cycles. This is evident to the user as

a latency between the start of a conversion and the data

being available on the digital outputs.

At start-up, a self-calibration is performed to minimize gain

and offset errors. The reset pin (RST) is initially held low

internally at power-up and will remain in that state until the

calibration is complete. The clock frequency should remain

fixed during this time.

Calibration accuracy is maintained for the sample rate at

which it is performed, and therefore should be repeated if the

clock frequency is changed by more than 10%. Recalibration

can be initiated via the RST pin, or power cycling, at any

time.

Reset

Recalibration of the ADC can be initiated at any time by

driving the RST pin low for a minimum of one clock cycle. An

open-drain driver is recommended.

The calibration sequence is initiated on the rising edge of

RST, as shown in Figure 21. The over-range output (OR) is

set high once RST is pulled low, and remains in that state

until calibration is complete. The OR output returns to

normal operation at that time, so it is important that the

analog input be within the converter’s full-scale range in

order to observe the transition. If the input is in an

over-range state the OR pin will stay high and it will not be

possible to detect the end of the calibration cycle.

While RST is low, the output clock (CLKOUT) stops toggling

and is set low. Normal operation of the output clock resumes

at the next input clock edge (CLKP/CLKN) after RST is de-

asserted. At 275MSPS the nominal calibration time is

~240ms.

Voltage Reference

The VREF pin is the full-scale reference, which sets the

full-scale input voltage for the chip and requires a bypass

capacitor of 0.1µF or larger. An internally generated

reference voltage is provided from a bandgap voltage buffer.

This buffer can sink or source up to 50µA externally.

An external voltage may be applied to this pin to provide a

more accurate reference than the internally generated

bandgap voltage or to match the full-scale reference among

a system of KAD2708C chips. One option in the latter

configuration is to use one KAD2708C's internally generated

reference as the external reference voltage for the other

chips in the system. Additionally, an externally provided

reference can be changed from the nominal value to adjust

the full-scale input voltage within a limited range.

To select whether the full-scale reference is internally

generated or externally provided, the digital input port

VREFSEL should be set appropriately, low for internal or

high for external.This pin also has an internal 18kΩ pull-up

resistor. To use the internally generated reference,

VREFSEL can be tied directly to AVSS, and to use an

external reference, VREFSEL can be left unconnected.

Analog Input

The fully differential ADC input (INP/INN) connects to the

sample and hold circuit. The ideal full-scale input voltage is

1.5VPP

, centered at the VCM voltage of 0.86V as shown in

Figure 22.

Best performance is obtained when the analog inputs are

driven differentially in an AC-coupled configuration. The

common-mode output voltage, VCM, should be used to

properly bias each input as shown in Figures 23 and 24. An

RF transformer will give the best noise and distortion

performance for wideband and/or high intermediate

frequency (IF) inputs. The recommended biasing is shown in

Figures 23 and 24.

FIGURE 21. CALIBRATION TIMING

CLKP

CLKN

CLKOUT

RST

Calibration Begins

Calibration Complete

Calibration Time

FIGURE 22. ANALOG INPUT RANGE

1.0

1.8

0.6

0.2

1.4 INP INN

VCM

0.86V

0.75V

-0.75V

KAD2708C

13 FN6812.1

April 14, 2011

A back-to-back transformer scheme is used to improve

common-mode rejection, which keeps the common-mode

level of the input matched to VCM. The value of the

termination resistor should be determined based on the

desired impedance.

The sample and hold circuit design uses a switched

capacitor input stage, which creates current spikes when the

sampling capacitance is reconnected to the input voltage.

This creates a disturbance at the input which must settle

before the next sampling point. Lower source impedance will

result in faster settling and improved performance. Therefore

a 1:1 transformer and low shunt resistance are

recommended for optimal performance.

A differential amplifier can be used in applications that

require DC coupling, at the expense of reduced dynamic

performance. In this configuration the amplifier will typically

reduce the achievable SNR and distortion performance. A

typical differential amplifier configuration is shown in

Figure 25.

Clock Input

The clock input circuit is a differential pair (see Figure 29).

Driving these inputs with a high level (up to 1.8VPP on each

input) sine or square wave will provide the lowest jitter

performance. The recommended drive circuit is shown in

Figure 26. The clock can be driven single-ended, but this will

reduce the edge rate and may impact SNR performance.

Use of the clock divider is optional. The KAD2708C's ADC

requires a clock with 50% duty cycle for optimum

performance. If such a clock is not available, one option is to

generate twice the desired sampling rate, then use the

KAD2708C's divide-by-2 to generate a 50%-duty-cycle

clock. This frequency divider uses the rising edge of the

clock, so 50% clock duty cycle is assured. Table 2 describes

the CLKDIV connection.

CLKDIV is internally pulled low, so a pull-up resistor or logic

driver must be connected for undivided clock.

Jitter

In a sampled data system, clock jitter directly impacts the

achievable SNR performance. The theoretical relationship

between clock jitter and maximum SNR is shown in

Equation 1 and is illustrated in Figure 27.

Where tJ is the RMS uncertainty in the sampling instant.

This relationship shows the SNR that would be achieved if

clock jitter were the only non-ideal factor. In reality,

achievable SNR is limited by internal factors such as

differential nonlinearity, aperture jitter and thermal noise.

FIGURE 23. TRANSFORMER INPUT, GENERAL APPLICATION

ADT1-1WT

0.1µF

KAD2708

VCM

50O

0.01µF

Analog

ADT1-1WT

ADTL1-12

0.1µF

KAD2708

VCM

ADTL1-12

1nF

Analog

Input

25O

FIGURE 24. TRANSFORMER INPUT, HIGH IF APPLICATION

KAD2708

VCM

0.1µF

0.22µF

69.8O

49.9O

100O

69.8O

348O

151O

25O

Vin

FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT

TABLE 2. CLKDIV PIN SETTINGS

CLKDIV PIN DIVIDE RATIO

AVSS 2

AVDD 1

TC4-1W

1nF

AVDD2

200O

CLKP

CLKN

1kO 1kO

1nF

Clock

Input

FIGURE 26. RECOMMENDED CLOCK DRIVE

SNR 20 log10

2πfINtJ

--------------------

⎝⎠

⎛⎞

=(EQ. 1)

KAD2708C

14 FN6812.1

April 14, 2011

Any internal aperture jitter combines with the input clock

jitter, in a root-sum-square fashion since they are not

statistically correlated, and this determines the total jitter in

the system. The total jitter, combined with other noise

sources, then determines the achievable SNR.

Digital Outputs

Data is output on a parallel bus with LVDS-compatible

drivers.

The output format (Binary or Two’s Complement) is selected

via the 2SC pin as shown in Table 3.

tj = 1 00 p s

tj = 10 p s

tj = 1 p s

tj = 0. 1 p s

10 Bits

12 Bits

14 Bits

100

1101001000

Inp ut Frequency - MHz

SNR - d

FIGURE 27. SNR vs CLOCK JITTER TABLE 3. 2SC PIN SETTINGS

2SC PIN MODE

AVSS Two’s Complement

AVDD Binary

Equivalent Circuits

FIGURE 28. ANALOG INPUTS FIGURE 29. CLOCK INPUTS

FIGURE 30. LVCMOS OUTPUT

AVDD3

INP

INN

AVDD3

F1 F2

Csamp

0.3pF

Charge

Pipeline

2pF

Csamp

0.3pF

Charge

Pipeline

ΦΦ

AVDD2

CLKP

CLKN

AVDD2

To Clock

Generation

D[9:0]

OVDD

DATA

KAD2708C

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6812.1

April 14, 2011

Layout Considerations

Split Ground and Power Planes

Data converters operating at high sampling frequencies require

extra care in PC board layout. Many complex board designs

benefit from isolating the analog and digital sections. Analog

supply and ground planes should be laid out under signal and

clock inputs. Locate the digital planes under outputs and logic

pins. Grounds should be joined under the chip.

Clock Input Considerations

Use matched transmission lines to the inputs for the analog

input and clock signals. Locate transformers, drivers and

terminations as close to the chip as possible.

Bypass and Filtering

Bulk capacitors should have low equivalent series

resistance. Tantalum is a good choice. For best

performance, keep ceramic bypass capacitors very close to

device pins. Longer traces will increase inductance, resulting

in diminished dynamic performance and accuracy. Make

sure that connections to ground are direct and low

impedance.

LVCMOS Outputs

Output traces and connections must be designed for 50Ω

characteristic impedance. Avoid crossing ground and

power-plane breaks with signal traces.

Unused Inputs

The RST and 2SC inputs are internally pulled up, and can be

left open-circuit if not used.

CLKDIV is internally pulled low, which divides the input clock

by two.

VREFSEL is internally pulled up. It must be held low for internal

reference, but can be left open for external reference.

Definitions

Analog Input Bandwidth is the analog input frequency at

which the spectral output power at the fundamental

frequency (as determined by FFT analysis) is reduced by

3dB from its full-scale low-frequency value. This is also

referred to as Full Power Bandwidth.

Aperture Delay or Sampling Delay is the time required

after the rise of the clock input for the sampling switch to

open, at which time the signal is held for conversion.

Aperture Jitter is the RMS variation in aperture delay for a

set of samples.

Clock Duty Cycle is the ratio of the time the clock wave is at

logic high to the total time of one clock period.

Differential Non-Linearity (DNL) is the deviation of any

code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB) is an alternate method of

specifying Signal to Noise-and-Distortion Ratio (SINAD). In

dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02.

Integral Non-Linearity (INL) is the deviation of each individual

code from a line drawn from negative full-scale (1/2 LSB below

the first code transition) through positive full-scale (1/2 LSB

above the last code transition). The deviation of any given code

from this line is measured from the center of that code.

Least Significant Bit (LSB) is the bit that has the smallest

value or weight in a digital word. Its value in terms of input

voltage is VFS/(2N - 1) where N is the resolution in bits.

Missing Codes are output codes that are skipped and will

never appear at the ADC output. These codes cannot be

reached with any input value.

Most Significant Bit (MSB) is the bit that has the largest

value or weight. Its value in terms of input voltage is VFS/2.

Pipeline Delay is the number of clock cycles between the

initiation of a conversion and the appearance at the output

pins of the corresponding data.

Power Supply Rejection Ratio (PSRR) is the ratio of a

change in power supply voltage to the input voltage

necessary to negate the resultant change in output code.

Signal to Noise-and-Distortion (SINAD) is the ratio of the

RMS signal amplitude to the RMS sum of all other spectral

components below one half the clock frequency, including

harmonics but excluding DC.

Signal-to-Noise Ratio (SNR) (without Harmonics) is the

ratio of the RMS signal amplitude to the RMS sum of all

other spectral components below one-half the sampling

frequency, excluding harmonics and DC.

Spurious-Free-Dynamic Range (SFDR) is the ratio of the

RMS signal amplitude to the RMS value of the peak spurious

spectral component. The peak spurious spectral component

may or may not be a harmonic.

Two-Tone SFDR is the ratio of the RMS value of either input

tone to the RMS value of the peak spurious component. The

peak spurious component may or may not be an IMD product.

KAD2708C

16 FN6812.1

April 14, 2011

KAD2708C

Package Outline Drawing

L68.10x10B

68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 11/08

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSEY14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.

NOTES:

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

BOTTOM VIEW

C0 . 2 REF

0 . 05 MAX.

0 . 00 MIN.

PIN 1

INDEX AREA

34 18

0.10 AMC B

4X 8.00

68X 0.55 68X 0.25

64X 0.50

10.00

0.90 Max

68X 0.25

68X 0.75

64X 0.50

7.70 Sq

9.65 Sq

PIN 1

INDEX AREA

Exp. DAP

7.70 Sq.

SEE DETAIL "X"

SEATING PLANE

0.08

0.10

8.00 Sq

(4X)

0.15

52 68