CYStech Electronics Corp. Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 1/9 Three Terminal Adjustable Output Positive Voltage Regulators PL317E3 The PL317E3 is an adjustable 3-terminal positive voltage regulator capable of supplying in excess of 1.5 A over an output voltage range of 1.2 V to 37 V. This voltage regulator is exceptionally easy to use and requires only two external resistors to set the output voltage. Further, it employs internal current limiting, thermal shutdown and safe area compensation, making it essentially blow-out proof. The PL317E3 serves a wide variety of applications including local, on-card regulation. This device can also be used to make a programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the PL317E3 can be used as a precision current regulator. Output Current in Excess of 1.5 A Output Adjustable between 1.2 V and 37 V Internal Thermal Overload Protection Internal Short Circuit Current Limiting Constant with Temperature Output Transistor Safe-Area Compensation Floating Operation for High Voltage Applications Eliminates Stocking many Fixed Voltages Standard Application Vin Cin 0.1F Vout PL317 + TO-220AB Cin is required if regulator is located an appreciate distance from power supply filter. Cout is not needed for stability, however, it does improve transient response. R1 IAdj + R2 Cout 1.0F Vout=1.25(1+R2/R1)+IAdjR2 Since IAdj is controlled to less than 100 A, the error associated with this term is negligible in most applications. Maximum Ratings Rating Input-Output Voltage Differential Power Dissipation TA=25 Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Operating Junction Temperature Range Storage Temperature Range PL317E3 Symbol VI-VO Value 40 Unit V PD JA JC TJ Tstg Internally Limited 65 5.0 -40 to +125 -65 to +150 W /W /W CYStek Product Specification CYStech Electronics Corp. Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 2/9 Electrical Characteristics(VI-VO=5V,IO=0.5A,TJ=0 to 125, unless otherwise noted) Characteristics Line Regulation(Note 1) Load Regulation(Note 1) Symbol Conditions Reg line TA=25,3.0VVI-VO40V Reg load TA=25,10mAIO1.5A VO5.0V VO5.0V Thermal Regulation(Note 4) Reg therm TA=25, 20ms pulse Adjust Pin Current IAdj 2.5VVI-VO40V,10mAIL1.5A Adjust Pin Current Change IAdj PD20W 3.0VVI-VO40V,10mAIO1.5A Reference Voltage Vref PD20W Temperature Stability Ts 0TJ125 Minimum Load Current to ILmin VI-VO=40V maintain Regulation Maximum Output Current Imax VI-VO15V,PD20W VI-VO40V,PD20W,TA=25 % of VO,TA=25,10Hzf10kHz RMS Noise N Ripple Rejection(Note 2) RR VO=10V,f=120Hz Without CAdj CAdj=10F Long-Term Stability(Note 3) S TJ=125,TA=25 for endpoint measurements Min - Typ 0.01 Max 0.04 Unit %/V - 5.0 0.1 0.03 50 0.2 25 0.5 0.07 100 5.0 mV %VO %VO/W A A 1.2 1.25 1.3 V - 0.7 3.5 10 %VO mA 1. 5 0.15 - 2.2 0.4 0.003 - A 66 - 65 80 0.3 1.0 %VO dB %/1.0k Hrs Notes:1.Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. 2.CAdj, when used, is connected between the adjustment pin and ground. 3.Since long-term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 4.Power dissipation within an IC voltage regulator produces a temperature gradient on the die, affecting individual IC components on the die. These effects can be minimized by proper integrated circuit design and layout techniques. Thermal regulation is the effect of these temperature gradients on the output voltage and is expressed in percentage of output change per watt of power change in a specified time. PL317E3 CYStek Product Specification Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 3/9 CYStech Electronics Corp. Representative Schematic Diagram Vin Vout Adjust VOH-VOL Line Regulation(%/V)= x100 VOL Vcc VIH VOH VIL Vin VOL Vout PL317 Pulse testing required 1% Duty Cycle is suggested Cin Adjust IAdj R1 1% Co + 1F RL 0.1F R2 1% Fig 1. Line Regulation and IAdj/Line test circuit PL317E3 CYStek Product Specification Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 4/9 CYStech Electronics Corp. Vin Vout VI IL PL317 Adjust * R1 1% IAdj Co + 1F Vo(max load) RL (min load) 0.1F Cin Vo(min load) RL (max load) R2 1% *Pulse testing required. 1% Duty Cycle is suggest Vo(min load)-Vo(max load) Load Regulation(mV)=Vo(min load)-Vo(max load) Load Regulation(%Vo)= x100 Vo(min load) Fig 2. Load Regulation and IAdj/Load test circuit Vin Vout IL PL317 Adjust R1 1% IAdj Cin Vref + 0.1F 1F Co RL Vo VI ISET R2 1% Pulse testing required. 1% Duty Cycle is suggested. To calculate R2: Vout=ISETR2+1.250V Assume ISET=5.25mA Fig 3. Standard Test Circuit PL317E3 CYStek Product Specification Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 5/9 CYStech Electronics Corp. Vin 24V Vout PL317 14V f=120Hz Adjust R1 1% D1 * 1N4002 + Cin 0.1F 1F Co RL Vout=10V Vo R2 1% CAdj + 10F * D1 Discharges CAdj if output is shorted to ground Fig 4. Ripple Rejection Test Circuit Application Information Basic Circuit Operation The PL317 is a 3-terminal floating regulator. In operation, the PL317 develops and maintains a nominal 1.25V reference (Vref) between its output and adjustment terminals. This reference voltage is converted to a programming current (Iprog) by R1(see Fig 5), and this constant current flows through R2 to ground. The regulated output voltage is given by: Vout=Vref(1+R2/R1)+IAdjR2 Since the current from the adjustment terminal (IAdj) represents an error term in the equation, the PL317 was designed to control IAdj to less than 100 A and keep it constant. To do this, all quiescent operating current is returned to the output terminal. This imposes the requirement for a minimum load current. If the load current is less than this minimum, the output voltage will rise. Since the PL317 is a floating regulator, it is only the voltage differential across the circuit which is important to performance, and operation at high voltages with respect to ground is possible. Vin Vout Vout PL317 Vref Adjust R1 Iprog IAdj R2 Vref=1.25V typical PL317E3 Fig 5. Basic Circuit Configuration CYStek Product Specification CYStech Electronics Corp. Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 6/9 Load Regulation The PL317 is capable of providing extremely good load regulation, but a few precautions are needed to obtain maximum performance. For best performance, the programming resistor (R1) should be connected as close to the regulator as possible to minimize line drops which effectively appear in series with the reference, thereby degrading regulation. The ground end of R2 can be returned near the load ground to provide remote ground sensing and improve load regulation. External Capacitors A 0.1F disc or 1.0F tantalum input bypass capacitor (Cin) is recommended to reduce the sensitivity to input line impedance. The adjustment terminal may be bypassed to ground to improve ripple rejection. This capacitor (CAdj) prevents ripple from being amplified as the output voltage is increased. A 10F capacitor should improve ripple rejection about 15 dB at 120 Hz in a 10V application. Although the PL317 is stable with no output capacitance, like any feedback circuit, certain values of external capacitance can cause excessive ringing. An output capacitance (Co) in the form of a 1.0F tantalum or 25F aluminum electrolytic capacitor on the output swamps this effect and insures stability. Protection Diodes When external capacitors are used with any IC regulator, it is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current points into the regulator. Fig 6 shows the PL317 with the recommended protection diodes for output voltages in excess of 25V or high capacitance values (Co>25F,CAdj>10F). Diode D1 prevents Co from discharging thru the IC during an input short circuit. Diode D2 protects against capacitor CAdj discharging through the IC during an output short circuit. The combination of diodes D1 and D2 prevents CAdj from discharging through the IC during an input short circuit. D1 Vin 1N4002 Vout PL317 Cin Adjust D2 1N4002 R1 + R2 Co CAdj Fig 6. Voltage Regulator with Protection Diodes PL317E3 CYStek Product Specification Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 7/9 CYStech Electronics Corp. Application Circuits D6* 1N4002 Vout Vin 32V to 40 V Vin 1 Vin 2 RSC PL317 PL317 (1) (2) Adjust 1 D1 1N4001 0.1F Current Limit Adjust 1.0k Iout Vout Vout 2 240 Adjust 2 D5 1N4001 + Voltage Adjust 5.0k D2 1N4001 Q1 2N3822 + 10F 1.0F Tantalum D3 Output Range:0Vo25V 1N4001 0Io1.5A D4 1N4001 -10V Q2 2N5640 Diodes D1 and D2 and transistor Q2 are added to allow adjustment of output voltage to 0V. * D6 protects both LM317's during an input short circuit. -10V Fig 7. "Laboratory" Power Supply with Adjustable Current Limit and Output Voltage +25V Vin Vout PL317 Adjust Iout R1 D1* 1.25 Vin R2 D1 1N4001 100 *To provide current limiting of Io to the system groung, the source of the FET must be tied to a negative voltage below -1.25V. 2N5640 D2 1N4001 R1=Vref/(Iomax+IDSS) R2Vref/IDSS Vo<BVDSS+1.25V+Vss ILmin-IDSS<Io<1.5A As shown 0<Io<1.0A Fig 8. Adjustable Current Limiter PL317E3 1N4002 Vout PL317 120 + Adjust 720 1.0F MPS2222 1.0k TTL Control *D1 protects the device during an input short circuit. Vss* Fig 9. 5.0V Electronic Shutdown Regulator CYStek Product Specification Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 8/9 CYStech Electronics Corp. Vin Vout PL317 Vin 240 Adjust 1N4001 50k Vout PL317 Adjust MPS2907 R2 + 10F Iout R1 IAdj Iout=(Vref/R1)+IAdj =1.25V/R1 10mAIout1.5A Fig 10. Slow Turn-on Regulator PL317E3 Fig 11. Current Regulator CYStek Product Specification CYStech Electronics Corp. Spec. No. : C513E3 Issued Date : 2003.04.09 Revised Date : . . Page No. : 9/9 TO-220AB Dimension Marking: B A D E C 317 H K M I 3 G N 2 3-Lead TO-220AB Plastic Package CYStek Package Code: E3 1 4 Style: Pin 1.Adj 2.Vout 3.Vin 4.Vout O P * : Typical Inches Min. Max. 0.2197 0.2949 0.3299 0.3504 0.1732 0.185 0.0453 0.0547 0.0138 0.0236 0.3803 0.4047 *0.6398 DIM A B C D E G H Millimeters Min. Max. 5.58 7.49 8.38 8.90 4.40 4.70 1.15 1.39 0.35 0.60 9.66 10.28 *16.25 DIM I K M N O P Inches Min. Max. *0.1508 0.0295 0.0374 0.0449 0.0551 *0.1000 0.5000 0.5618 0.5701 0.6248 Millimeters Min. Max. *3.83 0.75 0.95 1.14 1.40 *2.54 12.70 14.27 14.48 15.87 Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material: * Lead: 42 Alloy ; solder plating * Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0 Important Notice: * All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. * CYStek reserves the right to make changes to its products without notice. * CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. * CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. PL317E3 CYStek Product Specification