CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 1/9
PL317E3 CYStek Product Specification
Three Terminal Adjustable Output
Positive Voltage Regulators
PL317E3
The PL317E3 is an adjustable 3–terminal positive voltage regulator capable
of supplying in excess of 1.5 A over an output voltage range of 1.2 V to 37 V.
This voltage regulator is exceptionally easy to use and requires only two ex-
ternal resistors to set the output voltage. Further, it employs internal current
limiting, thermal shutdown and safe area compensation, making it essentially
blow–out proof.
The PL317E3 serves a wide variety of applications including local, on-card
regulation. This device can also be used to make a programmable output regu-
lator, or by connecting a fixed resistor between the adjustment and output, the
PL317E3 can be used as a precision current regulator.
Output Current in Excess of 1.5 A
Output Adjustable between 1.2 V and 37 V
Internal Thermal Overload Protection
Internal Short Circuit Current Limiting Constant with Temperature
Output Transistor Safe–Area Compensation
Floating Operation for High Voltage Applications
Eliminates Stocking many Fixed Voltages
Standard Application
+ +
PL317
R1
R2
CoutCin
Vin Vout
Maximum Ratings
Rating Symbol Value Unit
Input-Output Voltage Differential VI-VO 40 V
Power Dissipation
TA=25
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
PD
JA
JC
Internally Limited
65
5.0
W
/W
/W
Operating Junction Temperature Range TJ -40 to +125
Storage Temperature Range Tstg -65 to +150
TO-220AB
1.0µF 0.1µF
Cin is required if regulator is located an appreciate
distance from power supply filter.
**Cout is not needed for stability, however, it does
improve transient response.
Vout=1.25(1+R2/R1)+IAdjR2
Since IAdj is controlled to less than 100 µA, the
error associated with this term is negligible in
most applications.
IAdj
CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 2/9
PL317E3 CYStek Product Specification
Electrical Characteristics(VI-VO=5V,IO=0.5A,TJ=0 to 125, unless otherwise noted)
Characteristics Symbol Conditions Min Typ Max Unit
Line Regulation(Note 1) Reg line TA=25,3.0VVI-VO40V - 0.01 0.04 %/V
Load Regulation(Note 1) Reg
load TA=25,10mAIO1.5A
VO5.0V
VO5.0V
-
-
5.0
0.1
25
0.5
mV
%VO
Thermal Regulation(Note 4) Reg therm TA=25, 20ms pulse - 0.03 0.07 %VO/W
Adjust Pin Current IAdj - 50 100 µA
Adjust Pin Current Change IAdj 2.5VVI-VO40V,10mAIL1.5A
PD20W
- 0.2 5.0 µA
Reference Voltage Vref 3.0VVI-VO40V,10mAIO1.5A
PD20W
1.2 1.25 1.3 V
Temperature Stability Ts 0TJ125 - 0.7 - %VO
Minimum Load Current to
maintain Regulation
ILmin V
I-VO=40V - 3.5 10 mA
Maximum Output Current Imax VI-VO15V,PD20W
VI-VO40V,PD20W,TA=25
1. 5
0.15
2.2
0.4
-
-
A
RMS Noise N % of VO,TA=25,10Hzf10kHz - 0.003 - %VO
Ripple Rejection(Note 2) RR VO=10V,f=120Hz
Without CAdj
CAdj=10µF
-
66
65
80
-
-
dB
Long-Term Stability(Note 3) S TJ=125,TA=25 for endpoint
measurements
- 0.3 1.0 %/1.0k
Hrs
Notes:1.Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be
taken into account separately. Pulse testing with low duty cycle is used.
2.CAdj, when used, is connected between the adjustment pin and ground.
3.Since long-term stability cannot be measured on each device before shipment, this specification is an engineering
estimate of average stability from lot to lot.
4.Power dissipation within an IC voltage regulator produces a temperature gradient on the die, affecting individual IC
components on the die. These effects can be minimized by proper integrated circuit design and layout techniques.
Thermal regulation is the effect of these temperature gradients on the output voltage and is expressed in percentage
of output change per watt of power change in a specified time.
CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 3/9
PL317E3 CYStek Product Specification
Representative Schematic Diagram
Vin
Vout
Adjust
+
Vcc
Cin 0.1μF
IAdj
Adjust
Vin Vout
PL317
R2
1%
R1
1%
Co 1μFRL
VIL
VIH VO
H
VOL
Fig 1. Line Regulation and IAdj/Line test circuit
Pulse testing required
1% Duty Cycle is
suggested
VOH-VOL
Line Regulation(%/V)= ×100
VOL
CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 4/9
PL317E3 CYStek Product Specification
+
VI
Cin 0.1μF
IAdj
Adjust
Vin Vout
PL317
R2
1%
R1
1%
Co 1μFRL
IL
RL
(max load)
(min load)
*
Vo(min load
)
Vo(max load
)
*Pulse testing required.
1% Duty Cycle is sugges
t
+
Cin 0.1μF
IAdj
Adjust
Vin Vout
PL317
R2
1%
R1
1%
Co
1μFRL
IL
ISET
Vref
Vo
VI
Vo(min load)-Vo(max load)
Load Regulation(mV)=Vo(min load)-Vo(max load) Load Regulation(%Vo)= ×100
Vo(min load)
Fig 2. Load Regulation and IAdj/Load test circuit
Pulse testing required.
1% Duty Cycle is suggested.
To calculate R2: Vout=ISETR2+1.250V
Assume ISET=5.25mA
Fig 3. Standard Test Circuit
CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 5/9
PL317E3 CYStek Product Specification
+
Cin 0.1μF
Adjust
Vin Vout
PL317
R2
1%
R1
1%
Co
1μFRL
Vo
+
D1 *
CAdj 10μF
1N4002
Vout=10
V
* D1 Discharges CAdj if output is shorted to ground
24V
14V
f=120Hz
Application Information
Basic Circuit Operation
The PL317 is a 3-terminal floating regulator. In operation, the PL317 develops and maintains a nominal
1.25V reference (Vref) between its output and adjustment terminals. This reference voltage is converted
to a programming current (Iprog) by R1(see Fig 5), and this constant current flows through R2 to ground.
The regulated output voltage is given by:
Vout=Vref(1+R2/R1)+IAdjR2
Since the current from the adjustment terminal (IAdj) represents an error term in the equation, the PL317
was designed to control IAdj to less than 100 µA and keep it constant. To do this, all quiescent operating
current is returned to the output terminal. This imposes the requirement for a minimum load current. If
the load current is less than this minimum, the output voltage will rise.
Since the PL317 is a floating regulator, it is only the voltage differential across the circuit which is
important to performance, and operation at high voltages with respect to ground is possible.
R1
R2
Vout
Adjust
Vin Vout
IAdj
PL317
Iprog
Vref
Vref=1.25V typical
Fig 4. Ripple Rejection Test Circuit
Fig 5. Basic Circuit Configuration
CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 6/9
PL317E3 CYStek Product Specification
Load Regulation
The PL317 is capable of providing extremely good load regulation, but a few precautions are needed to
obtain maximum performance. For best performance, the programming resistor (R1) should be connected
as close to the regulator as possible to minimize line drops which effectively appear in series with the
reference, thereby degrading regulation. The ground end of R2 can be returned near the load ground to
provide remote ground sensing and improve load regulation.
External Capacitors
A 0.1µF disc or 1.0µF tantalum input bypass capacitor (Cin) is recommended to reduce the sensitivity to
input line impedance.
The adjustment terminal may be bypassed to ground to improve ripple rejection. This capacitor (CAdj)
prevents ripple from being amplified as the output voltage is increased. A 10µF capacitor should improve
ripple rejection about 15 dB at 120 Hz in a 10V application.
Although the PL317 is stable with no output capacitance, like any feedback circuit, certain values of
external capacitance can cause excessive ringing. An output capacitance (Co) in the form of a 1.0µF
tantalum or 25µF aluminum electrolytic capacitor on the output swamps this effect and insures stability.
Protection Diodes
When external capacitors are used with any IC regulator, it is sometimes necessary to add protection
diodes to prevent the capacitors from discharging through low current points into the regulator.
Fig 6 shows the PL317 with the recommended protection diodes for output voltages in excess of 25V or
high capacitance values (Co>25µF,CAdj>10µF). Diode D1 prevents Co from discharging thru the IC
during an input short circuit. Diode D2 protects against capacitor CAdj discharging through the IC during
an output short circuit. The combination of diodes D1 and D2 prevents CAdj from discharging through the
IC during an input short circuit.
R1
R2
Vout
Adjust
Vin
PL317
+C
o
CAdj
D2
D1
1N4002
Cin 1N4002
Fig 6. Voltage Regulator with Protection Diodes
CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 7/9
PL317E3 CYStek Product Specification
Application Circuits
+
+
-10V
-10V
Q2
2N5640
1N4001
D4
D3
Q1
2N3822
D2
D1
1N4001
1N4001
1N4001
1.0k 5.0k
RSC
D6*
1N4002
240 D5
10μF
1.0μF
Vout
Vout 2
Vin 2Vout
1N4001
Tantalum
Vin 1
Vin
32V to 40 V
0.1μF
Adjust 1
Current Limit Adjust
PL317 PL317
(1) (2)
Adjust 2
Iout
Voltage Adjust
Diodes D1 and D2 and transistor Q2 are added to
* D6 protects both LM317's during an input short circuit.
allow adjustment of output voltage to 0V.
Output Range:0Vo25V
0Io1.5A
Vss*
2N5640
D2
D1
1N400
1
1N400
1
100
R1
Vout
Vin
+25V
Adjust
PL317
Iout
1.25
R2
*To provide current limiting of Io to the system
groung, the source of the FET must be tied to a
negative voltage below -1.25V.
Fig 7. “Laboratory” Power Supply with Adjustable Current Limit and Output Voltage
R1=Vref/(Iomax+IDSS) R2Vref/IDSS
Vo <BVDSS+1.25V+Vss
ILmin-IDSS<Io<1.5A
As shown 0<Io<1.0A
Fig 8. Adjustable Current Limiter
+
PL317
Adjust
720 MPS2222
1.0k
TTL
Control
1.0μF
120
Vout
D1*
1N4002
Vin
*D1 protects the device during an input short circuit.
Fig 9. 5.0V Electronic Shutdown Regulator
CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 8/9
PL317E3 CYStek Product Specification
PL317
Adjust
R2
MPS2907
240
Vout
Vin
+10μF
50k 1N4001
Fig 10. Slow Turn-on Regulator
R1
Vout
Adjust
Vin Iout
IAdj
PL317
Iout=(Vref/R1)+IAdj
=1.25V/R1
10mAIout1.5A
Fig 11. Current Regulator
CYStech Electronics Corp.
Spec. No. : C513E3
Issued Date : 2003.04.09
Revised Date : . .
Page No. : 9/9
PL317E3 CYStek Product Specification
TO-220AB Dimension
*
: Typical
Inches Millimeters Inches Millimeters
DIM Min. Max. Min. Max.
DIM Min. Max. Min. Max.
A 0.2197 0.2949 5.58 7.49 I - *0.1508 - *3.83
B 0.3299 0.3504 8.38 8.90 K 0.0295 0.0374 0.75 0.95
C 0.1732 0.185 4.40 4.70 M 0.0449 0.0551 1.14 1.40
D 0.0453 0.0547 1.15 1.39 N - *0.1000 - *2.54
E 0.0138 0.0236 0.35 0.60 O 0.5000 0.5618 12.70 14.27
G 0.3803 0.4047 9.66 10.28 P 0.5701 0.6248 14.48 15.87
H -
*0.6398 - *16.25
Notes: 1.Controlling dimension: millimeters.
2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material.
3.If there is any question with packing specification or packing method, please contact your local CYStek sales office.
Material:
Lead: 42 Alloy ; solder plating
Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0
Important Notice:
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
CYStek reserves the right to make changes to its products without notice.
CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
AB
E
G
IK
M
O
P
3
2
1
C
N
H
D
4
Style: Pin 1.Adj 2.Vout 3.Vin
4.Vout
3-Lead TO-220AB Plastic Package
CYStek Package Code: E3
Marking:
317