Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.12
FUJITSU SEMICONDUCTOR
DATA SHEET DS405-00007-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL
ASSP for Power Management Applications
2ch DC/DC converter IC
with PFM/ PWM synchronous rectification
MB39A214A
DESCRIPTION
MB39A214A is a N-ch/ N-ch synchronous rectification type 2ch Buck DC/DC converter IC equipped with
a bottom detection comparator for low output voltage ripple. It supports low on-duty operation to allow
stable output of low voltages when there is a large difference between input and output voltages. It also
allows the high switching frequency setting, enabling the downsized peripheral circuits and low-cost
configuration. MB39A214A realizes ultra-rapid response and high efficiency with built-in enhanced
protection features. It is most suitable for the power supply for ASIC or FPGA core, input/output devices, or
memory.
FEATURES
y High efficiency
y Frequency setting by internal preset function : 310 kHz, 620 kHz, 1 MHz
y High accuracy reference voltage : ± 0.7% (Ta = + 25 °C)
y VIN Input voltage range : 6 V to 28 V
y Output voltage setting range : 0.7 V to 5.3 V
y Possible to select the automatic PFM/PWM selection mode or PWM-fixed mode
y PAF frequency limitation function (Prohibit Audio Frequency) : > 30 kHz (Min)
y Built-in boost diode, external fly-back diode not required
y Built-in discharge FET
y Built-in over voltage protection function
y Built-in under voltage protection function
y Built-in over temperature protection function
y Built-in over current limitation function
y Soft-start circuit without load dependence
y Current sense resistor not required
y Built-in synchronous rectification type output steps for N-ch MOS FET
y Standby current : 0 µA (Typ)
y Package : TSSOP24 (4.4 mm°6.5 mm°1.2 mm [Max])
APPLICATIONS
y Digital TV
y Photocopiers
y STB
y BD, DVD players/recorders
y Projectors etc.
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PIN ASSIGNMENT
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DRVH1
LX1
DRVL1
PGND
ILIM1
VCC
VB
MODE
ILIM2
DRVL2
LX2
DRVH
2
BST1
EN1
VOUT1
FB1
CS1
GND
FREQ
CS2
FB2
VOUT2
EN2
BST2
(FPT-24P-M09)
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PIN DESCRIPTIONS
Pin No. Pin Name I/O Description
1 BST1 CH1 boost capacitor connection pin.
2 EN1 I CH1 enable pin.
3 VOUT1 I CH1 input pin for DC/DC output voltage.
4 FB1 I CH1 input pin for feedback voltage.
5 CS1 I CH1 soft-start time setting capacitor connection pin.
6 GND Ground pin.
7 FREQ I
Frequency switching signal input pin.
FREQ : GND Short Switching frequency 310 kHz
FREQ : Open Switching frequency 620 kHz
FREQ : VB Short Switching frequency 1 MHz
8 CS2 I CH2 soft-start time setting capacitor connection pin.
9 FB2 I CH2 input pin for feedback voltage.
10 VOUT2 I CH2 input pin for DC/DC output voltage.
11 EN2 I CH2 enable pin.
12 BST2 CH2 boost capacitor connection pin.
13 DRVH2 O CH2 output pin for external high-side FET gate drive.
14 LX2 CH2 inductor and external high-side FET source connection pin.
15 DRVL2 CH2 output pin for external low-side FET gate drive.
16 ILIM2 I CH2 over current detection level setting voltage input pin.
17 MODE I
DC/DC control mode switching signal input pin.
MODE : GND Short PFM/PWM
MODE : Open PFM/PWM, PAF
MODE : VB Short PWM fixed
18 VB O Internal circuit bias output pin.
19 VCC I Power input pin for control and output circuits.
20 ILIM1 I CH1 over current detection level setting voltage input pin.
21 PGND Ground pin for output circuit.
22 DRVL1 O CH1 output pin for external low-side FET gate drive.
23 LX1 CH1 inductor and external high-side FET source connection pin.
24 DRVH1 O CH1 output pin for external high-side FET gate drive.
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BLOCK DIAGRAM
A
A
2 µA
2 µA
450 k
450 k
VIN
(6 V to 28
V
OVP
UVP
UVP2
UVP1
OVP2
OVP1
REF1
× 0.7 V
REF1
× 1.15V
/EN 1
/UVLO(OTP)
/EN1
OTP
UVP
REF1
(0.7 V)
t
ON
Generator
VCC
EN1
EN2
VCC
VB
VB
4 : 1
25
<Error Comp.>
VB
5.2 V
<ILIM Comp.>
<OVP Comp.>
<UVP Comp.>
VREF
2.5 V
R
Q
S
Slope & Offset
OVP latch
(delay:15 µs)
UVP latch
(delay:150 µs)
VOUT1
<CH1>
VOUT1
FB1
CS1
ILIM1
EN1
V
OUT2
VOUT2
FB2
CS2
ILIM2
EN2
<CH2>
EN
Logic EN1
"H": Enable
REF1
REF2
UVLO
(VB)
UVLO
(VREF)
UVLO OTP
to CH2
MODE
Select
BST2
MODE
FREQ
PGND
DRVL1
DRV
Logic
<IR Comp.>
LX1
PGND
×1.0
×1.0
LX1
DRVH1
VOUT1
DRVH
DRVL
BST1
VB
DRVH2
LX2
DRVL2
VOUT2
GND
FREQ
Select
"H": UVLO
release Thermal
Protection
EN2
(0.7 V)
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ABSOLUTE MAXIMUM RATINGS
Rating
Parameter Symbol Condition
Min Max
Unit
VCC pin input voltage VVCC VCC pin 0.3 + 30 V
BST pin input voltage VBST BST1, BST2 pins 0.3 + 36 V
LX pin input voltage VLX LX1, LX2 pins 1 + 30 V
Voltage between
BST and LX VBST-LX 0.3 + 7 V
EN pin input voltage VEN EN1, EN2 pins 0.3 + 30 V
VFB FB1, FB2 pins 0.3 VB + 0.3 V
VVOUT VOUT1, VOUT2 pins 0.3 + 7 V
VILIM ILIM1, ILIM2 pins 0.3 VB + 0.3 V
VCS CS1, CS2 pins 0.3 VB + 0.3 V
VFREQ FREQ pin 0.3 VB + 0.3 V
Input voltage
VMODE MODE pin 0.3 VB + 0.3 V
Output current IOUT DRVH1, DRVH2 pins,
DRVL1, DRVL2 pins — 60 mA
Power dissipation PD Ta + 25°C — + 1282 mW
Storage temperature TSTG 55 + 125 °C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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RECOMMENDED OPERATING CONDITIONS
Value
Parameter Symbol Condition
Min Typ Max
Unit
VCC pin input voltage VVCC VCC pin 6 28 V
BST pin input voltage VBST BST1, BST2 pins 34 V
EN pin input voltage VEN EN1, EN2 pins 0 28 V
VFB FB1, FB2 pins 0 VB V
VVOUT VOUT1, VOUT2 pins 0 5.5 V
VILIM ILIM1, ILIM2 pins 0 2 V
VFREQ FREQ pin 0 VB V
Input voltage
VMODE MODE pin 0 VB V
Peak output current IOUT
DRVH1, DRVH2 pins,
DRVL1, DRVL2 pins
Duty 5% (t = 1/fOSC¯Duty)
1200 + 1200 mA
Operating ambient
temperature Ta 30 + 25 + 85 °C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device
is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
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ELECTRICAL CHARACTERISTICS
(Ta = +25°C, VCC = 12 V, EN1, EN2 = 5 V)
Value
Parameter Symbol Pin
No. Condition
Min Typ Max
Unit
Output voltage VVB 18 VB = 0 A 5.04 5.20 5.36 V
Input stability LINE 18 VCC = 6 V to 28 V 10 100 mV
Load stability LOAD 18 VB = 0 A to 1 mA — 10 100 mV
Bias Voltage
Block
[VB Reg.] Short-circuit
output current IOS 18 VB = 0 V 145 100 75 mA
VTLH 18 VB pin 4.0 4.3 4.6 V
Threshold voltage
VTHL 18 VB pin 3.7 4.0 4.3 V
Under
voltage
Lockout
Protection
Circuit Block
[UVLO]
Hysteresis width VH 18 VB pin 0.3* V
Charge current ICS 5,8 CS1, CS2 = 0 V 1.5 1.0 0.75 µA
Electrical discharge
resistance RD 3,10 EN1, EN2 = 0 V,
VOUT1, VOUT2 0.15 V — 25*
Soft-Start/
Discharge
Block
[Soft Start,
Discharge] Discharge end
voltage VVOVTH 3,10 EN1, EN2 = 0 V,
VOUT1, VOUT2 pins — 0.2* V
tON11 24
FREQ pin GND connection
VCC = 12 V, VOUT1 = 1.5 V 430 538 646 ns
ON time
(Preset value 1)
tON21 13
FREQ pin GND connection
VCC = 12 V, VOUT2 = 1.5V 320 400 480 ns
tON12 24
FREQ pin OPEN
VCC = 12 V, VOUT1 = 1.5 V 210 263 316 ns
ON time
(Preset value 2)
tON22 13
FREQ pin OPEN
VCC = 12 V, VOUT2 = 1.5 V 160 200 240 ns
tON13 24
FREQ pin VB connection
VCC = 12 V, VOUT1 = 1.5 V 130 163 196 ns
ON time
(Preset value 3)
tON23 13
FREQ pin VB connection
VCC = 12 V, VOUT2 = 1.5 V 100 125 150 ns
tONMIN11 24
FREQ pin GND connection
VCC = 12 V, VOUT1 = 0V — 136 191 ns
Minimum
ON time
(Preset value 1) tONMIN21 13
FREQ pin GND connection
VCC = 12 V, VOUT2 = 0V — 103 145 ns
tONMIN12 24
FREQ pin OPEN
VCC = 12 V, VOUT1 = 0V — 77 108 ns
Minimum
ON time
(Preset value 2) tONMIN22 13
FREQ pin OPEN
VCC = 12 V, VOUT2 = 0V — 58 82 ns
tONMIN13 24
FREQ pin VB connection
VCC = 12V, VOUT1 = 0V — 55 77 ns
Minimum
ON time
(Preset value 3) tONMIN23 13
FREQ pin VB connection
VCC = 12 V, VOUT2 = 0V — 43 61 ns
ON/OFF
Time
Generator
Block
[tON
Generator]
Minimum OFF time tOFFMIN 24, 13 410 535 ns
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Value
Parameter Symbol Pin
No. Condition
Min Typ Max
Unit
Threshold voltage VTH 4, 9
Ta = +25°C 0.695 0.700 0.705 V
FB pin input current IFB 4, 9 FB1, FB2 = 0.7 V 0.1 0 +0.1 µA
Error
Comparison
Block
[Error Comp.] VOUT pin input
current IVO 3,10 VOUT1, VOUT2 = 1.5 V 6.0 8.6 µA
Over current detection
offset voltage VOFFILIM
21 to 23
21 to 14
PGND LX1, LX2
ILIM1, ILIM2 = 500 mV 30 0 +30 mV
ILIM pin current IILIM 20,16 ILIM1, ILIM2 = 0 V 6 5 4 µA
Over Current
Detection
Block
[ILIM Comp.] ILIM pin current
Temperature slope TILIM 20,16 Ta = +25°C — 4500* — ppm/
°C
Over-voltage
detecting voltage VOVP 4, 9 For REF1, REF2 voltage 110 115 120 %
Hysteresis width VHOVP 4, 9 5* %
Over-
voltage
Protection
Circuit Block
[OVP Comp.] Detection delay time tOVP 10 15 20
µs
Under-voltage
detecting voltage VUVP 4, 9 For REF1, REF2 voltage 65 70 75 %
Hysteresis width VHUVP 4, 9 10* %
Under-
voltage
Protection
Circuit Block
[UVP Comp.] Detection delay time tUVP 100 150 200 µs
TOTPH 150*
°C
Over-
temperature
Protection
Circuit Block
[OTP]
Protection
temperature TOTPL 125*
°C
ROH 24,13 DRVH1, DRVH2 =
100 mA — 4 6
High-side output
on-resistance
ROL 24,13 DRVH1, DRVH2 = 100 mA 1 1.5
ROH 22,15 DRVL1, DRVL2 =
100 mA — 4 6
Low-side output
on-resistance
ROL 22,15 DRVL1, DRVL2 = 100 mA 1 1.5
Output source
current ISOURCE
24,13
22,15
LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVH1, DRVH2 = 2.5 V
Duty 5%
0.5* — A
Output sink current ISINK 24,13
22,15
LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVH1, DRVH2 = 2.5 V
Duty 5%
— 0.9* — A
LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVL1, DRVL2-low to
DRVH1, DRVH2-on
15 25 35 ns
Output Block
[DRV]
Dead time tD 24 to 22
13 to 15 LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVH1, DRVH2-low to
DRVL1, DRVL2-on
35 50 65 ns
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Value
Parameter Symbol Pin
No. Condition
Min Typ Max
Unit
BST diode voltage VF 1,12 IF = 10 mA 0.75 0.85 0.95 V
Output Block
[DRV] Bias current IBST 1,12 LX1, LX2 = 0 V,
BST1, BST2 = 5.2 V 11 15 22
µA
Preset value 1
conditions VFREQ1 7 FREQ pin:
GND connection 0 — 0.2 V
Preset value 2
conditions VFREQ2 7 FREQ pin: OPEN 0.6 1.2 V
Preset value 3
conditions VFREQ3 7 FREQ pin: VB connection 2.4 VB V
Switching
Frequency
Control Block
[FREQ]
FREQ pin
output voltage VFREQ 7 FREQ = OPEN 0.63 0.9 1.17 V
PFM/PWM mode
conditions
PAF function
negate
VPFM1 17 MODE pin:
GND connection 0 — 0.2 V
PFM/PWM mode
conditions
PAF function
assert
VPFM2 17 MODE pin : OPEN 0.6 1.2 V
PWM-fixed mode
conditions VPWM 17 MODE pin : VB connection 4.6 VB V
PAF frequency fPAF
Ta = 30°C to +85°C 30 45 — kHz
PFM Control
Circuit Block
[MODE]
MODE pin voltage VMODE 17 MODE = OPEN 0.63 0.9 1.17 V
ON condition VON 2, 11 EN1, EN2 pins 2.64 V
OFF condition VOFF 2, 11 EN1, EN2 pins 0.66 V
Hysteresis width VH 2, 11 EN1, EN2 pins 0.4* V
Enable Block
[EN1 , EN2]
Input current IEN 2, 11 EN1, EN2 = 5V 11 15 22 µA
Standby current ICCS 19 EN1, EN2 = 0V 0 10 µA
Power supply
current during idle
period
ICC1 19
LX1, LX2 = 0 V
BST1, BST2 :
VB connection
FB1, FB2 = 0.75 V
— 600 860 µA
Power Supply
Current
Power supply
current during
operation
ICC2 19
LX1, LX2 = 0V
BST1, BST2 :
VB connection
FB1, FB2 = 0.6 V
— 1200 1700 µA
*: This parameter is not be specified. This should be used as a reference to support designing the circuits.
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TYPICAL CHARACTERISTICS
Power dissipation vs. Operating ambient temperature
Power dissipation PD (mW)
0
500
1000
1500
2000
-50 -25 +0 +25 +50 +75 +100+12
5
1282
Operating ambient temperature Ta (°C)
VB bias voltage vs. Operating ambient temperature VB bias voltage vs. VB bias output current
VB bias voltage VVB (V)
5.00
5.04
5.08
5.12
5.16
5.20
5.24
5.28
5.32
5.36
5.40
-40 -20 0 +20 +40 +60 +80 +100
VCC=12V
I
VB
=0A
VB bias voltage VVB (V)
5.0
5.1
5.2
5.3
5.4
-30 -25 -20 -15 -10 -5 0
VCC=6V
VCC=12V
VCC=28V
Operating ambient temperature Ta (°C) VB bias output current IVB (mA)
Error Comp. Threshold voltage vs.
Operating ambient temperature ILIM pin current vs. Operating ambient temperature
Error Comp. Threshold voltage VTH (V)
0.695
0.696
0.697
0.698
0.699
0.700
0.701
0.702
0.703
0.704
0.705
-40 -20 0 +20 +40 +60 +80+100
ILIM pin current IILIM (µA)
-6.0
-5.5
-5.0
-4.5
-4.0
-3.5
-40 -20 0 +20 +40 +60 +80 +100
Operating ambient temperature Ta (°C) Operating ambient temperature Ta (°C)
Ta = +25 °C
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DRVH1 on time vs. Operating ambient temperature DRVH2 on time vs. Operating ambient temperature
DRVH1 on time tON1 (ns)
100
150
2
00
2
50
300
350
4
00
4
50
500
550
600
650
700
-40 -20 0 +20 +40 +60 +80 +100
VCC=12V
VOUT1=1.5V
FREQ=GND
FREQ=OPEN
FREQ=VB
DRVH2 on time tON2 (ns)
50
100
150
200
250
300
350
400
450
500
-40 -20 0 +20 +40 +60 +80 +100
VCC=12V
VOUT2=1.5V
FREQ=GND
FREQ=OPEN
FREQ=VB
Operating ambient temperature Ta (°C) Operating ambient temperature Ta (°C)
DRVH1 minimum on time vs. Input voltage DRVH2 minimum on time vs. Input voltage
DRVH1 minimum on time tONMIN1 (ns)
0
50
100
150
200
250
5 1015202530
FREQ=GND
FREQ=OPEN
FREQ=VB
DRVH2 minimum on time tONMIN1 (ns)
0
50
100
150
200
5 1015202530
FREQ=GND
FREQ=OPEN
FREQ=VB
Input voltage VIN (V) Input voltage VIN (V)
DRVH1 minimum on time vs.
Operating ambient temperature DRVH2 minimum on time vs.
Operating ambient temperature
DRVH1 minimum on time tONMIN1 (ns)
40
60
80
100
120
140
160
180
-40 -20 0 +20 +40 +60 +80 +100
VCC=12V
VOUT1= 0 V
FREQ=GND
FREQ=OPEN
FREQ=VB
DRVH2 minimum on time tONMIN2 (ns)
20
40
60
80
100
120
140
-40 -20 0 +20 +40 +60 +80 +100
VCC=12V
VOUT2=0 V
FREQ=GND
FREQ=OPEN
FREQ=VB
Operating ambient temperature Ta (°C) Operating ambient temperature Ta (°C)
Ta = + 25°C
Ta = + 25°C
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Minimum off time vs. Input voltage Minimum off time vs.
Operating ambient temperature
Minimum off time tOFFMIN (ns)
200
250
300
350
400
450
500
550
600
5 1015202530
Minimum off time tOFFMIN (ns)
200
250
300
350
4
00
4
50
500
550
600
-40 -20 0 +20 +40 +60 +80 +100
VCC=12V
Input voltage VIN (V) Operating ambient temperature Ta (°C)
Dead time vs. Operating ambient temperature Bootstrap diode IF vs. VF
Dead time (ns)
20
25
3
0
3
5
4
0
4
5
50
55
6
0
-40 -20 0 +20 +40 +60 +80 +100
LX=0V
V
BST
=VB
t
D1
t
D2
IF current IF (mA)
0.001
0.01
0.1
1
10
100
0.2 0.4 0.6 0.8 1 1.2
Operating ambient temperature Ta (°C) VF voltage VF (V)
tD1 : Period from DRVL off to DRVH on
tD2 : Period from DRVH off to DRVL on
Ta = - 30°C
Ta =+25°C
Ta =+ 85°C
Ta = + 25°C
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FUNCTION
Bottom detection comparator system for low output voltage ripple
The bottom detection comparator system for low output voltage ripple determines the ON time (tON) using
the input voltage (VIN) and output voltage (VOUT) to hold the ON state to a specified period. During the OFF
period, the reference voltage (INTREF) is compared with the feedback voltage (FB) using the error
comparator (Error Comp.). When the feedback voltage (FB) is below the reference voltage (INTREF) ,
RS-FF is set and the ON period starts again. Switching is repeated as described above. Error Comp. is used
to compare the reference voltage (INTREF) with the feedback voltage (FB) to control the off-duty condition
in order to stabilize the output voltage.
This system adds the inductor current slope detected during the synchronous rectification period (tOFF) to
the reference voltage (INTREF) , and generates an output voltage slope during the OFF period, which is
essential for the bottom detection comparator system, in the IC. This enables the stable control operations
under the low output voltage ripple conditions.
y Circuit diagram
Bias
tON
generator
Slope
Detector
Drive
Logic
INTREF
VREF
VIN
IL
S
VOUT
Bias
Reg.
Lo-side
Drive
FB -
+
RS-FF
<Error Comp.> RQ
Hi-side
Drive
RS out
VINVOUT
tON
DRVH
DRVL
+
-
y Waveforms
t
t
ON
t
OFF
INTREF
DRVH
FB
I
L
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(1) Bias Voltage Block (VB Reg.)
The 5.2 V (Typ) bias voltage is generated from the VCC pin voltage for the control, output, and boost
circuits. When either or both of the EN1 pin (pin 2) and EN2 pin (pin 11) are set to the “H” level, the
system is restored from the standby state to supply the bias voltage from the VB pin (pin 18).
(2) ON/OFF Time Generator Block (tON Generator)
This block contains a capacitor for timing setting and a resistor for timing setting and generates ON time
(tON) which depends on input voltage and output voltage. The switching frequency can be switched by
setting the FREQ pin (pin 7) to any one of GND connection, OPEN, and VB connection. ON time for each
CH is obtained from the following formula.
<FREQ pin : GND connection>
VVOUT1
tON1 (ns) = VVIN ¯ 4300 (fOSC1 230 kHz)
VVOUT2
tON2 (ns) = VVIN ¯ 3200 (fOSC2 310 kHz)
<FREQ pin : OPEN>
VVOUT1
tON1 (ns) = VVIN ¯ 2100 (fOSC1 460 kHz)
VVOUT2
tON2 (ns) = VVIN ¯ 1600 (fOSC2 620 kHz)
<FREQ pin : VB connection>
VVOUT1
tON1 (ns) = VVIN ¯ 1300 (fOSC1 750 kHz)
VVOUT2
tON2 (ns) = VVIN ¯ 1000 (fOSC2 1000 kHz)
The switching frequency of CH2 is set to 1.33 times that of CH1 to prevent the beat by the frequency
difference of channel to channel.
(3) Output Block (DRV1, DRV2)
The output circuit is configured in CMOS type for both of the high-side and the low-side. It provides the
0.5 A (Typ) source current and 0.9 A (Typ) sink current, drive the external N-ch MOS FET. The output
circuit of the high-side FET supplies the power from the boost circuit including the built-in boost diode. The
output circuit of the low-side FET supplies the power from the VB pin. This circuit monitors the gate
voltages of the high-side and low-side FETs. Until either FET is turned off, this circuit controls the ON
timing of another FET, preventing the shoot-through current. The sink ON resistance of the output circuit is
low 1 (Typ), improve the self turn on margin of low-side FET.
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(4) Starting sequence
When the EN1 pin (pin 2) or EN2 pin (pin 11) is set to the “H” level, the bias voltage is supplied from the
VB pin. If the voltage of the VB pin exceeds the UVLO threshold voltage, the DC/DC converter starts
operations and carries out the soft start. The soft start is a function used to prevent a rush current when the
power is started.
Activating the soft start initiates charging of the capacitor connected to the CS1 pin (pin 5) and CS2 pin (pin
8) and inputs the lamp voltage to the error comparator (Error Comp.) of each channel. The DC/DC
converter generates the output voltage according to that lamp voltage. This results in the soft start operation
that does not depend on the output load. The over voltage protection (OVP) and under voltage protection
(UVP) functions are disabled while the soft start is active.
<Timing chart>
EN1
VB
CS1
DRVH1
UVLO V
TLH
INTREF
INTREF 0.805
V
1.6 V
1.6 V
0.805 V
DRVL1
V
OUT1
EN2
CS2
DRVH2
DRVL2
V
OUT2
CH1 soft start completed
UVLO release
CH2 soft start completed
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(5) DC/DC converter stop sequence (Discharge, standby)
When the EN1 pin (pin 2) or EN2 pin (pin 11) is set to the “L” level, the output capacitor is discharged
using the discharge FET (RON 25 ) in the IC. If the voltage of the VOUT1 pin (pin 3) and VOUT2 pin
(pin 10) is below 0.2 V (Typ) by discharging the output capacitor, the IC stops discharge operation. Further,
if both the EN1 and EN2 pins are set to the “L” level, the IC also stops the output of the VB pin and enters
the standby state after detecting UVLO. The current of the VCC pin (IVCC) is then 10 µA (Max).
<Timing chart>
EN1
UVLO V
THL
VB
CS1
RVH1
DRVL1
V
OUT1
EN2
0.2 V
1.6 V
1.6 V
0.2 V
CS2
RVH2
DRVL2
V
OUT2
(6) Under Voltage Lockout Protection (UVLO)
The under voltage lockout protection (UVLO) protects ICs from malfunction and protects the system from
destruction/deterioration, according to the reasons mentioned below.
y Transitional state when the bias voltage (VB) or the reference voltage (VREF) starts.
y Momentary decrease
To prevent such a malfunction, this function detects a voltage drop of the VB pin (pin 18) using the
comparator (UVLO Comp.), and stops IC operations.
When the VB pin exceeds the threshold voltage of the under voltage lockout protection circuit, the system
is restored.
CH2 discharge FET ON
CH1 discharge FET ON
Standby
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(7) Over Current Limitation (ILIM)
This function limits the output current when it has increased, and protects devices connected to the output.
This function detects the inductor current IL from the electromotive force of the low-side FET on-resistance
RON, and compares this voltage with the 1/5-time value of the voltage VILIM of the ILIM1 pin (pin 20) and
ILIM2 pin (pin 16) on a cyclically, using ILIM Comp. Until this voltage falls below the over current limit
value, the high-side FET is held in the off state. After the voltage has fallen below the limit value, the
high-side FET is placed into the on state. This limits the lower bound of the inductor current and also
restricts the over current. As a result, it becomes operation that the output voltage droops.
The over current limit value is set by connecting the resistor to the ILIM pin. The ILIM pin supplies the
constant current of 5 µA (Typ) . However, the current value has a temperature slope up to 4500 ppm/°C to
compensate the temperature dependence characteristics of the low-side FET on-resistance.
I
L
V
OUT
DRVH
DRVL
(I
OUT1
)
Output voltage setting value
Keep the off state of the high-side FET
until the detection value is gained.
Over current limit operation
Normal operation
VILIM
ILIM detection value (RON × IL =
5
)
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(8) Over Voltage Protection (OVP)
This function stops the output voltage when the output voltage has increased, and protects devices
connected to the output.
1. Using OVP Comp, this function makes a comparison between the voltage which is 1.15 times (Typ) of
the internal reference voltage INTREF1 and INTREF2 (0.7 V), and the feedback voltage for the FB1
pin (pin 4) and the FB2 pin (pin 9).
2. If the feedback voltage mentioned in 1 detects the higher state by 15µs (Typ) or more, the operations
below will be performed.
y Set the RS latch.
y Set the DRVH1 pin (pin 24) and the DRVH2 pin (pin 13) to the “L” level.
y Set the DRVL1 pin (pin 22) and the DRVL2 pin (pin 15) to the “H” level.
These operations fix the high-side FET to the off state and the low-side FET to the on state for both
channels of the DC/DC converter, and stops switching (latch stop).The over-voltage protection state can be
cancelled by setting both the EN1pin (pin 2) and EN2 pin (pin 11) to the “L” level or reducing the VCC
power once until the bias voltage (VB) falls below VTHL of UVLO.
<Timing chart>
VOUT1
FB1
0 V
0 V
0 V
0V
INTREF
INTREF
DRVH1
DRVL1
CS1
VOUT2
FB2
DRVH2
DRVL2
CS2
EN1, EN2
VB UVLO VTHL
15 µs
Output voltage
setting value
Output voltage
setting value
Standby
Less than 15 µs
Cancellation of over-voltage protection
state by EN = "L".
INTREF¯1.15
INTREF¯1.10
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(9) Under Voltage Protection (UVP)
This function stops the output voltage when the output voltage has lowered, and protects devices connected
to the output.
1. Using UVP Comp, this function makes a comparison between the voltage which is 0.7 times (Typ) of
the internal reference voltage REF1, REF2 (0.7 V), and the feedback voltage for the FB1 pin (pin 4) and
the FB2 pin (pin 9).
2. If the feedback voltage mentioned in 1 detects the higher state by 150µs (Typ) or more, the operations
below will be performed.
y Set the RS latch.
y Set the DRVH1 pin (pin 24) and the DRVH2 pin (pin 13) to the “L” level.
y Set the DRVL1 pin (pin 22) and the DRVL2 pin (pin 15) to the “L” level.
These operations fix the high-side FET to the off state and the low-side FET to the off state for both
channels of the DC/DC converter, and stops switching (latch stop). The discharge operation is then carried
out to discharge the output capacitor (The discharge operation continues until the state of the under-voltage
protection is released).
The under-voltage protection state can be cancelled by setting both the EN1 pin (pin 2) and EN2 pin (pin 11)
to the “L” level or reducing the VCC power once until the bias voltage (VB) falls below VTHL of UVLO.
<Timing chart>
V
OUT1
FB1
DRVH1
DRVL1
CS1
V
OUT2
FB2
DRVH2
DRVL2
CS2
EN1, EN2
VB
0 V
0 V
0 V
INTREF
INTREF
UVLO V
THL
150 µs
0 V
Output voltage
setting value
Standby
Less than 15 µs
Cancellation of over-voltage protection state by EN = "L".
INTREF ¯ 0.8
INTREF ¯0.7
Output voltage
setting value
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(10) Over Temperature Protection (OTP)
The over-temperature protection circuit block (OTP) provides a function that prevents the IC from a thermal
destruction. If the junction temperature reaches + 150°C, the DRVH1 pin (pin 24) and DRVH2 pin (pin 13)
are set to the “L” level, and the DRVL1 pin (pin 22 ) and DRVL2 pin (pin 15) are set to the “L” level. This
fixes the high-side and low-side FETs to the off-state, of both channels in the DC/DC converter, causing
switching to be stopped. The discharge operation is then carried out to discharge the output capacitor (The
discharge operation continues until the state of the over-temperature protection is released). If the junction
temperature drops to + 125°C, the soft start is reactivated. (Restored automatically.)
(11) Operation mode
In the PWM-fixed mode, the system acts by the switching frequency specified with the FREQ pin
regardless of the load.
In the automatic PFM/PWM selection mode, the switching frequency is reduced at low load, for enhancing
the conversion efficiency characteristics. This function detects 0 A of the inductor current from the
electromotive force of the low-side FET ON resistance when the low-side FET ON state, and places the
low-side FET into the off state. This idle period continued until the output voltage decreased, this results the
switching frequency being reduced automatically depending on the load current when the inductor current
is below the critical current. The system acts by the switching frequency specified with the FREQ pin, when
the inductor current exceeds the critical current.
For Automatic PFM/PWM selection mode with PAF function, the switching frequency at low load is held to
30 kHz (Min) or more.
The operation mode can be switched by setting the MODE pin (pin 17) to any one of GND connection,
OPEN, and VB connection.
y PWM-fixed mode
IOUTx
ILXx
V
LXx
0 A
y Automatic PFM/PWM selection mode
I
OUTx
I
LXx
V
LXx
0 A
Switching frequency reduced
Inductor current in the opposite
direction
X : Each channel number
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y Enable function table
EN1 pin EN2 pin DC/DC converter (CH1) DC/DC converter (CH2)
L L OFF OFF
H L ON OFF
L H OFF ON
H H ON ON
y DC/DC Control mode function table
MODE pin DC/DC control
GND connection Automatic PFM/PWM selection mode
OPEN Automatic PFM/PWM selection mode with PAF function
VB connection PWM-fixed mode
y Switching frequency control function table
FREQ pin Switching frequency
GND connection fOSC1 230 kHz, fOSC2 310 kHz
OPEN fOSC1 460 kHz, fOSC2 620 kHz
VB connection fOSC1 750 kHz, fOSC2 1000 kHz
y Protection function table
The following table shows the state of the VB pin (pin 18), the DRVH1 pin (pin 24), the DRVH2 pin (pin
13), the DRVL1 pin (pin 22), the DRVL2 pin (pin 15) when each protection function operates.
Output of each pin
after detection
Protection
function Detection condition
VB DRVH1,
DRVH2
DRVL1,
DRVL2
DC/DC output
dropping operation
Under Voltage
Lockout Protection
(UVLO)
VB < 4.0 V L L Natural electric
discharge
Over-current
limitation
(ILIM)
VPGND - VLX1, VLX2 >
VILIM1, VILIM2 5.2 V Switching Switching The voltage is dropped
by the constant current
Over Voltage
Protection
(OVP)
VFB1, VFB2 >
INTREF1, INTREF2¯1.15
(15 µs or higher)
5.2 V L H 0 V clamping
Under Voltage
Protection
(UVP)
VFB1, VFB2 >
INTREF1, INTREF2¯0.7
(150 µs or higher)
5.2 V L L Electrical discharge by
discharge function
Over Temperature
Protection
(OTP)
Tj > + 150 °C 5.2 V L L Electrical discharge by
discharge function
Enable
(EN)
EN1, EN2: H L
(VOUT1, VOUT2 > 0.2 V) 5.2 V L L Electrical discharge by
discharge function
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I/O PIN EQUIVALENT CIRCUIT DIAGRAM
VB
FB1
FB2
EN1
EN2
GND GND
MODE
GND
VB
VB
VB
VCC
ILIM1
ILIM2
VOUT1
VOUT2
GND
GND
PGND
VB
FRWQ
GND
EN1, EN2 pins
FB1, FB2 pins
ESD protection
element
FREQ pin MODE pin
ILIM1, ILIM2 pins VOUT1, VOUT2 pins
ESD protection
element
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VB
VB
BST1
BST2
LX1
LX2
VCC
GND
PGND
PGND
PGND
VB
DRVL1
DRVL2
DRVH1
DRVH2
VB
GND
VCC
CS1
CS2
GND
DRVL1, DRVL2 pins
CS pin
DRVH1, DRVH2, BST1, BST2, LX1, LX2 pins VB pin
VCC pin
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EXAMPLE APPLICATION CIRCUIT
VIN
VIN
VIN
VIN
PGND
PGND
VOUT1
PGND
VOUT2
1.0 V, 7 A
1.8 V, 7 A
MB39A214A
12 V
+
+
VOUT1
FB1
EN1
CS1
ILIM1
MODE
FREQ
VOUT2
EN2
CS2
EN2
EN1
C13 C12
C7
C8
R6
R4 R3-2 R3-1 R1-2 R1-1
R5
R2
GND
PGND
DRVL2
LX2
DRVH2
BST2
DRVL1
LX1
DRVH1
BST1
VB
VCC
ILIM2
FB2
3
19
18
1
24
23
12
13
14
15
21
21
Q3
Q3
Q1
56
7
43
78
21
Q1 56
43L1
L2
C5
C1-1
C1-2
C2-1
C3-1
C6
C3-2
C4-1
C4-3 C2-3
8
22
2
5
4
20
17
7
10
9
11
8
16
6
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PART LIST
Component Item Specification Vendor Package Part number Remarks
Q1 N-ch FET
VDS = 30 V, ID = 9 A, 5.4 A,
RON = 34 m, 13 m RENESAS SOP8 µPA2758 DualType
(2elements)
Q3 N-ch FET
VDS = 30 V, ID = 9 A, 5.4 A,
RON = 34 m, 13 m RENESAS SOP8 µPA2758 DualType
(2elements)
L1 Inductor 1 µH (18 A) NEC TOKIN - MPC1055L1R0
L2 Inductor 1.5 µH (12.4 A) NEC TOKIN - MPLC1040L1R5
C1-1 Ceramic
capacitor 10 µF (25 V) MURATA 3216 GRM31CB31E106K
C1-2 Ceramic
capacitor 10 µF (25 V) MURATA 3216 GRM31CB31E106K
C2-1 POSCAP 220 µF (2 V) SANYO D case 2TPLF220M6
C2-3 Ceramic
capacitor 1000 pF (50 V) TDK 1608 C1608JB1H102K
C3-1 Ceramic
capacitor 10 µF (25 V) MURATA 3216 GRM31CB31E106K
C3-2 Ceramic
capacitor 10 µF (25 V) MURATA 3216 GRM31CB31E106K
C4-1 POSCAP 150 µF (6.3 V) SANYO D case 6TPL150MU
C4-3 Ceramic
capacitor 1000 pF (50 V) TDK 1608 C1608JB1H102K
C5 Ceramic
capacitor 0.1 µF (50 V) TDK 1608 C1608JB1H104K
C6 Ceramic
capacitor 0.1 µF (50 V) TDK 1608 C1608JB1H104K
C7 Ceramic
capacitor 0.1 µF (50 V) TDK 1608 C1608JB1H104K
C8 Ceramic
capacitor 4.7 µF (16 V) TDK 1608 C1608JB1C475K
C12 Ceramic
capacitor 3300 pF (50 V) TDK 1608 C1608JB1H332K
C13 Ceramic
capacitor 3300 pF (50 V) TDK 1608 C1608JB1H332K
R1-1 Resistor 1.6 k SSM 1608 RR0816P162D
R1-2 Resistor 27 k SSM 1608 RR0816P273D
R2 Resistor 68 k SSM 1608 RR0816P683D
R3-1 Resistor 0.047 k SSM 1608 RR0816P470D
R3-2 Resistor 56 k SSM 1608 RR0816P563D
R4 Resistor 36 k SSM 1608 RR0816P363D
R5 Resistor 110 k SSM 1608 RR0816P114D
R6 Resistor 120 k SSM 1608 RR0816P124D
RENESAS : Renesas Electronics Corporation
SANYO : SANYO Electric Co., Ltd
NEC TOKIN : NEC TOKIN Corporation
TDK : TDK Corporation
MURATA : Murata Manufacturing Co., Ltd.
SSM : SUSUMU Co.,Ltd.
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APPLICATION NOTE
1. Setting Operating Conditions
Setting output voltages
The output voltage can be set by adjusting the setting output voltage resistor ratio. Setting output voltage is
calculated by the following formula.
R1 + R2 2.8¯10-7 ΔVOUTx
VOUTx = R2
¯ (0.6946 + 0.2667¯ΔIL¯ (1
tOFF ) ¯RON_Sync) + 2
VIN VOUT VOUT (VIN VOUTx)
ΔVOUTx = ESR ¯ΔIL, ΔIL = L
¯
VIN ¯ fOSC
, tOFF = VIN¯fOSC
VOUTx : Output setting voltage [V]
VIN : Power supply voltage [V]
ΔVOUTX : Output ripple voltage value [V]
tOFF : Off time [s]
RON_Sync : ON resistance of low-side FET []
ΔIL : Ripple current peak-to-peak value of inductor [A]
ESR : Series resistance element of output capacitor []
L : Inductor value [H]
fOSC : Switching frequency [Hz]
R1
V
OUTx
R2
VOUT
X
FB
X
The total resistor value (R1+R2) of the setting output resistor should be selected up to 100 k.
x: Each channel number
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Minimum power supply voltage
The maximum on duty is limited by "the minimum off time (tOFFMIN) that an IC holds without fail as a fixed
value" and "the on time (tON) determined by the power voltage value and the output voltage setting value".
The ratio between the output voltage and the power voltage must be less than the maximum on duty.
The minimum power supply voltage that is required to sustain the output voltage can be calculated by the
following formula.
(VOUT + IOUT_MAX ¯ (RDC + RON_Main)) ¯ VOUT
VIN_MIN = VOUT (VOUT + IOUT_MAX ¯ (RDC + RON_Sync)) ¯ tOFF_MIN ¯ fOSC ¯1.2
VIN_MIN : Power supply voltage [V]
VOUT : Output setting voltage [V]
IOUT_MAX : Maximum load current value [A]
RON_Main : ON resistance of high-side FET []
RON_Sync : ON resistance of low-side FET []
RDC : Series resistance of inductor []
fOSC : Switching frequency setting value [Hz]
tOFF_MIN : Minimum off time (Maximum value) [s]
(For the minimum off time, see “ON/OFF Time [Minimum OFF time ] ” in
ELECTRICAL CHARACTERISTICS”.)
Use the smaller switching frequency setting in order to make the voltage output possible with the lower
power voltage.
Slope voltages
It is necessary to sustain the Slope voltage 15 mV or higher in order to obtain the stable switching cycle.
The Slope voltage can be calculated by the following formula.
(VIN VOUT) ¯ VOUT ¯ RON_Sync
VSlope = L ¯ VIN ¯ fOSC
VSlope : Slope voltage [V]
VIN : Power supply voltage [V]
VOUT : Output setting voltage [V]
fOSC : Switching frequency [Hz]
RON_Sync : ON resistance of low-side FET []
L : Inductor value [H]
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Setting soft-start time
Calculate the soft-start time by the following formula.
ts = 7 ¯ 105 ¯ CCS
ts : Soft-start time [s] (time until output reaches 100%)
CCS : CS pin capacitor value [F]
Calculate the delay time until the soft-start activation by the following formula.
td = 43 ¯ CVB
td : VB voltage delay time (at VIN = 12 V) [s]
CVB : VB pin capacitor value [F]
When activating the other in the state where a side channel has already been activated (UVLO release: VB
output already), the delay time is hardly generated.
t
s1
t
d
t
s2
EN1
EN2
V
OUT1
V
OUT2
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Setting switching frequency
The switching frequency is set at the FREQ pin. As for the setting process, see the switching frequency
control function table.
Setting over current limitation
The over current limitation value can be set by adjusting the over current limitation setting resistor value
connected to the ILIM pin.
Calculate the resistor value by the following formula.
ΔIL
RLIM = 106 ¯ RON_Sync ¯ (ILIM 2 )
RLIM : Over current limitation value setting resistor []
ILIM : Over current limitation value [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
RON_Sync : ON resistance of low-side FET []
ILIM
RLIM
I
OUT
I
LIM
0
If the rate of inductor saturation current is small, the inductor value decreases and the ripple current of
inductor increase when the over-current flows. At that time there is a possibility that the limited output
current increases or is not limited, because the bottom of inductor current is detected. It is necessary to use
the inductor that has enough large rate of inductor saturation current to prevent the overlap current.
Inductor current
Over current
limitation value
Time
ΔIL
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The over current limit value is affected by ILIM pin source current and over current detection offset voltage
in the IC except for the on resistance of the low-side FET and the inductor value. The variation of dropped
over current limit value caused by IC characteristics is calculated by the following formula.
2 ¯10-7¯ RLIM + 0.03
ΔILIM = RON_Sync
ΔILIM : The variation of dropped over current limit value [A]
RLIM : Over current limitation value setting resistor []
RON_Sync : ON resistance of low-side FET []
I
O
0
I
LIM
I
LIM
The over current detection value needs to set a sufficient margin against the maximum load current.
Inductor current
Dropped over current limit value due to
IC's characteristics
Time
Over current limit value ΔILIM
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Power dissipation and the thermal design
IC's loss increases, if IC is used under the high power supply voltage, high switching frequency, high load
and high temperature. The IC internal loss can be calculated by the following formula.
PIC = VCC ¯ (ICC + QG_Total1 ¯ fOSC1 + QG_Total2 ¯ fOSC2)
PIC : IC internal loss [W]
VCC : Power supply voltage (VIN) [V]
ICC : Power supply current [A] (2 mA Max)
QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C]
QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C]
fOSC1 : CH1 switching frequency [Hz]
fOSC2 : CH2 switching frequency [Hz]
Calculate junction temperature (Tj) by the following formula.
Tj = Ta + θja ¯ PIC
Tj : Junction temperature [°C] (+ 125°C Max)
Ta : Ambient temperature [°C]
θja : TSSOP-24P Package thermal resistance (+ 78°C /W)
PIC : IC internal loss [W]
Handling of the pins when using a single channel
Although this device is a 2-channel DC/DC converter control IC, it is also able to be used as a 1-channel
DC/DC converter by handling the pins of the unused channel as shown in the following diagram.
Note: x is the unused channel number.
FBx
VOUTx
CSx
ENx
LXx
ILIMx
DRVHx
BSTx
DRVLx
“Open”
“Open”
“Open”
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2. Selecting parts
Selection of smoothing inductor
The inductor value selects the value that the ripple current peak-to-peak value of the inductor is 50% or less
of the maximum load current as a rough standard. Calculate the inductor value in this case by the following
formula.
VIN VOUT V
OUT
L LOR¯ IOUT_MAX
¯ VIN ¯fOSC
L : Inductor value [H]
IOUT_MAX : Maximum load current [A]
LOR : Ripple current peak-to-peak value of inductor/Maximum load current ratio (= 0.5)
VIN : Power supply voltage [V]
VOUT : Output setting voltage [V]
fOSC : Switching frequency [Hz]
It is necessary to calculate the maximum current value that flows to the inductor to judge whether the
electric current that flows to the inductor is a rated value or less. Calculate the maximum current value of
the inductor by the following formula.
ΔIL
ILMAX IOUT_MAX + 2
ILMAX : Maximum current value of inductor [A]
IOUT_MAX : Maximum load current [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
L : Inductor value [H]
VIN : Power supply voltage [V]
VOUT : Output setting voltage [V]
fOSC : Switching frequency [Hz]
I
OUT_MAX
IL
MAX
0
Inductor current
Time
ΔIL
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Selection of Switching FET
If selecting the high-side FET so that the value of the high-side FET conduction loss and the high-side FET
switching loss is same, the loss is effectively decreased.
Confirm that the high-side FET loss is within the rating value.
PMainFET = PRON_Main + PSW_Main
PMainFET : High-side FET loss [W]
PRON_Main : High-side FET conduction loss [W]
PSW_Main : High-side FET switching loss [W]
High-side FET conduction loss
VOUT
PRON_Main = IOUT_MAX
2 ¯ VIN
¯ RON_Main
PRON_Main : High-side FET conduction loss [W]
IOUT_MAX : Maximum load current [A]
VIN : Power supply voltage [V]
VOUT : Output voltage [V]
RON_Main : ON resistance of high-side FET []
The high-side FET switching loss can be calculated roughly by the following formula.
PSW_Main 1.56 ¯ VIN ¯ fOSC ¯ IOUT_MAX ¯ QSW
PSW_Main : Switching loss [W]
VIN : Power supply voltage [V]
fOSC : Switching frequency [Hz]
IOUT_MAX : Maximum load current [A]
QSW : Amount of high-side FET gate switch electric charge [C]
MOSFET has a tendency where the gate drive loss increases because the lower drive voltage product has
the bigger amount of gate electric charge (QG). Normally, we recommend a 4 V drive product, however, the
idle period at light load (both the high-side FET and the low-side FET is off-period) gets longer and the gate
drive voltage of the high-side FET may decrease, in the automatic PFM/PWM selection mode. The voltage
drops most at no-load mode. At this time, confirm that the boost voltage (voltage between BST-LX pins) is
a big enough value for the gate threshold value voltage of the high-side FET.
If it is not enough, consider adding the boost diode, increasing the capacitor value of the boost capacitor or
using a 2.5 V (or 1.8 V) drive product to the high-side FET.
Select the ON resistance of low-side FET from the range below.
0.2 0.1 0.015
RON_Sync ΔIL , RON_Sync ΔIL
, RON_Sync ΔIL
(ILIM
2 )
RON_Sync : ON resistance of low-side FET []
ΔIL : Ripple current peak-to-peak value of inductor [A]
ILIM : Over current detection value [A]
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If the formula above has been already satisfied and then a low ON resistance FET as possible is used for the
low-side FET, the loss is effectively decreased. Especially, it works dramatically in the low on duty mode.
The loss of the low-side FET can be calculated by the following formula.
VOUT
PSyncFET = PRON_Sync = IOUT_MAX
2 ¯ (1 – VIN
) ¯ RON_Sync
PSyncFET : Low-side FET loss [W]
PRON_Sync : Low-side FET conduction loss [W]
IOUT_MAX : Maximum load current [A]
VIN : Power supply voltage [V]
VOUT : Output voltage [V]
RON_Sync : ON resistance of low-side FET []
Turn-on and turn-off voltage of the low-side FET is generally small and the switching loss is small enough
to ignore, so that is omitted here.
Especially, when turning on the high-side FET under the high power supply voltage condition, the
rush-current might be generated by according to self-turn-on of the low-side FET. The parasitic capacitor
value of the low-side FET needs to satisfy the following conditions.
Crss
VTH_Sync > Ciss
¯VIN
VTH_Sync : Threshold voltage of low-side FET [V]
Crss : Parasitic feedback capacitance of low-side FET [F]
Ciss : Parasitic input capacitance of low-side FET [F]
VIN : Power supply voltage [V]
Also approaches of adding a capacitor close between the gate source pins of the low-side FET or adding
resistor between the BST pin and the boost capacitor, and so on are effective as a countermeasure of the
self-turn-on(adding resistor between the BST pin and the boost capacitor is also effective to adjust turn-on
time of the high-side FET).
This device monitors the gate voltage of the switching FET and optimizes the dead time. If the dumping
resistor is inserted among DRVH, DRVL and the switching FET gate to adjust turn-on and turn-off time of
the switching FET, this function might malfunction. In this device, resistor should not be connected among
the DRVH pin, the DRVL pin of IC and the switching FET gate, and should be connected by low
impedance as possible.
The gate drive power of the switching FET is supplied from LDO (VB) of IC inside. Select switching FET
so that the total amount of the switching FET electric charge for 2 channels (QG_Total1, QG_Total2)
satisfies the following formula.
IVB_MAX > QG_Total1 ¯ fOSC1 + QG_Total2 ¯ fOSC2
IVB_MAX : VB load current upper limit value (see the following graph) [A]
QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C]
QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C]
fOSC1 : CH1Switching frequency [Hz]
fOSC2 : CH2 Switching frequency [Hz]
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6
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
8 10121416182022242628
Moreover, select the total quantity of the high-side FET electric charge as a guide that does not exceed the
total quantity of the high-side FET electric charge upper limit value shown below.
5 1015202530
35
30
25
20
15
10
5
0
FREQ=GND:CH1
FREQ=GND:CH2
FREQ=OPEN:CH1
FREQ=OPEN:CH2
FREQ=VB:CH1
FREQ=VB:CH2
Whether the mean current value that flows to switching FET is a rated value or less of switching FET is
judged. Each rating value for the switching FET can be calculated roughly by the following formula.
ID_Main > IOUT_MAX ¯ D
ID_Sync > IOUT_MAX ¯ (1 – D)
ID_Main : high-side FET drain current [A]
ID_Sync : Low-side FET drain current [A]
IOUT_MAX : Maximum load current [A]
D : On-duty
VDSS > VIN
VDSS : Voltage between the high-side FET drain and source and the low-side FET drain and
source [V]
VIN : Power supply voltage [V]
VB load current upper limit value [A]
VIN [V]
Power supply voltage VIN [V]
The total quantity upper limit of electric
charge of the high-side FET QG_MAX [nC]
From the top line
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Selection of fly-back diode
This device is improved by adding the fly-back diode when the conversion efficiency improvement or the
suppression of the low-side FET fever is desired, although those are unnecessary to execute normally. The
effect is achieved in the condition where the switching frequency is high or output voltage is lower. Select
schottky barrier diode (SBD) that the forward current is as small as possible. In this DC/DC control IC, the
period for the electric current flow into fly-back diode is limited to dead time period because the
synchronous rectification system is adopted. (as for the dead time, see “Output Block” in “ELECTRICAL
CHARACTERISTICS”). Each rating for the fly-back diode can be calculated by the following formula.
ID IOUT_MAX ¯fOSC ¯ (tD1 + tD2)
ID : Forward current rating of SBD [A]
IOUT_MAX : Maximum load current [A]
fOSC : Switching frequency [Hz]
tD1, tD2 : Dead time [s]
ΔIL
IFSM IOUT_MAX + 2
IFSM : Peak forward surge current ratings of SBD [A]
IOUT_MAX : Maximum load current [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
VR_Fly > VIN
VR_Fly : Reverse voltage of fly-back diode direct current [V]
VIN : Power supply voltage [V]
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Selection of input capacitor
Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the
tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the
ceramic capacitor can not support.
The ripple voltage is generated in the power supply voltage by the switching operation of DC/DC. Calculate
the lower bound of input capacitor according to an allowable ripple voltage. Calculate the ripple voltage of
the power supply from the following formula.
IOUT_MAX V
OUT ΔIL
ΔVIN = CIN
¯
VIN ¯ fOSC + ESR ¯ (IOUT_MAX + 2 )
ΔVIN : Power supply ripple voltage peak-to-peak value [V]
IOUT_MAX : Maximum load current value [A]
CIN : Input capacitor value [F]
VIN : Power supply voltage [V]
VOUT : Output setting voltage [V]
fOSC : Switching frequency [Hz]
ESR : Series resistance component of input capacitor []
ΔIL : Ripple current peak-to-peak value of inductor [A]
Capacitor has frequency characteristic, the temperature characteristic, and the bias voltage characteristic, etc.
The effective capacitor value might become extremely small depending on the use conditions. Note the
effective capacitor value in the use conditions.
Calculate ratings of the input capacitor by the following formula:
VCIN > VIN
VCIN : Withstand voltage of the input capacitor [V]
VIN : Power supply voltage [V]
VOUT¯ (VIN VOUT)
Irms IOMAX ¯
VIN
Irms : Allowable ripple current of input capacitor (effective value) [A]
IOMAX : Maximum load current value [A]
VIN : Power supply voltage [V]
VOUT : Output setting voltage [V]
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Selection of output capacitor
A certain level of ESR is required for stable operation of this IC. Use a tantalum capacitor or polymer
capacitor as the output capacitor. If using a ceramic capacitor with low ESR, a resistor should be connected
in series with it to increase ESR equivalently.
Calculate the output capacitor value by the following formula as a guide.
1
COUT 4 ¯fOSC ¯ ESR
COUT : Output capacitor value [F]
fOSC : Switching frequency [Hz]
ESR : Series resistance of output capacitor []
Moreover, the output capacitor values are also derived from the allowable amount of overshoot and
undershoot. The following formula is represented as the worst condition in which the shift time for a sudden
load change is 0s. The output capacitor value allow a smaller amount than the value calculated by the
following formula when a longer shift time.
ΔIOUT
2 ¯ L
COUT 2 ¯ VOUT ¯ ΔVOUT_OVER Overshoot condition
ΔIOUT
2 ¯ L ¯ (VOUT + VIN ¯ fOSC ¯ tOFF_MIN)
COUT 2 ¯ VOUT ¯ ΔVOUT_UNDER ¯ (VIN VOUT VIN ¯ fOSC ¯ tOFF_MIN) Undershoot condition
COUT : Output capacitor value [F]
ΔVOUT_OVER : Allowable amount of output voltage overshoot [V]
ΔVOUT_UNDER : Allowable amount of output voltage undershoot [V]
ΔIOUT : Current difference in sudden load change [A]
L : Inductor value [H]
VIN : Power supply voltage [V]
VOUT : Output setting voltage [V]
fOSC : Switching frequency [Hz]
tOFF_MIN : Minimum off time
When changing to no load suddenly, the output voltage is overshoot, however, the current sink is not
executed in the mode other than PWM fix. As a result, the decrement of the output voltage might take a
long time. This sometimes results in the stop mode because of the over voltage detection. In the mode other
than PWM fix, select the capacitor value so that the overshoot value is set to the over voltage detection
voltage value or less (115% of the output setting voltage or less).
The capacitor has frequency, operating temperature, and bias voltage characteristics, etc. Therefore, it must
be noted that its effective capacitor value may be significantly smaller, depending on the use conditions.
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Calculate each rating of the output capacitor by the following formula:
VCOUT > VOUT
VCOUT : Withstand voltage of the output capacitor [V]
VOUT : Output voltage [V]
ΔIL
IRMS
23
IRMS : Allowable ripple current of output capacitor (effective value) [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
When connecting resistance in series configuration while a ceramic capacitor is in use, the resistor rating is
calculated by the following formula.
ESR¯ΔIL
2
PESR > 12
PESR : Power dissipation of resistor [W]
ESR : Resistor value []
ΔIL : Ripple current peak-to-peak value of inductor [A]
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Selection of bootstrap capacitor
To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. 0.1 µF is
assumed to be standard, however, it is necessary to adjust it when the high-side FET QG is big. Consider the
capacitor value calculated by the following formula as the lowest value for the bootstrap capacitor and
select a thing any more.
CBST 10¯QG
CBST : Bootstrap capacitor value [F]
QG : Total quantity of charge for the high-side FET gate [C]
Calculate ratings of the bootstrap capacitor by the following formula:
VCBST > VB
VCBST : Withstand voltage of the bootstrap capacitor [V]
VB : VB voltage [V]
VB pin capacitor
4.7 µF is assumed to be a standard, and when QG of switching FET used is large, it is necessary to adjust it.
To suppress the ripple voltage by the switching FET gate drive, consider the capacitor value calculated by
the following formula as the lowest value for VB capacitor and select a thing any more.
CVB 50¯QG
CVB : VB pin capacitor value [F]
QG : Total amount of gate charge of high-side FET and low-side switching FET for 2CH [C]
Calculate ratings of the VB pin capacitor by the following formula:
VCVB > VB
VCVB : Withstand voltage of the VB pin capacitor [V]
VB : VB voltage [V]
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Layout
Consider the points listed below and do the layout design.
y Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor
connected with the VCC and VB pins, and GND pin of the switching system parts with switching system
GND (PGND). Connect other GND connection pins with control system GND (AGND), and separate
each GND, and try not to pass the heavy current path through the control system GND (AGND) as much
as possible. In that case, connect control system GND (AGND) and switching system GND (PGND) at
the single point of GND (PGND) directly below IC. Switching system parts are Input capacitor (CIN),
Switching FET, fly-back diode (SBD), inductor (L) and Output capacitor (COUT).
y Connect the switching system parts as much as possible on the surface. Avoid the connection through the
through-hole as much as possible.
y As for GND pins of the switching system parts, provide the through hole at the proximal place, and
connect it with GND of internal layer.
y Pay the most attention to the loop composed of input capacitor (CIN), switching FET, and fly-back diode
(SBD). Consider parts are disposed mutually to be near for making the current loop as small as possible.
y Place the bootstrap capacitor (CBST1, CBST2) proximal to BSTx and LXx pins of IC as much as possible.
y Connect the line to the LX pin proximal to the drain pin of low-side FET. Also large electric current
flows momentary in this net. Wire the line of width of about 0.8 mm as standard, and as short as possible.
y Large electric current flows momentary in the net of DRVHx and DRVLx pins connected with the gate of
switching FET. Wire the linewidth of about 0.8 mm to be a standard, as short as possible. Take special
care about the line of the DRVLx pin, and wire the line as short as possible.
y By-pass capacitor (CVCC, CVB) connected with VCC, and VB should be placed close to the pin as much as
possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal
through-hole.
y Pull the feedback line to be connected to the VOUTx pin of the IC separately from near the output
capacitor pin, whenever possible. Consider the line connected with VOUTx and FBx pins to keep away
from a switching system parts as much as possible because it is sensitive to the noise.
Also, place the output voltage setting resistor connected to this line near IC, and try to shorten the line to
the FBx pin. In addition, for the internal layer right under the component mounting place, provide the
control system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the
power supply as much as possible.
Consider that the discharge current momentary flows into the VOUTx pin (about 200 mA at Vout = 5 V)
when the DC/DC operation stops, and then sustain the width for the feedback line.
There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and
parts sensitive to noise should be considered to be placed away from the inductor (or backside of place
equipped with inductor).
1pin
AGND
AGND
PGND
PGND
CBST2
CVCC
CVB
CBST1
SBD(option)
PGND
VIN
CIN
LL
CIN
SBD (option)
COUT COUT
VOUT1 VOUT2
Layout example of IC peripheral Layout example of switching system parts
Through-hole
Connect AGND and PGND right under IC
Surface Internal
layer
Output voltage setting
resistor layout
Low-side FET
To the LX1 pin
Low-side FET
To the LX2 pin
Output voltage
VOUT2 feedback
Output voltage
VOUT1 feedback
High-side FET High-side FET
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REFERENCE DATA
Conversion Efficiency vs.Load Current Conversion Efficiency vs.Load Current
Conversion Efficiency η (%)
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1 10
PFM/PWM
PAF PWM
V
IN
= 12 V
V
OUT1
= 1.0 V
FREQ = Open
Ta = +25°C
Conversion Efficiencyη (%)
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1 10
PFM/PWM
PAF
V
IN
= 12 V
V
OUT2
= 1.8 V
FREQ = Open
Ta = +25°C
PWM
Load Current IOUT1 (A) Load Current IOUT2 (A)
Switching Frequency vs. Load Current Switching Frequency vs. Load Current
Switching Frequency fosc1 (kHz)
1000
100
10
1
0.001 0.01 0.1 1 1
0
PFM/PWM
PAF
V
IN
= 12 V
V
OUT1
= 1.0 V
FREQ = Open
Ta = + 2 5 °C
PWM
Switching Frequency fosc2 (kHz)
1000
100
10
1
0.001 0.01 0.1 1 1
0
PFM/PWM
PAF
V
IN
= 12 V
V
OUT2
= 1.8 V
FREQ = Open
Ta = +25°C
PWM
Load Current IOUT1(A) Load Current IOUT2 (A)
Output Voltage vs. Load Current Output Voltage vs. Load Current
Output Voltage VOUT1 (V)
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
0.001 0.01 0.1 1 10
PFM/PWM
PAF
V
IN
= 12 V
V
OUT1
= 1.0 V
FREQ = Open
Ta = +25°C
PWM
Output Voltage VOUT2 (V)
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
0.001 0.01 0.1 1 1
0
PFM/PWM
PAF
VIN = 12 V
VOUT2 = 1.8 V
FREQ = Open
Ta = + 2 5 °C
PWM
Load Current IOUT1 (A) Load Current IOUT2 (A)
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Ripple Waveform
V
IN
=12 V, V
OUT1
=1.0 V, I
OUT1
=0 A, MODE=GND,
FREQ=Open, Ta=+25°C
V
OUT1
20 mV/div
100 ms/div
V
IN
=12 V, V
OUT2
=1.8 V, I
OUT2
=0 A, MODE=GND,
FREQ=Open, Ta=+25°C
V
OUT2
20 mV/div
20 ms/div
V
IN
=12 V, V
OUT1
=1.0 V, I
OUT1
=7 A, MODE=GND,
FREQ=Open, Ta=+25°C
VOUT1 20 mV/div
2 µs/div
V
IN
=12 V, V
OUT2
=1.8 V, I
OUT2
=7 A, MODE=GND,
FREQ=Open, Ta=+25°C
V
OUT2
20 mV/div
2 µs/div
Load Sudden Change Waveform
VIN=12 V, VOUT1=1.0 V, IOUT1=0 A 4 A, MODE=GND,
FREQ=Open, Ta=+25°C
V
OUT1
50 mV/div
I
OUT1
2 A/div
10 µs/div
4 A
0 A
V
IN
=12 V, V
OUT2
=1.8 V, I
OUT2
=0 A 4 A, MODE=GND,
FREQ=Open, Ta=+25°C
V
OUT2
50 mV/div
I
OUT2
2 A/div
10 µs/div
4 A
0 A
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EN Startup and Shutdown Waveform
V
IN
=12 V, V
OUT1
=1.0 V, I
OUT1
=7 A (0.14 ), MODE=GND,
FREQ=Open, Ta=+25°C
EN1 10 V/div
V
OUT1
500 mV/div
LX1 10 V/div
500 µs/div
V
IN
=12V, V
OUT2
=1.8 V, I
OUT2
=7 A (0.26 ), MODE=GND,
FREQ=Open, Ta=+25°C
EN1 10V/div
VOUT1 500 mV/div
LX1 10V/div
500 µs/div
Output Over Current Waveform
V
IN
=12 V, V
OUT1
=1.0 V,MODE=VB,FREQ=Open, Ta=+25°C
I
OUT1
5 A/div
V
OUT1
500 mV/div
LX1 10 V/div
100 µs/div
Normal operation Over current
limitation
Under voltage protection
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USAGE PRECAUTION
1. Do not configure the IC over the maximum ratings.
If the IC is used over the maximum ratings, the LSI may be permanently damaged.
It is preferable for the device to normally operate within the recommended usage conditions. Usage outside
of these conditions can have an adverse effect on the reliability of the LSI.
2. Use the device within the recommended operating conditions.
The recommended values guarantee the normal LSI operation under the recommended operating conditions.
The electrical ratings are guaranteed when the device is used within the recommended operating conditions
and under the conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common impedance.
4. Take appropriate measures against static electricity.
y Containers for semiconductor materials should have anti-static protection or be made of conductive
material.
y After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
y Work platforms, tools, and instruments should be properly grounded.
y Working personnel should be grounded with resistance of 250 k to 1 M in serial body and ground.
5. Do not apply negative voltages.
The use of negative voltages below 0.3 V may make the parasitic transistor activated to the LSI, and can
cause malfunctions.
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ORDERING INFORMATION
Part number Package Remarks
MB39A214APFT 24-pin plastic TSSOP
(FPT-24P-M09)
EV BOARD ORDERING INFORMATION
EV board number EV board version No. Remarks
MB39A214A-EVB-01 MB39A214A-EVB-01 Rev. 1.0 TSSOP-24
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RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of FUJITSU SEMICONDUCTOR with “E1” are compliant with RoHS Directive, and has
observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB),
and polybrominated diphenyl ethers (PBDE). A product whose part number has trailing characters “E1” is
RoHS compliant.
MARKING FORMAT (Lead Free version)
XXXX
39A214A
XXX
E1
INDEX
Lead-free version
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LABELING SAMPLE (Lead free version)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead-free mark
JEITA logo JEDEC logo
The part number of a lead-free product has
the trailing characters "E1".
"ASSEMBLED IN CHINA" is printed on the label
of a product assembled in China.
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MB39A214APFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY
LEVEL
[FUJITSU SEMICONDUCTOR Recommended Mounting Conditions]
Item Condition
Mounting Method IR (infrared reflow), warm air reflow
Mounting times 2 times
Before opening Please use it within two years after
manufacture.
From opening to the 2nd reflow Less than 8 days
Storage period
When the storage period after
opening was exceeded
Please process within 8 days
after baking (125°C ±3°C, 24H+ 2H/0H) .
Baking can be performed up to two times.
Storage conditions 5°C to 30°C, 70% RH or less (the lowest possible humidity)
[Mounting Conditions]
(1) IR (infrared reflow)
260°C
(e)
(d')
(d)
245°C
170 °C
190 °C
RT (b)
(a)
(c)
to
Main heating
"M" rank : 250°C Max
(a) Temperature Increase gradient : Average 1°C/s to 4°C /s
(b) Preliminary heating : Temperature 170°C to 190°C, 60 s to 180 s
(c) Temperature Increase gradient : Average 1°C /s to 4°C /s
(d) Peak temperature : Temperature 250°C Max; 245°C or more, 10 s or less
(d') Main Heating : Temperature 230°C or more, 40 s or less
or
Temperature 225°C or more, 60 s or less
or
Temperature 220°C or more, 80 s or less
(e) Cooling : Natural cooling or forced cooling
Note: Temperature : the top of the package bod
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS405-00007-1v0-E
(2) Manual soldering (partial heating method)
Item Condition
Before opening Within two years after manufacture
Storage period
Between opening and mounting
Within two years after manufacture
(No need to control moisture during the storage
period because of the partial heating method.)
Storage conditions 5°C to 30°C, 70% RH or less (the lowest possible humidity)
Mounting conditions Temperature at the tip of a soldering iron: 400°C Max
Time: Five seconds or below per pin*
*: Make sure that the tip of a soldering iron does not come in contact with the package body.
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MB39A214A
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS405-00007-1v0-E
PACKAGE DIMENSIONS
24-pin plastic TSSOP Lead pitch 0.50 mm
Package width ×
package length 4.40 mm × 6.50 mm
Lead shape Gullwing
Sealing method Pl asti c mol d
Mounting height 1.20 mm MAX
Weight 0.08 g
24-pin plastic TSSOP
(FPT-24P-M09)
(FPT-24P-M09)
C
2007-2010 FUJITS U SEMICONDUCTOR LIMITED F24032S-c-2-5
6.50± 0.10 (.256±. 004)
#
4.40± 0.10 6.40± 0.20
(.252±. 008)
(.173±. 004)
#
0.10± 0.05
(Mounting height)
0.10(.004)
0.50(.020)
112
24 13
"A"
(Stand off)
0.145± 0.045
(.0057±. 0018)
M
0.13(.005)
Details of "A" part
0~8°
(.024±. 006)
0.60± 0.15
INDEX
(.004±. 002)
BTM E-MARK
1.10
+0.10
+.004
–0.15
–.006
.043
0.20
+0.07
+.003
–0.02
–.001
.008
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS405-00007-1v0-E
CONTENTS
page
DESCRIPTION.................................................................................................................................1
FEATURES ....................................................................................................................................... 1
APPLICATIONS...............................................................................................................................1
PIN ASSIGNMENT.......................................................................................................................... 2
PIN DESCRIPTIONS .......................................................................................................................3
BLOCK DIAGRAM ......................................................................................................................... 4
ABSOLUTE MAXIMUM RATINGS .............................................................................................. 5
RECOMMENDED OPERATING CONDITIONS........................................................................... 6
ELECTRICAL CHARACTERISTICS............................................................................................. 7
TYPICAL CHARACTERISTICS...................................................................................................10
FUNCTION.....................................................................................................................................13
I/O PIN EQUIVALENT CIRCUIT DIAGRAM.............................................................................22
EXAMPLE APPLICATION CIRCUIT ..........................................................................................24
PART LIST......................................................................................................................................25
APPLICATION NOTE ...................................................................................................................26
REFERENCE DATA.......................................................................................................................42
USAGE PRECAUTION ................................................................................................................. 45
ORDERING INFORMATION........................................................................................................46
EV BOARD ORDERING INFORMATION ..................................................................................46
RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION ................................47
MARKING FORMAT (Lead Free version)....................................................................................47
LABELING SAMPLE (Lead free version) ....................................................................................48
MB39A214APFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL49
PACKAGE DIMENSIONS.............................................................................................................51
CONTENTS ....................................................................................................................................52
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS405-00007-1v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS405-00007-1v0-E
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DS405-00007-1v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
DS405-00007-1v0-E
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road,
Pudong District, Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of
any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR
assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would
result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department