Intel® Celeron® Mobile Processor
Dual-Core on 45-nm Process
Datasheet
For Platforms Based on Mobile Intel® 4 Series Express Chipset Family
September 2009
Document Number: 321111-003
2Datasheet
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Datasheet 3
Contents
1Introduction..............................................................................................................7
1.1 Terminology .......................................................................................................8
1.2 References .........................................................................................................9
2 Low Power Features ................................................................................................ 11
2.1 Clock Control and Low Power States .................................................................... 11
2.1.1 Core Low-Power States ........................................................................... 12
2.1.2 Package Low-Power States ...................................................................... 13
2.2 Low-Power FSB Features .................................................................................... 15
2.3 Processor Power Status Indicator (PSI#) Signal..................................................... 15
3 Electrical Specifications ........................................................................................... 17
3.1 Power and Ground Pins ...................................................................................... 17
3.2 FSB Clock (BCLK[1:0]) and Processor Clocking...................................................... 17
3.3 Voltage Identification......................................................................................... 17
3.4 Catastrophic Thermal Protection .......................................................................... 20
3.5 Reserved and Unused Pins.................................................................................. 20
3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 21
3.7 FSB Signal Groups............................................................................................. 21
3.8 CMOS Signals ................................................................................................... 23
3.9 Maximum Ratings.............................................................................................. 23
3.10 Processor DC Specifications ................................................................................ 24
4 Package Mechanical Specifications and Pin Information .......................................... 29
4.1 Package Mechanical Specifications ....................................................................... 29
4.2 Processor Pinout and Pin List .............................................................................. 33
4.3 Alphabetical Signals Reference ............................................................................ 53
5 Thermal Specifications and Design Considerations .................................................. 61
5.1 Monitoring Die Temperature ............................................................................... 61
5.1.1 Thermal Diode ....................................................................................... 62
5.1.2 Thermal Diode Offset .............................................................................. 64
5.1.3 Intel® Thermal Monitor........................................................................... 65
5.1.4 Digital Thermal Sensor............................................................................ 66
5.1.5 Out of Specification Detection .................................................................. 67
5.1.6 PROCHOT# Signal Pin ............................................................................. 67
4Datasheet
Figures
1 Package-Level Low-Power States ................................................................................11
2 Core Low-Power States .............................................................................................12
3 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2).................30
4 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2).................31
5 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ........................................32
6 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ........................................33
Tables
1 Coordination of Core-Level Low-Power States at the Package Level .................................11
2 Voltage Identification Definition ..................................................................................17
3 BSEL[2:0] Encoding for BCLK Frequency......................................................................21
4 FSB Pin Groups ........................................................................................................22
5 Processor Absolute Maximum Ratings..........................................................................23
6 DC Voltage and Current Specifications.........................................................................25
7 FSB Differential BCLK Specifications............................................................................26
8 AGTL+ Signal Group DC Specifications ........................................................................27
9 CMOS Signal Group DC Specifications..........................................................................28
10 Open Drain Signal Group DC Specifications ..................................................................28
11 The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 1 of 2) ..........................................................................................................34
12 The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 2 of 2) ..........................................................................................................35
13 Pin Listing by Pin Name .............................................................................................37
14 Pin Listing by Pin Number ..........................................................................................44
15 Signal Description.....................................................................................................53
16 Power Specifications for the Intel Celeron Dual-Core Processor - Standard Voltage ............61
17 Thermal Diode Interface ............................................................................................62
18 Thermal Diode Parameters Using Diode Model ..............................................................63
19 Thermal Diode Parameters Using Transistor Model ........................................................64
20 Thermal Diode ntrim and Diode Correction Toffset ........................................................65
Datasheet 5
Revision History
§
Document
Number
Revision
Number Description Date
321111 -001 • Initial Release November 2008
321111 -002 • Added T3000, T3100, T3300, and T3500 processors June 2009
321111 -003
• Added specifications for SFF processor SU2300
• Added C4 state support information for SU2300 SFF
processor
• Added Speedstep technology suppport information for
SU2300 SFF processor
•details:
•Chapter 1: updated feature list for SFF processor
•Section 2.1: added C4/deeper sleep state information
•Figure 1: updated C4/deeper sleep state information
•Figure 2: updated C4/deeper sleep state information
•Table 1: Added C4/deeper sleep state information
•Section Section 2.1.1.6, Section 2.1.2.6: Added C4/deeper
sleep state information
•Section 2.2: Added information on Intel speedstep
technology description
•Table 8: added table for SU2300 processor DC specifications
•Table 25 : added table for SU2300 thermal specifications
•Figure 7, Tabl e 1 9 , Ta b l e 2 0 , Table 1 7 , Ta b l e 2 3 added
SU2300 pin and package information
September 2009
6Datasheet
Datasheet 7
Introduction
1 Introduction
This document provides electrical, mechanical, and thermal specifications for the
Intel® Celeron® Mobile Processor Dual-Core T1x00, Intel(R) Celeron Processors T3x00
and Intel(R) Celeron Dual-core SFF Processors. The processor supports the Mobile
Intel® 4 Series Express Chipset and Intel® 82801IBM (ICH9M) Controller-Hub Based
Systems.
Note: In this document, the Celeron processor is referred to as the processor and Mobile
Intel® 4 Series Express Chipset family is referred to as the (G)MCH.
The following list provides some of the key features on this processor:
• Dual-Core processor for mobile with enhanced performance
• Intel architecture with Intel® Wide Dynamic Execution
• L1 Cache to Cache (C2C) transfer
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each
core
• On-die, 1-MB second level shared cache with advanced transfer cache architecture
• Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and
Supplemental Streaming SIMD Extensions 3 (SSSE3)
• 667-MHz Source-Synchronous Front Side Bus (FSB) for the T1x00 Series, and 800-
MHz Source-Synchronous Front Side Bus (FSB) for the T3x00 Series processors
and SFF processors
• Digital Thermal Sensor (DTS)
• Intel® 64 Technology
• PSI2 functionality
• Execute Disable Bit support for enhanced security
• Half ratio support (N/2) for Core to Bus ratio
• Supports enhanced Intel® Virtualization Technology (SFF processor only)
• Intel® Deeper Sleep low-power state with P_LVL4 I/O Support (SFF processor
only)
• Advanced power management feature includes Enhanced Intel SpeedStep®
Technology (SFF processor only)
Introduction
8 Datasheet
1.1 Terminology
Term Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
XXXX means that the specification or value is yet to be determined.
Front Side Bus
(FSB)
Refers to the interface between the processor and system core logic (also
known as the chipset components).
AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
Storage
Conditions
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor landings should not
be connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
Enhanced Intel
SpeedStep®
Technology
Technology that provides power management capabilities to laptops.
Processor Core Processor core die with integrated L1 and L2 cache. All AC timing and
signal integrity specifications are at the pads of the processor core.
Intel® 64
Technology 64-bit memory extensions to the IA-32 architecture.
Intel®
Virtualization
Technology
Processor virtualization which when used in conjunction with Virtual
Machine Monitor software enables multiple, robust independent software
environments inside a single platform.
TDP Thermal Design Power
VCC The processor core power supply
VSS The processor ground
Datasheet 9
Introduction
1.2 References
Material and concepts available in the following documents may be beneficial when
reading this document.
Document Document Number
Intel® Celeron® Dual-Core T1x00 Processors Specification Update
for Platforms Based on Mobile Intel® 4 Series Express Chipset Family
See http://
www.intel.com/design/
mobile/specupdt/
319734.htm
Mobile Intel® 4 Series Express Chipset Family Datasheet 355969
Mobile Intel® 4 Series Express Chipset Family Specification Update 320123
Intel® I/O Controller Hub 9(ICH9)/ I/O Controller Hub 9M (ICH9M)
Datasheet
See http://
www.intel.com/Assets/
PDF/datasheet/
316972.pdf
Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M)
Specification Update
See http://
www.intel.com/Assets/
PDF/specupdate/
316973.pdf
Intel® 64 and IA-32 Architectures Software Developer’s Manual
See http://
www.intel.com/design/
pentium4/manuals/
index_new.htm
Intel® 64 and IA-32 Architectures Software Developer's Manuals
Documentation Change
See http://
developer.intel.com/
design/processor/
specupdt/252046.htm
Volume 1: Basic Architecture 253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide 253668
Volume 3B: System Programming Guide 253669
Introduction
10 Datasheet
Datasheet 11
Low Power Features
2 Low Power Features
2.1 Clock Control and Low Power States
The processor supports the C1/AutoHALT, C1/MWAIT, C2, C3 and some support the C4
core low-power states, along with their corresponding package-level states for power
management. See Chapter 3 to see if C4 is supported. These package states include
Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep Sleep. The processor’s central
power management logic enters a package low-power state by initiating a P_LVLx
(P_LVL2, P_LVL3, P_LVL4) I/O read to the (G)MCH. Figure 1 shows the package-level
low-power states and Figure 2 shows the core low-power states. Refer to Tabl e 1 for a
mapping of core low-power states to package low-power states.
The processor implements two software interfaces for requesting low-power states:
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK
register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are
converted to equivalent MWAIT C-state requests inside the processor and do not
directly result in I/O reads on the processor FSB. The monitor address does not need to
be setup before using the P_LVLx I/O read interface. The sub-state hints used for each
P_LVLx read can be configured through the IA32_MISC_ENABLES Model Specific
Register (MSR).
If the processor encounters a chipset break event while STPCLK# is asserted, it asserts
the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to
system logic that the processor should return to the Normal state.
NOTE: AutoHALT or MWAIT/C1
Table 1. Coordination of Core-Level Low-Power States at the Package Level
Core States Package States
C0 Normal
C1(1) Normal
C2 Stop Grant
C3 Deep Sleep
C4 Deeper Sleep
Figure 1. Package-Level Low-Power States
Stop Grant
Snoop
Normal Stop
Grant
Deep
Sleep
STPCLK# asserted
Snoop
serviced
Snoop
occurs
Deeper
Sleep†
Sleep
SLP# asserted
SLP# deasserted
DPSLP# asserted
DPSLP# deasserted DPRSTP# deasserted
DPRSTP# asserted
STPCLK# deasserted
† — Deeper Sleep includes the Deeper Sleep state and Deep C4 sub-state
Low Power Features
12 Datasheet
2.1.1 Core Low-Power States
2.1.1.1 C0 State
This is the normal operating state of the processor.
2.1.1.2 C1/AutoHALT Powerdown State
C1/AutoHALT is a low-power state entered when the processor core executes the HALT
instruction. The processor core transitions to the C0 state upon the occurrence of
SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# causes the
processor to immediately initialize itself.
A System Management Interrupt (SMI) A System Management Interrupt (SMI) handler
returns execution to either Normal state or the C1/AutoHALT Powerdown state. See the
Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A/3B:
System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the C1/AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
returns execution to the HALT state.
The processor in C1/AutoHALT powerdown state process only the bus snoops. The
processor enters a snoopable sub-state (not shown in Figure 2) to process the snoop
and then return to the C1/AutoHALT Powerdown state.
Figure 2. Core Low-Power States
C2†
C0
Stop
Grant
Core state
break
P_LVL2 or
MWAIT(C2)
C3†
Core
state
break
P_LVL3 or
MWAIT(C3)
C1/MWAIT
Core state
break
MWAIT(C1)
C1/Auto
Halt
Halt break
HLT instruction
C4† ‡
Core State
break
P_LVL4
MWAIT(C4)
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
asserted
break
= A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
e
state break
= (halt break OR Monitor event) AND STPCLK# high (not asserted)
STPCLK
# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
Core C
4 state supports the package level Deep C4 sub-state.
Datasheet 13
Low Power Features
2.1.1.3 C1/MWAIT Powerdown State
C1/MWAIT is a low-power state entered when the processor core executes the MWAIT
instruction. Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT
state except that there is an additional event that can cause the processor core to
return to the C0 state: the Monitor event. See the Intel® 64 and IA-32 Intel®
Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference
for more information.
2.1.1.4 Core C2 State
The core of the processor can enter the C2 state by initiating a P_LVL2 I/O read to the
P_BLK or an MWAIT(C2) instruction, but the processor does not issue a Stop Grant
Acknowledge special bus cycle unless the STPCLK# pin is also asserted.
The processor in C2 state processes only the bus snoops. The processor enters a
snoopable sub-state (not shown in Figure 2) to process the snoop and then return to
the C2 state.
2.1.1.5 Core C3 State
Core C3 state is a very low-power state the processor core can enter while maintaining
context. The core of the processor can enter the C3 state by initiating a P_LVL3 I/O
read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the
processor core flushes the contents of its L1 cache into the processor’s L2 cache.
Except for the caches, the processor core maintains all its architectural state in the C3
state. The Monitor remains armed if it is configured. All of the clocks in the processor
core are stopped in the C3 state.
Because the core’s caches are flushed, the processor keeps the core in the C3 state
when the processor detects a snoop on the FSB. The processor core transitions to the
C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR),
or FSB interrupt message. RESET# causes the processor core to immediately initialize
itself.
2.1.1.6 Core C4 State
Individual cores of the dual-core processor that have C4 can enter the C4 state by
initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor
core behavior in the C4 state is nearly identical to the behavior in the C3 state. The
only difference is that if both processor cores are in C4, the central power management
logic will request that the entire processor enter the Deeper Sleep package low-power
state (see Section 2.1.2.6)
2.1.2 Package Low-Power States
Package level low-power states are applicable to the processor.
2.1.2.1 Normal State
This is the normal operating state for the processor. The processor enters the Normal
state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state.
2.1.2.2 Stop-Grant State
When the STPCLK# pin is asserted the core of the processor enters the Stop-Grant
state within 20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core returns
to the previous core low-power state.
Low Power Features
14 Datasheet
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to VCCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor stays in
Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, and
DPSLP# pins must be deasserted more than 480 µs prior to RESET# deassertion (AC
Specification T45). When re-entering the Stop-Grant state from the Sleep state,
STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#
(AC Specification T75).
While in the Stop-Grant state, the processor services snoops and latch interrupts
delivered on the FSB. The processor latches SMI#, INIT# and LINT[1:0] interrupts and
services only upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# is
asserted if there is any pending interrupt or monitor event latched within the processor.
Pending interrupts that are blocked by the EFLAGS.IF bit being clear still cause
assertion of PBE#. Assertion of PBE# indicates to system logic that the processor
should return to the Normal state.
A transition to the Stop Grant Snoop state occurs when the processor detects a snoop
on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)
occurs with the assertion of the SLP# signal.
2.1.2.3 Stop Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in Stop-
Grant state by entering the Stop-Grant Snoop state. The processor stays in this state
until the snoop on the FSB has been serviced (whether by the processor or another
agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-
Grant state once the snoop has been serviced or the interrupt has been latched.
2.1.2.4 Sleep State
The Sleep state is a low-power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#
pin should only be asserted when the processor is in the Stop-Grant state. SLP#
assertions while the processor is not in the Stop-Grant state is out of specification and
may result in unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state causes unpredictable behavior. Any transition on an input signal before the
processor has returned to the Stop-Grant state results in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor resets itself, ignoring the
transition through Stop-Grant state. If RESET# is driven active while the processor is in
the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after
RESET# is asserted to ensure the processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 2.1.2.5.) While
the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur.
Datasheet 15
Low Power Features
2.1.2.5 Deep Sleep State
Deep Sleep state is a very low-power state the processor can enter while maintaining
context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on appropriate chipset based platforms with
the CK505 clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of
DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-
started after DPSLP# deassertion as described above. A period of 15 microseconds (to
allow for PLL stabilization) must occur before the processor can be considered to be in
the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter
the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. Any transition on an input signal before
the processor has returned to Stop-Grant state results in unpredictable behavior.
2.1.2.6 Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but further reduces core
voltage levels. One of the potential lower core voltage levels is achieved by entering the
base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is
achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of
Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of
the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely
shut down.
Exit from Deeper Sleep is initiated by DPRSTP# deassertion when either core requests
a core state other than C4 or either core requests a processor performance state other
than the lowest operating point.
2.2 Enhanced Intel SpeedStep® Technology
Some processors feature Enhanced Intel SpeedStep Technology. See each processor’s
DCL to see if it supports Enhanced Intel SpeedStep Technology. Following are the key
features of Enhanced Intel SpeedStep Technology:
• Multiple voltage and frequency operating points provide optimal performance at the
lowest power.
• Voltage and frequency selection is software-controlled by writing to processor
MSRs:
— If the target frequency is higher than the current frequency, VCC is ramped up
in steps by placing new values on the VID pins, and the PLL then locks to the
new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
new frequency and the VCC is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in
progress, the new transition is deferred until the previous transition completes.
Low Power Features
16 Datasheet
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Low transition latency and large number of transitions possible per second:
— Processor core (including L2 cache) is unavailable for up to 10 μs during the
frequency transition.
— The bus protocol (BNR# mechanism) is used to block snooping.
• Improved Intel® Thermal Monitor mode:
— When the on-die thermal sensor indicates that the die temperature is too high
the processor can automatically perform a transition to a lower frequency and
voltage specified in a software-programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to
acceptable levels, an up-transition to the previous frequency and voltage point
occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions
enabling better system-level thermal management.
• Enhanced thermal management features:
— Digital Thermal Sensor and Out of Specification detection.
— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in
case of unsuccessful TM2 transition.
— Dual core thermal management synchronization.
Each core in the dual-core processor implements an independent MSR for controlling
Enhanced Intel SpeedStep Technology, but both cores must operate at the same
frequency and voltage. The processor has performance state coordination logic to
resolve frequency and voltage requests from the two cores into a single frequency and
voltage request for the package as a whole. If both cores request the same frequency
and voltage, then the processor will transition to the requested common frequency and
voltage. If the two cores have different frequency and voltage requests, then the
processor will take the highest of the two frequencies and voltages as the resolved
request and transition to that frequency and voltage.
Caution: Enhanced Intel SpeedStep Technology transitions are multistep processes
that require clocked control. These transitions cannot occur when the processor is in
the Sleep or Deep Sleep package low-power states since processor clocks are not
active in these states.
2.3 Low-Power FSB Features
The processor incorporates FSB low-power enhancements:
• Dynamic On Die Termination disabling
•Low V
CCP (I/O termination voltage)
The On Die Termination on the processor FSB buffers is disabled when the signals are
driven low, resulting in power savings. The low I/O termination voltage is on a
dedicated voltage plane independent of the core voltage, enabling low I/O switching
power at all times.
Datasheet 17
Low Power Features
2.4 Processor Power Status Indicator (PSI#) Signal
The PSI# signal is asserted when the processor is in a reduced power consumption
state. PSI# can be used to improve light load efficiency of the voltage regulator,
resulting in platform power savings and extended battery life. The algorithm that the
processor uses for determining when to assert PSI# is different from the algorithm
used in previous processors.
Low Power Features
18 Datasheet
Datasheet 19
Electrical Specifications
3 Electrical Specifications
3.1 Power and Ground Pins
For clean, on-chip power distribution, the processor has a large number of VCC (power)
and VSS (ground) inputs. All power pins must be connected to VCC power planes while
all VSS pins must be connected to system ground planes. Use of multiple power and
ground planes is recommended to reduce I*R drop. The processor VCC pins must be
supplied the voltage determined by the VID (Voltage ID) pins.
3.2 FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor uses a differential clocking
implementation.
3.3 Voltage Identification
The processor uses seven voltage identification pins,VID[6:0], to support automatic
selection of power supply voltages. The VID pins for processor are CMOS outputs
driven by the processor VID circuitry. Tab l e 2 specifies the voltage level corresponding
to the state of VID[6:0]. A 1 refers to a high-voltage level and a 0 refers to low-voltage
level.
Table 2. Voltage Identification Definition (Sheet 1 of 4)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
0 0 0 0 0 0 0 1.5000
0 0 0 0 0 0 1 1.4875
0 0 0 0 0 1 0 1.4750
0 0 0 0 0 1 1 1.4625
0 0 0 0 1 0 0 1.4500
0 0 0 0 1 0 1 1.4375
0 0 0 0 1 1 0 1.4250
0 0 0 0 1 1 1 1.4125
0 0 0 1 0 0 0 1.4000
0 0 0 1 0 0 1 1.3875
0 0 0 1 0 1 0 1.3750
0 0 0 1 0 1 1 1.3625
0 0 0 1 1 0 0 1.3500
0 0 0 1 1 0 1 1.3375
0 0 0 1 1 1 0 1.3250
0 0 0 1 1 1 1 1.3125
0 0 1 0 0 0 0 1.3000
0 0 1 0 0 0 1 1.2875
0 0 1 0 0 1 0 1.2750
0 0 1 0 0 1 1 1.2625
0 0 1 0 1 0 0 1.2500
0 0 1 0 1 0 1 1.2375
Electrical Specifications
20 Datasheet
0 0 1 0 1 1 0 1.2250
0 0 1 0 1 1 1 1.2125
0 0 1 1 0 0 0 1.2000
0 0 1 1 0 0 1 1.1875
0 0 1 1 0 1 0 1.1750
0 0 1 1 0 1 1 1.1625
0 0 1 1 1 0 0 1.1500
0 0 1 1 1 0 1 1.1375
0 0 1 1 1 1 0 1.1250
0 0 1 1 1 1 1 1.1125
0 1 0 0 0 0 0 1.1000
0 1 0 0 0 0 1 1.0875
0 1 0 0 0 1 0 1.0750
0 1 0 0 0 1 1 1.0625
0 1 0 0 1 0 0 1.0500
0 1 0 0 1 0 1 1.0375
0 1 0 0 1 1 0 1.0250
0 1 0 0 1 1 1 1.0125
0 1 0 1 0 0 0 1.0000
0 1 0 1 0 0 1 0.9875
0 1 0 1 0 1 0 0.9750
0 1 0 1 0 1 1 0.9625
0 1 0 1 1 0 0 0.9500
0 1 0 1 1 0 1 0.9375
0 1 0 1 1 1 0 0.9250
0 1 0 1 1 1 1 0.9125
0 1 1 0 0 0 0 0.9000
0 1 1 0 0 0 1 0.8875
0 1 1 0 0 1 0 0.8750
0 1 1 0 0 1 1 0.8625
0 1 1 0 1 0 0 0.8500
0 1 1 0 1 0 1 0.8375
0 1 1 0 1 1 0 0.8250
0 1 1 0 1 1 1 0.8125
0 1 1 1 0 0 0 0.8000
0 1 1 1 0 0 1 0.7875
0 1 1 1 0 1 0 0.7750
0 1 1 1 0 1 1 0.7625
0 1 1 1 1 0 0 0.7500
0 1 1 1 1 0 1 0.7375
0 1 1 1 1 1 0 0.7250
0 1 1 1 1 1 1 0.7125
1 0 0 0 0 0 0 0.7000
1 0 0 0 0 0 1 0.6875
1 0 0 0 0 1 0 0.6750
1 0 0 0 0 1 1 0.6625
1 0 0 0 1 0 0 0.6500
Table 2. Voltage Identification Definition (Sheet 2 of 4)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
Datasheet 21
Electrical Specifications
1 0 0 0 1 0 1 0.6375
1 0 0 0 1 1 0 0.6250
1 0 0 0 1 1 1 0.6125
1 0 0 1 0 0 0 0.6000
1 0 0 1 0 0 1 0.5875
1 0 0 1 0 1 0 0.5750
1 0 0 1 0 1 1 0.5625
1 0 0 1 1 0 0 0.5500
1 0 0 1 1 0 1 0.5375
1 0 0 1 1 1 0 0.5250
1 0 0 1 1 1 1 0.5125
1 0 1 0 0 0 0 0.5000
1 0 1 0 0 0 1 0.4875
1 0 1 0 0 1 0 0.4750
1 0 1 0 0 1 1 0.4625
1 0 1 0 1 0 0 0.4500
1 0 1 0 1 0 1 0.4375
1 0 1 0 1 1 0 0.4250
1 0 1 0 1 1 1 0.4125
1 0 1 1 0 0 0 0.4000
1 0 1 1 0 0 1 0.3875
1 0 1 1 0 1 0 0.3750
1 0 1 1 0 1 1 0.3625
1 0 1 1 1 0 0 0.3500
1 0 1 1 1 0 1 0.3375
1 0 1 1 1 1 0 0.3250
1 0 1 1 1 1 1 0.3125
1 1 0 0 0 0 0 0.3000
1 1 0 0 0 0 1 0.2875
1 1 0 0 0 1 0 0.2750
1 1 0 0 0 1 1 0.2625
1 1 0 0 1 0 0 0.2500
1 1 0 0 1 0 1 0.2375
1 1 0 0 1 1 0 0.2250
1 1 0 0 1 1 1 0.2125
1 1 0 1 0 0 0 0.2000
1 1 0 1 0 0 1 0.1875
1 1 0 1 0 1 0 0.1750
1 1 0 1 0 1 1 0.1625
1 1 0 1 1 0 0 0.1500
1 1 0 1 1 0 1 0.1375
1 1 0 1 1 1 0 0.1250
1 1 0 1 1 1 1 0.1125
1 1 1 0 0 0 0 0.1000
1 1 1 0 0 0 1 0.0875
1 1 1 0 0 1 0 0.0750
1 1 1 0 0 1 1 0.0625
Table 2. Voltage Identification Definition (Sheet 3 of 4)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
Electrical Specifications
22 Datasheet
3.4 Catastrophic Thermal Protection
The processor supports the THERMTRIP# signal for catastrophic thermal protection. An
external thermal sensor should also be used to protect the processor and the system
against excessive temperatures. Even with the activation of THERMTRIP#, which halts
all processor internal clocks and activity, leakage current can be high enough that the
processor cannot be protected in all conditions without power removal to the processor.
If the external thermal sensor detects a catastrophic processor temperature of 125 °C
(maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor
must be turned off within 500 ms to prevent permanent silicon damage due to thermal
runaway of the processor. THERMTRIP# functionality is not guaranteed if the
PWRGOOD signal is not asserted.
3.5 Reserved and Unused Pins
All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC,
VSS, or to any other signal (including each other) may result in component malfunction
or incompatibility with future processors. See Section 4.2 for a pin listing of the
processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (VSS). Unused outputs can be left
unconnected.
The TEST1 and TEST2 pins must have a stuffing option of separate pull-down resistors
to VSS.
For the purpose of testability, route the TEST3 and TEST5 signals through a ground-
referenced Zo = 55-Ω trace that ends in a via that is near a GND via and is accessible
through an oscilloscope connection.
1 1 1 0 1 0 0 0.0500
1 1 1 0 1 0 1 0.0375
1 1 1 0 1 1 0 0.0250
1 1 1 0 1 1 1 0.0125
1 1 1 1 0 0 0 0.0000
1 1 1 1 0 0 1 0.0000
1 1 1 1 0 1 0 0.0000
1 1 1 1 0 1 1 0.0000
1 1 1 1 1 0 0 0.0000
1 1 1 1 1 0 1 0.0000
1 1 1 1 1 1 0 0.0000
1 1 1 1 1 1 1 0.0000
Table 2. Voltage Identification Definition (Sheet 4 of 4)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
Datasheet 23
Electrical Specifications
3.6 FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate
chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Tab l e 3 .
3.7 FSB Signal Groups
The FSB signals have been combined into groups by buffer type in the following
sections. AGTL+ input signals have differential input buffers, which use GTLREF as a
reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input
group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers
to the AGTL+ output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus, two sets of timing
parameters need to be specified. One set is for common clock signals, which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals, which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Tabl e 4 identifies which signals are common clock, source synchronous,
and asynchronous.
Table 3. BSEL[2:0] Encoding for BCLK Frequency
BSEL[2] BSEL[1] BSEL[0] BCLK Frequency
L L L RESERVED
L L H 133 MHz
L H H RESERVED
L H L 200 MHz
H H L RESERVED
H H H RESERVED
H L H RESERVED
H L L RESERVED
Electrical Specifications
24 Datasheet
NOTES:
1. Refer to Chapter 4 for signal descriptions and termination requirements.
2. In processor systems where there is no debug port implemented on the system board, these signals are
used to support a debug port interposer. In systems with the debug port implemented on the system
board, these signals are no connects.
3. BPM[2:1]# and PRDY# are AGTL+ output only signals.
4. PROCHOT# signal type is open drain output and CMOS input.
5. On die termination differs from other AGTL+ signals.
Table 4. FSB Pin Groups
Signal Group Type Signals1
AGTL+ Common Clock Input Synchronous
to BCLK[1:0] BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, TRDY#
AGTL+ Common Clock I/O Synchronous
to BCLK[1:0]
ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, PRDY#3, DPWR#
AGTL+ Source Synchronous
I/O
Synchronous
to assoc.
strobe
AGTL+ Strobes Synchronous
to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input Asynchronous A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output Asynchronous FERR#, IERR#, THERMTRIP#
Open Drain I/O Asynchronous PROCHOT#4
CMOS Output Asynchronous PSI#, VID[6:0], BSEL[2:0]
CMOS Input Synchronous
to TCK TCK, TDI, TMS, TRST#
Open Drain Output Synchronous
to TCK TDO
FSB Clock Clock BCLK[1:0]
Power/Other COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA,
THERMDC, VCC, VCCA, VCCP, VCC_SENSE, VSS, VSS_SENSE
Signals Associated Strobe
REQ[4:0]#,
A[16:3]# ADSTB[0]#
A[35:17]# ADSTB[1]#
D[15:0]#,
DINV0#
DSTBP0#,
DSTBN0#
D[31:16]#,
DINV1#
DSTBP1#,
DSTBN1#
D[47:32]#,
DINV2#
DSTBP2#,
DSTBN2#
D[63:48]#,
DINV3#
DSTBP3#,
DSTBN3#
Datasheet 25
Electrical Specifications
3.8 CMOS Signals
CMOS input signals are shown in Ta b l e 4 . Legacy output FERR#, IERR# and other non-
AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for more than four BCLKs in order
for the processor to recognize them. See Section 3.10 for the DC specifications for the
CMOS signal groups.
3.9 Maximum Ratings
Ta b l e 5 specifies absolute maximum and minimum ratings. If the processor stays within
functional operation limits, functionality and long-term reliability can be expected.
Caution: At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long term reliability can be
expected. At conditions exceeding absolute maximum and minimum ratings, neither
functionality nor long term reliability can be expected.
Caution: Precautions should always be taken to avoid high-static voltages or electric fields.
NOTES:
1. For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
2. Storage temperature is applicable to storage conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias.
Storage within these limits does not affect the long term reliability of the device. For
functional operation, please refer to the processor case temperature specifications.
3. This rating applies to the processor and does not include any tray or packaging.
4. Failure to adhere to this specification can affect the long-term reliability of the processor.
Table 5. Processor Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes1
TSTORAGE Processor storage
temperature -40 85 °C 2, 3, 4
VCC
Any processor supply voltage
with respect to VSS
-0.3 1.55 V
VinAGTL+
AGTL+ buffer DC input
voltage with respect to VSS
-0.1 1.55 V
VinAsynch_CMOS
CMOS buffer DC input
voltage with respect to VSS
-0.1 1.55 V
Electrical Specifications
26 Datasheet
3.10 Processor DC Specifications
The processor DC specifications in this section are defined at the processor
core (pads) unless noted otherwise. See Ta b l e 4 for the pin signal definitions and
signal pin assignments.
Tab l e 7 through Ta b l e 1 0 list the DC specifications for the processor and are valid only
while meeting specifications for junction temperature, clock frequency, and input
voltages. The Highest Frequency Mode (HFM) and Super Low Frequency Mode
(SuperLFM) refer to the highest and lowest core operating frequencies supported on
the processor. Active mode load line specifications apply in all states except in the Deep
Sleep and Deeper Sleep states. VCC,BOOT is the default voltage driven by the voltage
regulator at power up in order to set the VID values. Unless specified otherwise, all
specifications for the processor are at Tjunction = 100 °C. Care should be taken to read
all notes associated with each parameter.
Datasheet 27
Electrical Specifications
NOTES:
1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
in such a way that two processors at the same frequency may have different settings within the VID range.
Note that this differs from the VID employed by the processor during a power management event (Intel
Thermal Monitor 2, or Extended Halt State).
2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3. Specified at 105 °C Tj.
4. Specified at the nominal VCC.
5. 800-MHz FSB supported
6. Instantaneous current ICC_CORE_INST of 55 A has to be sustained for short time (tINST) of 10 µs. Average
current is less than maximum specified ICCDES. VR OCP threshold should be high enough to support current
levels described herein.
7. Measured at the bulk capacitors on the motherboard.
8. Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
9. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low.
10. This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high.
1-MB L2 cache.
Table 6. DC Voltage and Current Specifications for the T3x00 Celeron Processors
Symbol Parameter Min Typ Max Unit Notes
VCC VCC of the Processor Core 0.8 1.25 V 1, 2
VCC,BOOT Default VCC Voltage for Initial Power Up 1.20 V 2, 8
VCCP AGTL+ Termination Voltage 1.00 1.05 1.10 V
VCCA PLL Supply Voltage 1.425 1.5 1.575 V
ICCDES
ICC for processors
Recommended Design Targets: 47 A 5
ICC
ICC for processors A
Processor
Number Frequency Die Variant
T3000 1.8 GHz 1 MB 47 A 3, 4
T3100 1.9 GHz 1 MB 47 A 3, 4
IAH,
ISGNT
ICC Auto-Halt & Stop-Grant 25.4 A 3, 4
ISLP ICC Sleep 24.7 A 3, 4
IDSLP ICC Deep Sleep 22.9 A 3, 4
dICC/DT
VCC Power Supply Current Slew Rate at
CPU Package Pin 600 A/µs 6, 7
ICCA ICC for VCCA Supply 130 mA
ICCP
ICC for VCCP Supply before VCC Stable
ICC for VCCP Supply after VCC Stable
4.5
2.5
A
A
9
10
Electrical Specifications
28 Datasheet
NOTES:
1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
in such a way that two processors at the same frequency may have different settings within the VID range.
Note that this differs from the VID employed by the processor during a power management event (Intel
Thermal Monitor 2, or Extended Halt State).
2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3. Specified at 100 °C Tj.
4. Specified at the nominal VCC.
5. 667-MHz FSB supported
6. Instantaneous current ICC_CORE_INST of 55 A has to be sustained for short time (tINST) of 10 µs. Average
current is less than maximum specified ICCDES. VR OCP threshold should be high enough to support current
levels described herein.
7. Measured at the bulk capacitors on the motherboard.
8. Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
9. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low.
10. This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high.
11. 512-KB L2 cache.
Table 7. DC Voltage and Current Specifications for the T1x00 Celeron Mobile
Processors
Symbol Parameter Min Typ Max Unit Notes
VCC VCC of the Processor Core 0.95 1.15 1.30 V 1, 2
VCC,BOOT Default VCC Voltage for Initial Power Up 1.20 V 2, 8
VCCP AGTL+ Termination Voltage 1.00 1.05 1.10 V
VCCA PLL Supply Voltage 1.425 1.5 1.575 V
ICCDES
ICC for processors
Recommended Design Targets: 36 A 5
ICC
ICC for processors A
Processor
Number Frequency Die Variant
T1600 1.66 GHz 1 MB 41 A 3, 4
T1700 1.83 GHz 1 MB 41 A 3, 4
IAH,
ISGNT
ICC Auto-Halt & Stop-Grant 21 A 3, 4
ISLP ICC Sleep 20.5 A 3, 4
IDSLP ICC Deep Sleep 18.6 A 3, 4
dICC/DT
VCC Power Supply Current Slew Rate at
CPU Package Pin 600 A/µs 6, 7
ICCA ICC for VCCA Supply 130 mA
ICCP
ICC for VCCP Supply before VCC Stable
ICC for VCCP Supply after VCC Stable
4.5
2.5
A
A
9
10
Datasheet 29
Electrical Specifications
Table 8 lists the DC specifications for the processor and are valid only while meeting
specifications for junction temperature, clock frequency, and input voltages. The
Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest
and lowest core operating frequencies supported on the Genuine Intel Processor. Unless
specified otherwise, all specifications for the processor are at Tjunction =100 ºC. Care
should be taken to read all notes associated with each parameter.
NOTES:
1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during
manufacturing such that two processors at the same frequency may have different settings within the VID
range. Note that this differs from the VID employed by the processor during a power management event
(ex: Extended Halt State).
2. The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a
100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3. Specified at 100°C Tj.
4. Specified at nominal VCC.
Table 8. Voltage and Current Specifications for the Ultra Low Voltage Dual-Core 1M
Cache Intel Celeron SFF Genuine Intel Processor
Symbol Parameter Min Typ Max Unit Notes
VCC VCC of the Processor Core 0.8 1.1 V 1, 2
VCC,BOOT Default VCC Voltage for Initial Power Up — 1.20 — V 2, 8
VCCP AGTL+ Termination Voltage 1.00 1.05 1.10 V
VCCA PLL Supply Voltage 1.425 1.5 1.575 V
ICCDES ICC for Processors Recommended Design Target ——18A 5
ICC
ICC for processors A
Processor
Number Frequency Die Variant
SU2300 1.2GHz 1MB 17.6 A 3, 4
IAH,
ISGNT
ICC Auto-Halt & Stop-Grant ——
6.3 A3, 4
ISLP ICC Sleep ——
5.9
A3, 4
IDSLP ICC Deep Sleep ——5.0A 3, 4
IDPRSLP ICC Deeper Sleep ——3.2A 3, 4
dICC/DT
VCC Power Supply Current Slew Rate at
Processor Package Pin — — 600 A/µs 7
ICCA ICC for VCCA Supply — — 130 mA
ICCP
ICC for VCCP Supply before VCC Stable
ICC for VCCPSupply after VCC Stable ——
4.5
2.5
A
A
8
9
Electrical Specifications
30 Datasheet
5. 800-MHz FSB supported
6. Measured at the bulk capacitors on the motherboard.
7. Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
8. This is a power-up peak current specification, which is applicable when VCCP is high and VCC core is low.
9. This is a steady-state Icc current specification, which is applicable when both VCCP and VCC core are high.
10. SU2300 processor operates at same core frequency in HFM and LFM.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the
falling edge of BCLK1.
3. For Vin between 0 V and VIH.
4. Cpad includes die capacitance only. No package parasitics are included.
5. ΔVCROSS is defined as the total variation of all crossing voltages as defined in Note 2.
6. Measurement taken from differential waveform.
7. Measurement taken from single-ended waveform.
8. Only applies to the differential rising edge (Clock rising and Clock# falling).
Table 9. FSB Differential BCLK Specifications
Symbol Parameter Min Typ Max Unit Notes1
VCROSS Crossing Voltage 0.3 0.55 V 2, 7, 8
ΔVCROSS Range of Crossing Points 140 mV 2, 7, 5
VSWING Differential Output Swing 300 mV 6
ILI Input Leakage Current -5 +5 µA 3
Cpad Pad Capacitance 0.95 1.2 1.45 pF 4
Datasheet 31
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that is interpreted as a
logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that is interpreted as a
logical high value.
4. VIH and VOH may experience excursions above VCCP
. However, input signal drivers must
comply with the signal quality specifications.
5. This is the pull-down driver resistance. Measured at 0.31*VCCP
. RON (min) = 0.4*RTT
, RON
(typ) = 0.455*RTT
, RON (max) = 0.51*RTT
. RTT typical value of 55 Ω is used for RON typ/
min/max calculations.
6. GTLREF should be generated from VCCP with a 1%-tolerance resistor divider. The VCCP
referred to in these specifications is the instantaneous VCCP
.
7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver.
Measured at 0.31*VCCP
. RTT is connected to VCCP on die.
8. Specified with on die RTT and RON turned off. Vin between 0 and VCCP
.
9. Cpad includes die capacitance only. No package parasitics are included.
10. This is the external resistor on the comp pins.
11. On die termination resistance measured at 0.33*VCCP
.
Table 10. AGTL+ Signal Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes1
VCCP I/O Voltage 1.00 1.05 1.10 V
GTLREF Reference Voltage 2/3 VCCP V6
RCOMP Compensation Resistor 27.23 27.5 27.78 Ω10
RODT Termination Resistor 55 Ω11
VIH Input High Voltage GTLREF+0.10 VCCP VCCP+0.10 V 3,6
VIL Input Low Voltage -0.10 0 GTLREF-0.10 V 2,4
VOH Output High Voltage VCCP-0.10 VCCP VCCP 6
RTT Termination Resistance 50 55 61 Ω 7
RON Buffer On Resistance 22 25 28 Ω5
ILI Input Leakage Current ±100 µA 8
Cpad Pad Capacitance 1.6 2.1 2.55 pF 9
Electrical Specifications
32 Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The VCCP referred to in these specifications refers to instantaneous VCCP
.
3. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are
included.
4. Measured at 0.1*VCCP
.
5. Measured at 0.9*VCCP
.
6. For Vin between 0 V and VCCP
. Measured when the driver is tristated.
7. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package
parasitics are included.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Measured at 0.2 V.
3. VOH is determined by value of the external pull-up resistor to VCCP
.
4. For Vin between 0 V and VOH.
5. Cpad includes die capacitance only. No package parasitics are included.
§
Table 11. CMOS Signal Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes1
VCCP I/O Voltage 1.00 1.05 1.10 V
VIH Input High Voltage 0.7*VCCP VCCP VCCP+0.1 V 2
VIL
Input Low Voltage
CMOS -0.10 0.00 0.3*VCCP V2
VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2
VOL Output Low Voltage -0.10 0 0.1*VCCP V2
IOH Output High Current 1.5 4.1 mA 5
IOL Output Low Current 1.5 4.1 mA 4
ILI Input Leakage Current ±100 µA 6
Cpad1 Pad Capacitance 1.6 2.1 2.55 pF 7
Cpad2 Pad Capacitance for
CMOS Input 0.95 1.2 1.45 3
Table 12. Open Drain Signal Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes1
VOH Output High Voltage VCCP-5% VCCP VCCP+5% V 3
VOL Output Low Voltage 0 0.20 V
IOL Output Low Current 16 50 mA 2
ILO Output Leakage Current ±200 µA 4
Cpad Pad Capacitance 1.9 2.2 2.45 pF 5
Datasheet 33
Package Mechanical Specifications and Pin Information
4 Package Mechanical
Specifications and Pin
Information
4.1 Package Mechanical Specifications
The processor is available in a 1-MB, 478-pin Micro-FCPGA package. The package
mechanical dimensions, keep-out zones, processor mass specifications, and package
loading specifications are shown in Figure 3 through Figure 6.
The SFF processor (ULV DC) is available 956-ball Micro-FCBGA packages. The package
mechanical dimensions are shown in Figure 7.
The maximum outgoing co-planarity is 0.2 mm (8 mils) for SFF Package
The mechanical package pressure specifications are in a direction normal to the surface
of the processor. This requirement is to protect the processor die from fracture risk due
to uneven die pressure distribution under tilt, stack-up tolerances and other similar
conditions. These specifications assume that a mechanical attach is designed
specifically to load one type of processor.
Moreover, the processor package substrate should not be used as a mechanical
reference or load-bearing surface for the thermal or mechanical solution. Please refer
to the Santa Rosa Platform Mechanical Design Guide for more details.
Note: For M-step based processors refer to the 2-MB package drawings.
Package Mechanical Specifications and Pin Information
34 Datasheet
Figure 3. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)
h
Top View
Front View
Detail A
Bottom View
Side View
P
! "#$%$
&'%(
)
*
*
*
+,- ,./0
1--1.0.2
1/
*
1
1
1
1
*
)1.
!
34! 5
6
1
1
ø
0.356 CA
MB
ø
0.254 C
M
Datasheet 35
Package Mechanical Specifications and Pin Information
Figure 4. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)
Top View
Bottom View
Side View
ø
0.406
ø
0.305±0.25
CA
MB
ø
0.254 C
M
!
!
"# $ %&
' (( $ %&
'
Package Mechanical Specifications and Pin Information
36 Datasheet
Figure 5. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)
Top View
Front View
Detail A
Bottom View
Side View
P
! "#$%$
&'%(
)
*
*
+,- ,./0
1--1.0.2
1/
*
1
1
1
1
*
)1.
!
34! 5
6
1
1
ø
0.356 CA
MB
ø
0.254 C
M
Datasheet 37
Package Mechanical Specifications and Pin Information
Figure 6. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)
Top View
Bottom View
Side View
ø
0.406
ø
0.305±0.25
CA
MB
ø
0.254
C
M
!
!
!
!
"# $ %&
' (( $ %&
'
Package Mechanical Specifications and Pin Information
38 Datasheet
Figure 7. SFF (ULV DC) Die Micro-FCBGA Processor Package Drawing
TOP VIEW
FRONT VIEW
SIDE VIEW
BOTTOM VIEW
DETAIL B
DETAIL A
! "#$%&%!
'()* +,-!&./00
/!
1
2
2
1
345 544
446
4 47
1
1
2
2
ø0.14 A
A
B
LC
ø0.04
ø0.46±0.04
(Metal Diameter)
ø0.39±0.02
(Solder Resist Opening)
L
1 68 5 56565 5 5645 5 5
5 43 5 59 665+9 3 56 459 815+ 1 656
86 5 5 56565
:
2
1
4
6
+
8 ;
3
:
83
+;
6
4
2:
1
Datasheet 39
Package Mechanical Specifications and Pin Information
4.2 Processor Pinout and Pin List
Ta b l e 1 3 shows the top view pinout of the Intel Celeron Dual-Core processor. The pin
list, arranged in two different formats, is shown in the following pages.
Table 13. The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 1 of 2)
1 234 5 678910111213
AVSS SMI# VSS FERR# A20M# VCC VSS VCC VCC VSS VCC VCC A
BRSVD INIT# LINT1 DPSLP# VSS VCC VSS VCC VCC VSS VCC VSS B
CRESET# VSS RSVD IGNNE
#VSS LINT0 THERM
TRIP# VSS VCC VCC VSS VCC VCC C
DVSS RSVD RSVD VSS STPCLK
#
PWRGO
OD SLP# VSS VCC VCC VSS VCC VSS D
EDBSY# BNR# VSS HITM# DPRSTP
#VSS VCC VSS VCC VCC VSS VCC VCC E
FBR0# VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS F
GVSS TRDY# RS[2]# VSS BPRI# HIT# G
HADS# REQ[1]
#VSS LOCK# DEFER# VSS H
JA[9]# VSS REQ[3]
#A[3]# VSS VCCP J
KVSS REQ[2]
#
REQ[0]
#VSS A[6]# VCCP K
LREQ[4]# A[13]# VSS A[5]# A[4]# VSS L
MADSTB[0
]# VSS A[7]# RSVD VSS VCCP M
NVSS A[8]# A[10]# VSS RSVD VCCP N
PA[15]# A[12]# VSS A[14]# A[11]# VSS P
RA[16]# VSS A[19]# A[24]# VSS VCCP R
TVSS RSVD A[26]# VSS A[25]# VCCP T
UA[23]# A[30]# VSS A[21]# A[18]# VSS U
VADSTB[1
]# VSS RSVD A[31]# VSS VCCP V
WVSS A[27]# A[32]# VSS A[28]# A[20]# W
YCOMP[3] A[17]# VSS A[29]# A[22]# VSS Y
AA COMP[2] VSS A[35]# A[33]# VSS TDI VCC VSS VCC VCC VSS VCC VCC AA
AB VSS A[34]# TDO VSS TMS TRST# VCC VSS VCC VCC VSS VCC VSS AB
AC PREQ# PRDY# VSS BPM[3]
#TCK VSS VCC VSS VCC VCC VSS VCC VCC AC
AD BPM[2]# VSS BPM[1]
#
BPM[0]
#VSS VID[0] VCC VSS VCC VCC VSS VCC VSS AD
AE VSS VID[6] VID[4] VSS VID[2] PSI# VSS
SENSE VSS VCC VCC VSS VCC VCC AE
AF TEST5 VSS VID[5] VID[3] VID[1] VSS VCC
SENSE VSS VCC VCC VSS VCC VSS AF
1 234 5 678910111213
Package Mechanical Specifications and Pin Information
40 Datasheet
Table 14. The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 2 of 2)
14 15 16 17 18 19 20 21 22 23 24 25 26
AVSS VCC VSS VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THRMDA VSS TEST6 A
BVCC VCC VSS VCC VCC VSS VCC VSS BSEL[0] BSEL[1] VSS THRMDC VCCA B
CVSS VCC VSS VCC VCC VSS DBR# BSEL[2] VSS TEST1 TEST3 VSS VCCA C
DVCC VCC VSS VCC VCC VSS IERR# PROCHO
T# RSVD VSS DPWR# TEST2 VSS D
EVSS VCC VSS VCC VCC VSS VCC VSS D[0]# D[7]# VSS D[6]# D[2]# E
FVCC VCC VSS VCC VCC VSS VCC DRDY# VSS D[4]# D[1]# VSS D[13]# F
GVCCP D[3]# VSS D[9]# D[5]# VSS G
HVSS D[12]# D[15]# VSS DINV[0]# DSTBP[
0]# H
JVCCP VSS D[11]# D[10]# VSS DSTBN[
0]# J
KVCCP D[14]# VSS D[8]# D[17]# VSS K
LVSS D[22]# D[20]# VSS D[29]# DSTBN[
1]# L
MVCCP VSS D[23]# D[21]# VSS DSTBP[
1]# M
NVCCP D[16]# VSS DINV[1]# D[31]# VSS N
PVSS D[26]# D[25]# VSS D[24]# D[18]# P
RVCCP VSS D[19]# D[28]# VSS COMP[0
]R
TVCCP D[37]# VSS D[27]# D[30]# VSS T
UVSS DINV[2]# D[39]# VSS D[38]# COMP[1
]U
VVCCP VSS D[36]# D[34]# VSS D[35]# V
WVCCP D[41]# VSS D[43]# D[44]# VSS W
YVSS D[32]# D[42]# VSS D[40]# DSTBN[
2]# Y
AA VSS VCC VSS VCC VCC VSS VCC D[50]# VSS D[45]# D[46]# VSS DSTBP[
2]#
A
A
AB VCC VCC VSS VCC VCC VSS VCC D[52]# D[51]# VSS D[33]# D[47]# VSS A
B
AC VSS VCC VSS VCC VCC VSS DINV[3
]# VSS D[60]# D[63]# VSS D[57]# D[53]# AC
A
DVCC VCC VSS VCC VCC VSS D[54]# D[59]# VSS D[61]# D[49]# VSS GTLREF A
D
AE VSS VCC VSS VCC VCC VSS VCC D[58]# D[55]# VSS D[48]# DSTBN[3]
#VSS AE
AF VCC VCC VSS VCC VCC VSS VCC VSS D[62]# D[56]# DSTBP[3]
#VSS TEST4 AF
14 15 16 17 18 19 20 21 22 23 24 25 26
Datasheet 41
Package Mechanical Specifications and Pin Information
Table 15. SFF Processor Top View Upper Left Side
BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC
1VSS VSS TDO A[35]# A[17]# A[31]# A[30]# A[19]# COMP[
2] A[16]#
2VSS BPM[3]
#PREQ# A[22]# A[34]# A[32]# A[21]# A[23]# COMP[
3] A[11]#
3VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4VSS VID[5] VID[6] TCK A[20]# A[28]# A[27]# A[18]# A[26]# A[24]# A[12]#
5VID[4] BPM[2]
#TMS A[33]# A[29]# ADSTB
[1]#
RSVD0
4A[25]# RSVD0
3A[14]# A[10]#
6VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
7VID[1] BPM[1]
#TDI VSS VCCP VCCP VCCP VCCP VCCP VCCP VCCP
8VID[0] VID[3] BPM[0]
#TRST# VSS VSS VSS VSS VSS VSS VSS
9VSS VSS VSS VSS VCCP VCCP VCCP VCCP VCCP VCCP VCCP
10 PSI# VID[2] TEST5 PRDY# VSS VCCP VSS VCCP VSS VCCP VSS
11 VSS VSS VSS VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
12 VCCS
ENSE VSS VSS VSS VSS VCCP VSS VCCP VSS VCCP VSS
13 VSSSE
NSE VSS VSS VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
14 VCC VCC VCC VCC VCC VCC VCC VCCP VCCP VCCP VCCP
15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
16 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
17 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
18 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
20 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
21 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
22 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Package Mechanical Specifications and Pin Information
42 Datasheet
Table 16. SFF Processor Top View Upper Right Side
AB AA Y W V U T R P N M L K J H G F E D C B A
1A[7]# A[5]# REQ[2]
#
REQ[0]
#LOCK# TRDY# DBSY# VSS VSS
2A[15]# RSVD0
2
RSVD0
1A[9]# A[3]# BR0# RS[0]# HIT# HITM# VSS
3VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4A[8]# ADSTB
[0]# A[4]# A[6]# REQ[3]
#ADS# RS[2]# RS[1]# RSVD0
6FERR# VSS
5A[13]# REQ[4]
#VSS REQ[1]
#
DEFER
#BPRI# BNR# RESET
#SMI# LINT1 VSS
6VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
7VCCP VCCP VCCP VCCP VCCP VCCP DBR# DPRST
P#
PWRG
OOD A20M# VSS
8VSS VSS VSS VSS VSS VSS VSS RSVD0
7
STPCL
K# INIT# DPSLP
#
9VCCP VCCP VCCP VCCP VCCP VCCP RSVD0
5VSS VSS LINT0 VSS
10 VCCP VSS VCCP VSS VCCP VSS VCCP VSS IGNNE
#SLP#
THER
MTRIP
#
11 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VSS VSS
12 VCCP VSS VCCP VSS VCCP VSS VCCP VCCP VCCP VCCP VCCP
13 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
14 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
16 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
17 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
18 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
20 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
21 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
22 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
Datasheet 43
Package Mechanical Specifications and Pin Information
Table 17. SFF Processor Top View Lower Left Side
BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC
23 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
24 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
25 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
26 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
27 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
28 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
29 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
30 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
31 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
32 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
33 VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC
34 THRM
DC
THRM
DA VSS VSS VCC VSS VSS VSS VSS VSS VSS
35 D[58]# D[62]# VSS VSS VSS VCCP VCCP VCCP VCCP VCCP VCCP
36 VSS VSS D[56]# VSS VSS VCCP VSS VCCP VSS VCCP VSS
37 DINV[3
]# D[54]# VSS VSS VSS VCCP VCCP VCCP VCCP VCCP VCCP
38 VSS D[55]# DSTBP
[3]# D[48]# VSS VCCP VSS VCCP VSS VCCP VSS
39 D[59]# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
40 VSS D[61]# DSTBN
[3]# D[50]# D[57]# D[45]# D[42]# D[43]# D[34]# D[35]# D[26]#
41 VSS D[60]# D[52]# D[51]# D[53]# D[46]# D[47]# DINV[2
]# D[37]# TEST4 D[27]#
42 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
43 VSS GTLRE
FD[63]# D[33]# D[41]# DSTBP
[2]# D[36]# D[44]# COMP[
0] TEST6
44 VSS VSS D[49]# D[32]# D[40]# DSTBN
[2]# D[39]# D[38]# COMP[
1]
Package Mechanical Specifications and Pin Information
44 Datasheet
Table 18. SFF Processor Top View Lower Right Side
AB AA Y W V U T R P N M L K J H G F E D C B A
23 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
24 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
25 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
26 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
27 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
28 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
29 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
30 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
31 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
32 VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCPVCCP
33 VCC VCC VCC VCC VCC VCC VCC VCC VCCP VCCP VCCP
34 VSS VSS VSS VSS VSS VSS VSS VSS VCCP VCCA VCCA
35 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP BCLK[
1]
BCLK[
0]
36 VCCP VSS VCCP VSS VCCP VSS VCCP VCCP VCCP VSS VSS
37 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VSS TEST1 BSEL[1
]
BSEL[0
]
38 VCCP VSS VCCP VSS VCCP VSS VCCP VSS DRDY# PROC
HOT#
BSEL[2
]
39 VSS VSS VSS VSS VSS VSS VSS D[6]# VSS VSS VSS
40 D[25]# D[29]# D[17]# D[11]# DINV[0
]# D[12]# DSTBN
[0]# D[4]# D[0]# TEST2 IERR#
41 D[24]# D[21]# D[23]# D[20]# D[10]# D[8]# DSTBP
[0]# D[13]# D[7]# DPWR
#VSS
42 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
43 D[28]# DSTBP
[1]#
DSTBN
[1]#
DINV[1
]# D[22]# D[15]# D[3]# D[1]# D[2]# TEST3
44 D[19]# D[30]# D[18]# D[31]# D[16]# D[14]# D[9]# D[5]# VSS VSS
Datasheet 45
Package Mechanical Specifications and Pin Information
Table 19. Pin Listing by Pin Name
(Sheet 1 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
A[3]# J4 Source Synch Input/
Output
A[4]# L5 Source Synch Input/
Output
A[5]# L4 Source Synch Input/
Output
A[6]# K5 Source Synch Input/
Output
A[7]# M3 Source Synch Input/
Output
A[8]# N2 Source Synch Input/
Output
A[9]# J1 Source Synch Input/
Output
A[10]# N3 Source Synch Input/
Output
A[11]# P5 Source Synch Input/
Output
A[12]# P2 Source Synch Input/
Output
A[13]# L2 Source Synch Input/
Output
A[14]# P4 Source Synch Input/
Output
A[15]# P1 Source Synch Input/
Output
A[16]# R1 Source Synch Input/
Output
A[17]# Y2 Source Synch Input/
Output
A[18]# U5 Source Synch Input/
Output
A[19]# R3 Source Synch Input/
Output
A[20]# W6 Source Synch Input/
Output
A[21]# U4 Source Synch Input/
Output
A[22]# Y5 Source Synch Input/
Output
A[23]# U1 Source Synch Input/
Output
A[24]# R4 Source Synch Input/
Output
A[25]# T5 Source Synch Input/
Output
A[26]# T3 Source Synch Input/
Output
A[27]# W2 Source Synch Input/
Output
A[28]# W5 Source Synch Input/
Output
A[29]# Y4 Source Synch Input/
Output
A[30]# U2 Source Synch Input/
Output
A[31]# V4 Source Synch Input/
Output
A[32]# W3 Source Synch Input/
Output
A[33]# AA4 Source Synch Input/
Output
A[34]# AB2 Source Synch Input/
Output
A[35]# AA3 Source Synch Input/
Output
A20M# A6 CMOS Input
ADS# H1 Common Clock Input/
Output
ADSTB[0]# M1 Source Synch Input/
Output
ADSTB[1]# V1 Source Synch Input/
Output
BCLK[0] A22 Bus Clock Input
BCLK[1] A21 Bus Clock Input
BNR# E2 Common Clock Input/
Output
BPM[0]# AD4 Common Clock Input/
Output
BPM[1]# AD3 Common Clock Output
BPM[2]# AD1 Common Clock Output
BPM[3]# AC4 Common Clock Input/
Output
BPRI# G5 Common Clock Input
Table 19. Pin Listing by Pin Name
(Sheet 2 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
Package Mechanical Specifications and Pin Information
46 Datasheet
BR0# F1 Common Clock Input/
Output
BSEL[0] B22 CMOS Output
BSEL[1] B23 CMOS Output
BSEL[2] C21 CMOS Output
COMP[0] R26 Power/Other Input/
Output
COMP[1] U26 Power/Other Input/
Output
COMP[2] AA1 Power/Other Input/
Output
COMP[3] Y1 Power/Other Input/
Output
D[0]# E22 Source Synch Input/
Output
D[1]# F24 Source Synch Input/
Output
D[2]# E26 Source Synch Input/
Output
D[3]# G22 Source Synch Input/
Output
D[4]# F23 Source Synch Input/
Output
D[5]# G25 Source Synch Input/
Output
D[6]# E25 Source Synch Input/
Output
D[7]# E23 Source Synch Input/
Output
D[8]# K24 Source Synch Input/
Output
D[9]# G24 Source Synch Input/
Output
D[10]# J24 Source Synch Input/
Output
D[11]# J23 Source Synch Input/
Output
D[12]# H22 Source Synch Input/
Output
D[13]# F26 Source Synch Input/
Output
D[14]# K22 Source Synch Input/
Output
Table 19. Pin Listing by Pin Name
(Sheet 3 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
D[15]# H23 Source Synch Input/
Output
D[16]# N22 Source Synch Input/
Output
D[17]# K25 Source Synch Input/
Output
D[18]# P26 Source Synch Input/
Output
D[19]# R23 Source Synch Input/
Output
D[20]# L23 Source Synch Input/
Output
D[21]# M24 Source Synch Input/
Output
D[22]# L22 Source Synch Input/
Output
D[23]# M23 Source Synch Input/
Output
D[24]# P25 Source Synch Input/
Output
D[25]# P23 Source Synch Input/
Output
D[26]# P22 Source Synch Input/
Output
D[27]# T24 Source Synch Input/
Output
D[28]# R24 Source Synch Input/
Output
D[29]# L25 Source Synch Input/
Output
D[30]# T25 Source Synch Input/
Output
D[31]# N25 Source Synch Input/
Output
D[32]# Y22 Source Synch Input/
Output
D[33]# AB24 Source Synch Input/
Output
D[34]# V24 Source Synch Input/
Output
D[35]# V26 Source Synch Input/
Output
D[36]# V23 Source Synch Input/
Output
Table 19. Pin Listing by Pin Name
(Sheet 4 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
Datasheet 47
Package Mechanical Specifications and Pin Information
D[37]# T22 Source Synch Input/
Output
D[38]# U25 Source Synch Input/
Output
D[39]# U23 Source Synch Input/
Output
D[40]# Y25 Source Synch Input/
Output
D[41]# W22 Source Synch Input/
Output
D[42]# Y23 Source Synch Input/
Output
D[43]# W24 Source Synch Input/
Output
D[44]# W25 Source Synch Input/
Output
D[45]# AA23 Source Synch Input/
Output
D[46]# AA24 Source Synch Input/
Output
D[47]# AB25 Source Synch Input/
Output
D[48]# AE24 Source Synch Input/
Output
D[49]# AD24 Source Synch Input/
Output
D[50]# AA21 Source Synch Input/
Output
D[51]# AB22 Source Synch Input/
Output
D[52]# AB21 Source Synch Input/
Output
D[53]# AC26 Source Synch Input/
Output
D[54]# AD20 Source Synch Input/
Output
D[55]# AE22 Source Synch Input/
Output
D[56]# AF23 Source Synch Input/
Output
D[57]# AC25 Source Synch Input/
Output
D[58]# AE21 Source Synch Input/
Output
Table 19. Pin Listing by Pin Name
(Sheet 5 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
D[59]# AD21 Source Synch Input/
Output
D[60]# AC22 Source Synch Input/
Output
D[61]# AD23 Source Synch Input/
Output
D[62]# AF22 Source Synch Input/
Output
D[63]# AC23 Source Synch Input/
Output
DBR# C20 CMOS Output
DBSY# E1 Common Clock Input/
Output
DEFER# H5 Common Clock Input
DINV[0]# H25 Source Synch Input/
Output
DINV[1]# N24 Source Synch Input/
Output
DINV[2]# U22 Source Synch Input/
Output
DINV[3]# AC20 Source Synch Input/
Output
DPRSTP# E5 CMOS Input
DPSLP# B5 CMOS Input
DPWR# D24 Common Clock Input/
Output
DRDY# F21 Common Clock Input/
Output
DSTBN[0]# J26 Source Synch Input/
Output
DSTBN[1]# L26 Source Synch Input/
Output
DSTBN[2]# Y26 Source Synch Input/
Output
DSTBN[3]# AE25 Source Synch Input/
Output
DSTBP[0]# H26 Source Synch Input/
Output
DSTBP[1]# M26 Source Synch Input/
Output
DSTBP[2]# AA26 Source Synch Input/
Output
Table 19. Pin Listing by Pin Name
(Sheet 6 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
Package Mechanical Specifications and Pin Information
48 Datasheet
DSTBP[3]# AF24 Source Synch Input/
Output
FERR# A5 Open Drain Output
GTLREF AD26 Power/Other Input
HIT# G6 Common Clock Input/
Output
HITM# E4 Common Clock Input/
Output
IERR# D20 Open Drain Output
IGNNE# C4 CMOS Input
INIT# B3 CMOS Input
LINT0 C6 CMOS Input
LINT1 B4 CMOS Input
LOCK# H4 Common Clock Input/
Output
PRDY# AC2 Common Clock Output
PREQ# AC1 Common Clock Input
PROCHOT# D21 Open Drain Input/
Output
PSI# AE6 CMOS Output
PWRGOOD D6 CMOS Input
REQ[0]# K3 Source Synch Input/
Output
REQ[1]# H2 Source Synch Input/
Output
REQ[2]# K2 Source Synch Input/
Output
REQ[3]# J3 Source Synch Input/
Output
REQ[4]# L1 Source Synch Input/
Output
RESET# C1 Common Clock Input
RS[0]# F3 Common Clock Input
RS[1]# F4 Common Clock Input
RS[2]# G3 Common Clock Input
RSVD B2 Reserved
RSVD C3 Reserved
RSVD D2 Reserved
RSVD D3 Reserved
RSVD D22 Reserved
Table 19. Pin Listing by Pin Name
(Sheet 7 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
RSVD F6 Reserved
RSVD M4 Reserved
RSVD N5 Reserved
RSVD T2 Reserved
RSVD V3 Reserved
SLP# D7 CMOS Input
SMI# A3 CMOS Input
STPCLK# D5 CMOS Input
TCK AC5 CMOS Input
TDI AA6 CMOS Input
TDO AB3 Open Drain Output
TEST1 C23 Test
TEST2 D25 Test
TEST3 C24 Test
TEST4 AF26 Test
TEST5 AF1 Test
TEST6 A26 Test
THERMTRIP
#C7 Open Drain Output
THRMDA A24 Power/Other
THRMDC B25 Power/Other
TMS AB5 CMOS Input
TRDY# G2 Common Clock Input
TRST# AB6 CMOS Input
VCC A7 Power/Other
VCC A9 Power/Other
VCC A10 Power/Other
VCC A12 Power/Other
VCC A13 Power/Other
VCC A15 Power/Other
VCC A17 Power/Other
VCC A18 Power/Other
VCC A20 Power/Other
VCC AA7 Power/Other
VCC AA9 Power/Other
VCC AA10 Power/Other
VCC AA12 Power/Other
Table 19. Pin Listing by Pin Name
(Sheet 8 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
Datasheet 49
Package Mechanical Specifications and Pin Information
VCC AA13 Power/Other
VCC AA15 Power/Other
VCC AA17 Power/Other
VCC AA18 Power/Other
VCC AA20 Power/Other
VCC AB7 Power/Other
VCC AB9 Power/Other
VCC AB10 Power/Other
VCC AB12 Power/Other
VCC AB14 Power/Other
VCC AB15 Power/Other
VCC AB17 Power/Other
VCC AB18 Power/Other
VCC AB20 Power/Other
VCC AC7 Power/Other
VCC AC9 Power/Other
VCC AC10 Power/Other
VCC AC12 Power/Other
VCC AC13 Power/Other
VCC AC15 Power/Other
VCC AC17 Power/Other
VCC AC18 Power/Other
VCC AD7 Power/Other
VCC AD9 Power/Other
VCC AD10 Power/Other
VCC AD12 Power/Other
VCC AD14 Power/Other
VCC AD15 Power/Other
VCC AD17 Power/Other
VCC AD18 Power/Other
VCC AE9 Power/Other
VCC AE10 Power/Other
VCC AE12 Power/Other
VCC AE13 Power/Other
VCC AE15 Power/Other
VCC AE17 Power/Other
Table 19. Pin Listing by Pin Name
(Sheet 9 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
VCC AE18 Power/Other
VCC AE20 Power/Other
VCC AF9 Power/Other
VCC AF10 Power/Other
VCC AF12 Power/Other
VCC AF14 Power/Other
VCC AF15 Power/Other
VCC AF17 Power/Other
VCC AF18 Power/Other
VCC AF20 Power/Other
VCC B7 Power/Other
VCC B9 Power/Other
VCC B10 Power/Other
VCC B12 Power/Other
VCC B14 Power/Other
VCC B15 Power/Other
VCC B17 Power/Other
VCC B18 Power/Other
VCC B20 Power/Other
VCC C9 Power/Other
VCC C10 Power/Other
VCC C12 Power/Other
VCC C13 Power/Other
VCC C15 Power/Other
VCC C17 Power/Other
VCC C18 Power/Other
VCC D9 Power/Other
VCC D10 Power/Other
VCC D12 Power/Other
VCC D14 Power/Other
VCC D15 Power/Other
VCC D17 Power/Other
VCC D18 Power/Other
VCC E7 Power/Other
VCC E9 Power/Other
VCC E10 Power/Other
Table 19. Pin Listing by Pin Name
(Sheet 10 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
Package Mechanical Specifications and Pin Information
50 Datasheet
VCC E12 Power/Other
VCC E13 Power/Other
VCC E15 Power/Other
VCC E17 Power/Other
VCC E18 Power/Other
VCC E20 Power/Other
VCC F7 Power/Other
VCC F9 Power/Other
VCC F10 Power/Other
VCC F12 Power/Other
VCC F14 Power/Other
VCC F15 Power/Other
VCC F17 Power/Other
VCC F18 Power/Other
VCC F20 Power/Other
VCCA B26 Power/Other
VCCA C26 Power/Other
VCCP G21 Power/Other
VCCP J6 Power/Other
VCCP J21 Power/Other
VCCP K6 Power/Other
VCCP K21 Power/Other
VCCP M6 Power/Other
VCCP M21 Power/Other
VCCP N6 Power/Other
VCCP N21 Power/Other
VCCP R6 Power/Other
VCCP R21 Power/Other
VCCP T6 Power/Other
VCCP T21 Power/Other
VCCP V6 Power/Other
VCCP V21 Power/Other
VCCP W21 Power/Other
VCCSENSE AF7 Power/Other
VID[0] AD6 CMOS Output
VID[1] AF5 CMOS Output
Table 19. Pin Listing by Pin Name
(Sheet 11 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
VID[2] AE5 CMOS Output
VID[3] AF4 CMOS Output
VID[4] AE3 CMOS Output
VID[5] AF3 CMOS Output
VID[6] AE2 CMOS Output
VSS A2 Power/Other
VSS A4 Power/Other
VSS A8 Power/Other
VSS A11 Power/Other
VSS A14 Power/Other
VSS A16 Power/Other
VSS A19 Power/Other
VSS A23 Power/Other
VSS A25 Power/Other
VSS AA2 Power/Other
VSS AA5 Power/Other
VSS AA8 Power/other
VSS AA11 Power/Other
VSS AA14 Power/Other
VSS AA16 Power/Other
VSS AA19 Power/Other
VSS AA22 Power/Other
VSS AA25 Power/Other
VSS AB1 Power/Other
VSS AB4 Power/Other
VSS AB8 Power/Other
VSS AB11 Power/Other
VSS AB13 Power/Other
VSS AB16 Power/Other
VSS AB19 Power/Other
VSS AB23 Power/Other
VSS AB26 Power/Other
VSS AC3 Power/Other
VSS AC6 Power/Other
VSS AC8 Power/Other
VSS AC11 Power/Other
Table 19. Pin Listing by Pin Name
(Sheet 12 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
Datasheet 51
Package Mechanical Specifications and Pin Information
VSS AC14 Power/Other
VSS AC16 Power/Other
VSS AC19 Power/Other
VSS AC21 Power/Other
VSS AC24 Power/Other
VSS AD2 Power/Other
VSS AD5 Power/Other
VSS AD8 Power/Other
VSS AD11 Power/Other
VSS AD13 Power/Other
VSS AD16 Power/Other
VSS AD19 Power/Other
VSS AD22 Power/Other
VSS AD25 Power/Other
VSS AE1 Power/Other
VSS AE4 Power/Other
VSS AE8 Power/Other
VSS AE11 Power/Other
VSS AE14 Power/Other
VSS AE16 Power/Other
VSS AE19 Power/Other
VSS AE23 Power/Other
VSS AE26 Power/Other
VSS AF2 Power/Other
VSS AF6 Power/Other
VSS AF8 Power/Other
VSS AF11 Power/Other
VSS AF13 Power/Other
VSS AF16 Power/Other
VSS AF19 Power/Other
VSS AF21 Power/Other
VSS AF25 Power/Other
VSS B6 Power/Other
VSS B8 Power/Other
VSS B11 Power/Other
VSS B13 Power/Other
Table 19. Pin Listing by Pin Name
(Sheet 13 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
VSS B16 Power/Other
VSS B19 Power/Other
VSS B21 Power/Other
VSS B24 Power/Other
VSS C2 Power/Other
VSS C5 Power/Other
VSS C8 Power/Other
VSS C11 Power/Other
VSS C14 Power/Other
VSS C16 Power/Other
VSS C19 Power/Other
VSS C22 Power/Other
VSS C25 Power/Other
VSS D1 Power/Other
VSS D4 Power/Other
VSS D8 Power/Other
VSS D11 Power/Other
VSS D13 Power/Other
VSS D16 Power/Other
VSS D19 Power/Other
VSS D23 Power/Other
VSS D26 Power/Other
VSS E3 Power/Other
VSS E6 Power/Other
VSS E8 Power/Other
VSS E11 Power/Other
VSS E14 Power/Other
VSS E16 Power/Other
VSS E19 Power/Other
VSS E21 Power/Other
VSS E24 Power/Other
VSS F2 Power/Other
VSS F5 Power/Other
VSS F8 Power/Other
VSS F11 Power/Other
VSS F13 Power/Other
Table 19. Pin Listing by Pin Name
(Sheet 14 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
Package Mechanical Specifications and Pin Information
52 Datasheet
VSS F16 Power/Other
VSS F19 Power/Other
VSS F22 Power/Other
VSS F25 Power/Other
VSS G1 Power/Other
VSS G4 Power/Other
VSS G23 Power/Other
VSS G26 Power/Other
VSS H3 Power/Other
VSS H6 Power/Other
VSS H21 Power/Other
VSS H24 Power/Other
VSS J2 Power/Other
VSS J5 Power/Other
VSS J22 Power/Other
VSS J25 Power/Other
VSS K1 Power/Other
VSS K4 Power/Other
VSS K23 Power/Other
VSS K26 Power/Other
VSS L3 Power/Other
VSS L6 Power/Other
VSS L21 Power/Other
VSS L24 Power/Other
VSS M2 Power/Other
VSS M5 Power/Other
VSS M22 Power/Other
VSS M25 Power/Other
VSS N1 Power/Other
VSS N4 Power/Other
VSS N23 Power/Other
VSS N26 Power/Other
VSS P3 Power/Other
VSS P6 Power/Other
VSS P21 Power/Other
VSS P24 Power/Other
Table 19. Pin Listing by Pin Name
(Sheet 15 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
VSS R2 Power/Other
VSS R5 Power/Other
VSS R22 Power/Other
VSS R25 Power/Other
VSS T1 Power/Other
VSS T4 Power/Other
VSS T23 Power/Other
VSS T26 Power/Other
VSS U3 Power/Other
VSS U6 Power/Other
VSS U21 Power/Other
VSS U24 Power/Other
VSS V2 Power/Other
VSS V5 Power/Other
VSS V22 Power/Other
VSS V25 Power/Other
VSS W1 Power/Other
VSS W4 Power/Other
VSS W23 Power/Other
VSS W26 Power/Other
VSS Y3 Power/Other
VSS Y6 Power/Other
VSS Y21 Power/Other
VSS Y24 Power/Other
VSSSENSE AE7 Power/Other Output
Table 20. Pin Listing by Pin Number
(Sheet 1 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
VSS A2 Power/Other
SMI# A3 CMOS Input
VSS A4 Power/Other
FERR# A5 Open Drain Output
A20M# A6 CMOS Input
VCC A7 Power/Other
Table 19. Pin Listing by Pin Name
(Sheet 16 of 16)
Pin Name Pin
Number
Signal Buffer
Type Direction
Datasheet 53
Package Mechanical Specifications and Pin Information
VSS A8 Power/Other
VCC A9 Power/Other
VCC A10 Power/Other
VSS A11 Power/Other
VCC A12 Power/Other
VCC A13 Power/Other
VSS A14 Power/Other
VCC A15 Power/Other
VSS A16 Power/Other
VCC A17 Power/Other
VCC A18 Power/Other
VSS A19 Power/Other
VCC A20 Power/Other
BCLK[1] A21 Bus Clock Input
BCLK[0] A22 Bus Clock Input
VSS A23 Power/Other
THRMDA A24 Power/Other
VSS A25 Power/Other
TEST6 A26 Test
COMP[2] AA1 Power/Other Input/
Output
VSS AA2 Power/Other
A[35]# AA3 Source Synch Input/
Output
A[33]# AA4 Source Synch Input/
Output
VSS AA5 Power/Other
TDI AA6 CMOS Input
VCC AA7 Power/Other
VSS AA8 Power/other
VCC AA9 Power/Other
VCC AA10 Power/Other
VSS AA11 Power/Other
VCC AA12 Power/Other
VCC AA13 Power/Other
VSS AA14 Power/Other
VCC AA15 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 2 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
VSS AA16 Power/Other
VCC AA17 Power/Other
VCC AA18 Power/Other
VSS AA19 Power/Other
VCC AA20 Power/Other
D[50]# AA21 Source Synch Input/
Output
VSS AA22 Power/Other
D[45]# AA23 Source Synch Input/
Output
D[46]# AA24 Source Synch Input/
Output
VSS AA25 Power/Other
DSTBP[2]# AA26 Source Synch Input/
Output
VSS AB1 Power/Other
A[34]# AB2 Source Synch Input/
Output
TDO AB3 Open Drain Output
VSS AB4 Power/Other
TMS AB5 CMOS Input
TRST# AB6 CMOS Input
VCC AB7 Power/Other
VSS AB8 Power/Other
VCC AB9 Power/Other
VCC AB10 Power/Other
VSS AB11 Power/Other
VCC AB12 Power/Other
VSS AB13 Power/Other
VCC AB14 Power/Other
VCC AB15 Power/Other
VSS AB16 Power/Other
VCC AB17 Power/Other
VCC AB18 Power/Other
VSS AB19 Power/Other
VCC AB20 Power/Other
D[52]# AB21 Source Synch Input/
Output
Table 20. Pin Listing by Pin Number
(Sheet 3 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
Package Mechanical Specifications and Pin Information
54 Datasheet
D[51]# AB22 Source Synch Input/
Output
VSS AB23 Power/Other
D[33]# AB24 Source Synch Input/
Output
D[47]# AB25 Source Synch Input/
Output
VSS AB26 Power/Other
PREQ# AC1 Common
Clock Input
PRDY# AC2 Common
Clock Output
VSS AC3 Power/Other
BPM[3]# AC4 Common
Clock
Input/
Output
TCK AC5 CMOS Input
VSS AC6 Power/Other
VCC AC7 Power/Other
VSS AC8 Power/Other
VCC AC9 Power/Other
VCC AC10 Power/Other
VSS AC11 Power/Other
VCC AC12 Power/Other
VCC AC13 Power/Other
VSS AC14 Power/Other
VCC AC15 Power/Other
VSS AC16 Power/Other
VCC AC17 Power/Other
VCC AC18 Power/Other
VSS AC19 Power/Other
DINV[3]# AC20 Source Synch Input/
Output
VSS AC21 Power/Other
D[60]# AC22 Source Synch Input/
Output
D[63]# AC23 Source Synch Input/
Output
VSS AC24 Power/Other
D[57]# AC25 Source Synch Input/
Output
Table 20. Pin Listing by Pin Number
(Sheet 4 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
D[53]# AC26 Source Synch Input/
Output
BPM[2]# AD1 Common
Clock Output
VSS AD2 Power/Other
BPM[1]# AD3 Common
Clock Output
BPM[0]# AD4 Common
Clock
Input/
Output
VSS AD5 Power/Other
VID[0] AD6 CMOS Output
VCC AD7 Power/Other
VSS AD8 Power/Other
VCC AD9 Power/Other
VCC AD10 Power/Other
VSS AD11 Power/Other
VCC AD12 Power/Other
VSS AD13 Power/Other
VCC AD14 Power/Other
VCC AD15 Power/Other
VSS AD16 Power/Other
VCC AD17 Power/Other
VCC AD18 Power/Other
VSS AD19 Power/Other
D[54]# AD20 Source Synch Input/
Output
D[59]# AD21 Source Synch Input/
Output
VSS AD22 Power/Other
D[61]# AD23 Source Synch Input/
Output
D[49]# AD24 Source Synch Input/
Output
VSS AD25 Power/Other
GTLREF AD26 Power/Other Input
VSS AE1 Power/Other
VID[6] AE2 CMOS Output
VID[4] AE3 CMOS Output
VSS AE4 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 5 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
Datasheet 55
Package Mechanical Specifications and Pin Information
VID[2] AE5 CMOS Output
PSI# AE6 CMOS Output
VSSSENSE AE7 Power/Other Output
VSS AE8 Power/Other
VCC AE9 Power/Other
VCC AE10 Power/Other
VSS AE11 Power/Other
VCC AE12 Power/Other
VCC AE13 Power/Other
VSS AE14 Power/Other
VCC AE15 Power/Other
VSS AE16 Power/Other
VCC AE17 Power/Other
VCC AE18 Power/Other
VSS AE19 Power/Other
VCC AE20 Power/Other
D[58]# AE21 Source Synch Input/
Output
D[55]# AE22 Source Synch Input/
Output
VSS AE23 Power/Other
D[48]# AE24 Source Synch Input/
Output
DSTBN[3]# AE25 Source Synch Input/
Output
VSS AE26 Power/Other
TEST5 AF1 Test
VSS AF2 Power/Other
VID[5] AF3 CMOS Output
VID[3] AF4 CMOS Output
VID[1] AF5 CMOS Output
VSS AF6 Power/Other
VCCSENSE AF7 Power/Other
VSS AF8 Power/Other
VCC AF9 Power/Other
VCC AF10 Power/Other
VSS AF11 Power/Other
VCC AF12 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 6 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
VSS AF13 Power/Other
VCC AF14 Power/Other
VCC AF15 Power/Other
VSS AF16 Power/Other
VCC AF17 Power/Other
VCC AF18 Power/Other
VSS AF19 Power/Other
VCC AF20 Power/Other
VSS AF21 Power/Other
D[62]# AF22 Source Synch Input/
Output
D[56]# AF23 Source Synch Input/
Output
DSTBP[3]# AF24 Source Synch Input/
Output
VSS AF25 Power/Other
TEST4 AF26 Test
RSVD B2 Reserved
INIT# B3 CMOS Input
LINT1 B4 CMOS Input
DPSLP# B5 CMOS Input
VSS B6 Power/Other
VCC B7 Power/Other
VSS B8 Power/Other
VCC B9 Power/Other
VCC B10 Power/Other
VSS B11 Power/Other
VCC B12 Power/Other
VSS B13 Power/Other
VCC B14 Power/Other
VCC B15 Power/Other
VSS B16 Power/Other
VCC B17 Power/Other
VCC B18 Power/Other
VSS B19 Power/Other
VCC B20 Power/Other
VSS B21 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 7 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
Package Mechanical Specifications and Pin Information
56 Datasheet
BSEL[0] B22 CMOS Output
BSEL[1] B23 CMOS Output
VSS B24 Power/Other
THRMDC B25 Power/Other
VCCA B26 Power/Other
RESET# C1 Common
Clock Input
VSS C2 Power/Other
RSVD C3 Reserved
IGNNE# C4 CMOS Input
VSS C5 Power/Other
LINT0 C6 CMOS Input
THERMTRIP
#C7 Open Drain Output
VSS C8 Power/Other
VCC C9 Power/Other
VCC C10 Power/Other
VSS C11 Power/Other
VCC C12 Power/Other
VCC C13 Power/Other
VSS C14 Power/Other
VCC C15 Power/Other
VSS C16 Power/Other
VCC C17 Power/Other
VCC C18 Power/Other
VSS C19 Power/Other
DBR# C20 CMOS Output
BSEL[2] C21 CMOS Output
VSS C22 Power/Other
TEST1 C23 Test
TEST3 C24 Test
VSS C25 Power/Other
VCCA C26 Power/Other
VSS D1 Power/Other
RSVD D2 Reserved
RSVD D3 Reserved
VSS D4 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 8 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
STPCLK# D5 CMOS Input
PWRGOOD D6 CMOS Input
SLP# D7 CMOS Input
VSS D8 Power/Other
VCC D9 Power/Other
VCC D10 Power/Other
VSS D11 Power/Other
VCC D12 Power/Other
VSS D13 Power/Other
VCC D14 Power/Other
VCC D15 Power/Other
VSS D16 Power/Other
VCC D17 Power/Other
VCC D18 Power/Other
VSS D19 Power/Other
IERR# D20 Open Drain Output
PROCHOT# D21 Open Drain Input/
Output
RSVD D22 Reserved
VSS D23 Power/Other
DPWR# D24 Common
Clock
Input/
Output
TEST2 D25 Test
VSS D26 Power/Other
DBSY# E1 Common
Clock
Input/
Output
BNR# E2 Common
Clock
Input/
Output
VSS E3 Power/Other
HITM# E4 Common
Clock
Input/
Output
DPRSTP# E5 CMOS Input
VSS E6 Power/Other
VCC E7 Power/Other
VSS E8 Power/Other
VCC E9 Power/Other
VCC E10 Power/Other
VSS E11 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 9 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
Datasheet 57
Package Mechanical Specifications and Pin Information
VCC E12 Power/Other
VCC E13 Power/Other
VSS E14 Power/Other
VCC E15 Power/Other
VSS E16 Power/Other
VCC E17 Power/Other
VCC E18 Power/Other
VSS E19 Power/Other
VCC E20 Power/Other
VSS E21 Power/Other
D[0]# E22 Source Synch Input/
Output
D[7]# E23 Source Synch Input/
Output
VSS E24 Power/Other
D[6]# E25 Source Synch Input/
Output
D[2]# E26 Source Synch Input/
Output
BR0# F1 Common
Clock
Input/
Output
VSS F2 Power/Other
RS[0]# F3 Common
Clock Input
RS[1]# F4 Common
Clock Input
VSS F5 Power/Other
RSVD F6 Reserved
VCC F7 Power/Other
VSS F8 Power/Other
VCC F9 Power/Other
VCC F10 Power/Other
VSS F11 Power/Other
VCC F12 Power/Other
VSS F13 Power/Other
VCC F14 Power/Other
VCC F15 Power/Other
VSS F16 Power/Other
VCC F17 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 10 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
VCC F18 Power/Other
VSS F19 Power/Other
VCC F20 Power/Other
DRDY# F21 Common
Clock
Input/
Output
VSS F22 Power/Other
D[4]# F23 Source Synch Input/
Output
D[1]# F24 Source Synch Input/
Output
VSS F25 Power/Other
D[13]# F26 Source Synch Input/
Output
VSS G1 Power/Other
TRDY# G2 Common
Clock Input
RS[2]# G3 Common
Clock Input
VSS G4 Power/Other
BPRI# G5 Common
Clock Input
HIT# G6 Common
Clock
Input/
Output
VCCP G21 Power/Other
D[3]# G22 Source Synch Input/
Output
VSS G23 Power/Other
D[9]# G24 Source Synch Input/
Output
D[5]# G25 Source Synch Input/
Output
VSS G26 Power/Other
ADS# H1 Common
Clock
Input/
Output
REQ[1]# H2 Source Synch Input/
Output
VSS H3 Power/Other
LOCK# H4 Common
Clock
Input/
Output
DEFER# H5 Common
Clock Input
Table 20. Pin Listing by Pin Number
(Sheet 11 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
Package Mechanical Specifications and Pin Information
58 Datasheet
VSS H6 Power/Other
VSS H21 Power/Other
D[12]# H22 Source Synch Input/
Output
D[15]# H23 Source Synch Input/
Output
VSS H24 Power/Other
DINV[0]# H25 Source Synch Input/
Output
DSTBP[0]# H26 Source Synch Input/
Output
A[9]# J1 Source Synch Input/
Output
VSS J2 Power/Other
REQ[3]# J3 Source Synch Input/
Output
A[3]# J4 Source Synch Input/
Output
VSS J5 Power/Other
VCCP J6 Power/Other
VCCP J21 Power/Other
VSS J22 Power/Other
D[11]# J23 Source Synch Input/
Output
D[10]# J24 Source Synch Input/
Output
VSS J25 Power/Other
DSTBN[0]# J26 Source Synch Input/
Output
VSS K1 Power/Other
REQ[2]# K2 Source Synch Input/
Output
REQ[0]# K3 Source Synch Input/
Output
VSS K4 Power/Other
A[6]# K5 Source Synch Input/
Output
VCCP K6 Power/Other
VCCP K21 Power/Other
D[14]# K22 Source Synch Input/
Output
Table 20. Pin Listing by Pin Number
(Sheet 12 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
VSS K23 Power/Other
D[8]# K24 Source Synch Input/
Output
D[17]# K25 Source Synch Input/
Output
VSS K26 Power/Other
REQ[4]# L1 Source Synch Input/
Output
A[13]# L2 Source Synch Input/
Output
VSS L3 Power/Other
A[5]# L4 Source Synch Input/
Output
A[4]# L5 Source Synch Input/
Output
VSS L6 Power/Other
VSS L21 Power/Other
D[22]# L22 Source Synch Input/
Output
D[20]# L23 Source Synch Input/
Output
VSS L24 Power/Other
D[29]# L25 Source Synch Input/
Output
DSTBN[1]# L26 Source Synch Input/
Output
ADSTB[0]# M1 Source Synch Input/
Output
VSS M2 Power/Other
A[7]# M3 Source Synch Input/
Output
RSVD M4 Reserved
VSS M5 Power/Other
VCCP M6 Power/Other
VCCP M21 Power/Other
VSS M22 Power/Other
D[23]# M23 Source Synch Input/
Output
D[21]# M24 Source Synch Input/
Output
VSS M25 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 13 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
Datasheet 59
Package Mechanical Specifications and Pin Information
DSTBP[1]# M26 Source Synch Input/
Output
VSS N1 Power/Other
A[8]# N2 Source Synch Input/
Output
A[10]# N3 Source Synch Input/
Output
VSS N4 Power/Other
RSVD N5 Reserved
VCCP N6 Power/Other
VCCP N21 Power/Other
D[16]# N22 Source Synch Input/
Output
VSS N23 Power/Other
DINV[1]# N24 Source Synch Input/
Output
D[31]# N25 Source Synch Input/
Output
VSS N26 Power/Other
A[15]# P1 Source Synch Input/
Output
A[12]# P2 Source Synch Input/
Output
VSS P3 Power/Other
A[14]# P4 Source Synch Input/
Output
A[11]# P5 Source Synch Input/
Output
VSS P6 Power/Other
VSS P21 Power/Other
D[26]# P22 Source Synch Input/
Output
D[25]# P23 Source Synch Input/
Output
VSS P24 Power/Other
D[24]# P25 Source Synch Input/
Output
D[18]# P26 Source Synch Input/
Output
A[16]# R1 Source Synch Input/
Output
Table 20. Pin Listing by Pin Number
(Sheet 14 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
VSS R2 Power/Other
A[19]# R3 Source Synch Input/
Output
A[24]# R4 Source Synch Input/
Output
VSS R5 Power/Other
VCCP R6 Power/Other
VCCP R21 Power/Other
VSS R22 Power/Other
D[19]# R23 Source Synch Input/
Output
D[28]# R24 Source Synch Input/
Output
VSS R25 Power/Other
COMP[0] R26 Power/Other Input/
Output
VSS T1 Power/Other
RSVD T2 Reserved
A[26]# T3 Source Synch Input/
Output
VSS T4 Power/Other
A[25]# T5 Source Synch Input/
Output
VCCP T6 Power/Other
VCCP T21 Power/Other
D[37]# T22 Source Synch Input/
Output
VSS T23 Power/Other
D[27]# T24 Source Synch Input/
Output
D[30]# T25 Source Synch Input/
Output
VSS T26 Power/Other
A[23]# U1 Source Synch Input/
Output
A[30]# U2 Source Synch Input/
Output
VSS U3 Power/Other
A[21]# U4 Source Synch Input/
Output
Table 20. Pin Listing by Pin Number
(Sheet 15 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
Package Mechanical Specifications and Pin Information
60 Datasheet
A[18]# U5 Source Synch Input/
Output
VSS U6 Power/Other
VSS U21 Power/Other
DINV[2]# U22 Source Synch Input/
Output
D[39]# U23 Source Synch Input/
Output
VSS U24 Power/Other
D[38]# U25 Source Synch Input/
Output
COMP[1] U26 Power/Other Input/
Output
ADSTB[1]# V1 Source Synch Input/
Output
VSS V2 Power/Other
RSVD V3 Reserved
A[31]# V4 Source Synch Input/
Output
VSS V5 Power/Other
VCCP V6 Power/Other
VCCP V21 Power/Other
VSS V22 Power/Other
D[36]# V23 Source Synch Input/
Output
D[34]# V24 Source Synch Input/
Output
VSS V25 Power/Other
D[35]# V26 Source Synch Input/
Output
VSS W1 Power/Other
A[27]# W2 Source Synch Input/
Output
A[32]# W3 Source Synch Input/
Output
VSS W4 Power/Other
A[28]# W5 Source Synch Input/
Output
A[20]# W6 Source Synch Input/
Output
VCCP W21 Power/Other
Table 20. Pin Listing by Pin Number
(Sheet 16 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
D[41]# W22 Source Synch Input/
Output
VSS W23 Power/Other
D[43]# W24 Source Synch Input/
Output
D[44]# W25 Source Synch Input/
Output
VSS W26 Power/Other
COMP[3] Y1 Power/Other Input/
Output
A[17]# Y2 Source Synch Input/
Output
VSS Y3 Power/Other
A[29]# Y4 Source Synch Input/
Output
A[22]# Y5 Source Synch Input/
Output
VSS Y6 Power/Other
VSS Y21 Power/Other
D[32]# Y22 Source Synch Input/
Output
D[42]# Y23 Source Synch Input/
Output
VSS Y24 Power/Other
D[40]# Y25 Source Synch Input/
Output
DSTBN[2]# Y26 Source Synch Input/
Output
Table 20. Pin Listing by Pin Number
(Sheet 17 of 17)
Pin Name Pin
Number
Signal
Buffer Type Direction
Datasheet 61
Package Mechanical Specifications and Pin Information
Table 21. SFF Listing by Ball Name
Signal Name Ball
Number
A[3]# P2
A[4]# V4
A[5]# W1
A[6]# T4
A[7]# AA1
A[8]# AB4
A[9]# T2
A[10]# AC5
A[11]# AD2
A[12]# AD4
A[13]# AA5
A[14]# AE5
A[15]# AB2
A[16]# AC1
A[17]# AN1
A[18]# AK4
A[19]# AG1
A[20]# AT4
A[21]# AK2
A[22]# AT2
A[23]# AH2
A[24]# AF4
A[25]# AJ5
A[26]# AH4
A[27]# AM4
A[28]# AP4
A[29]# AR5
A[30]# AJ1
A[31]# AL1
A[32]# AM2
A[33]# AU5
A[34]# AP2
A[35]# AR1
A20M# C7
ADS# M4
ADSTB[0]# Y4
ADSTB[1]# AN5
BCLK[0] A35
BCLK[1] C35
BNR# J5
BPM[0]# AY8
BPM[1]# BA7
BPM[2]# BA5
BPM[3]# AY2
BPRI# L5
BR0# M2
BSEL[0] A37
BSEL[1] C37
BSEL[2] B38
COMP[0] AE43
COMP[1] AD44
COMP[2] AE1
COMP[3] AF2
D[0]# F40
D[1]# G43
D[2]# E43
D[3]# J43
D[4]# H40
D[5]# H44
D[6]# G39
D[7]# E41
D[8]# L41
D[9]# K44
D[10]# N41
D[11]# T40
D[12]# M40
D[13]# G41
D[14]# M44
D[15]# L43
D[16]# P44
D[17]# V40
D[18]# V44
D[19]# AB44
Signal Name Ball
Number
Package Mechanical Specifications and Pin Information
62 Datasheet
D[20]# R41
D[21]# W41
D[22]# N43
D[23]# U41
D[24]# AA41
D[25]# AB40
D[26]# AD40
D[27]# AC41
D[28]# AA43
D[29]# Y40
D[30]# Y44
D[31]# T44
D[32]# AP44
D[33]# AR43
D[34]# AH40
D[35]# AF40
D[36]# AJ43
D[37]# AG41
D[38]# AF44
D[39]# AH44
D[40]# AM44
D[41]# AN43
D[42]# AM40
D[43]# AK40
D[44]# AG43
D[45]# AP40
D[46]# AN41
D[47]# AL41
D[48]# AV38
D[49]# AT44
D[50]# AV40
D[51]# AU41
D[52]# AW41
D[53]# AR41
D[54]# BA37
D[55]# BB38
D[56]# AY36
D[57]# AT40
Signal Name Ball
Number
D[58]# BC35
D[59]# BC39
D[60]# BA41
D[61]# BB40
D[62]# BA35
D[63]# AU43
DBR# J7
DBSY# J1
DEFER# N5
DINV[0]# P40
DINV[1]# R43
DINV[2]# AJ41
DINV[3]# BC37
DPRSTP# G7
DPSLP# B8
DPWR# C41
DRDY# F38
DSTBN[0]# K40
DSTBN[1]# U43
DSTBN[2]# AK44
DSTBN[3]# AY40
DSTBP[0]# J41
DSTBP[1]# W43
DSTBP[2]# AL43
DSTBP[3]# AY38
FERR# D4
GTLREF AW43
HIT# H2
HITM# F2
IERR# B40
IGNNE# F10
INIT# D8
LINT0 C9
LINT1 C5
LOCK# N1
PRDY# AV10
PREQ# AV2
PROCHOT# D38
Signal Name Ball
Number
Datasheet 63
Package Mechanical Specifications and Pin Information
PSI# BD10
PWRGOOD E7
REQ[0]# R1
REQ[1]# R5
REQ[2]# U1
REQ[3]# P4
REQ[4]# W5
RESET# G5
RS[0]# K2
RS[1]# H4
RS[2]# K4
RSVD01 V2
RSVD02 Y2
RSVD03 AG5
RSVD04 AL5
RSVD05 J9
RSVD06 F4
RSVD07 H8
SLP# D10
SMI# E5
STPCLK# F8
TCK AV4
TDI AW7
TDO AU1
TEST1 E37
TEST2 D40
TEST3 C43
TEST4 AE41
TEST5 AY10
TEST6 AC43
THERMTRIP# B10
THRMDA BB34
THRMDC BD34
TMS AW5
TRDY# L1
TRST# AV8
VCC AA33
VCC AB16
Signal Name Ball
Number
VCC AB18
VCC AB20
VCC AB22
VCC AB24
VCC AB26
VCC AB28
VCC AB30
VCC AB32
VCC AC33
VCC AD16
VCC AD18
VCC AD20
VCC AD22
VCC AD24
VCC AD26
VCC AD28
VCC AD30
VCC AD32
VCC AE33
VCC AF16
VCC AF18
VCC AF20
VCC AF22
VCC AF24
VCC AF26
VCC AF28
VCC AF30
VCC AF32
VCC AG33
VCC AH16
VCC AH18
VCC AH20
VCC AH22
VCC AH24
VCC AH26
VCC AH28
VCC AH30
VCC AH32
Signal Name Ball
Number
Package Mechanical Specifications and Pin Information
64 Datasheet
VCC AJ33
VCC AK16
VCC AK18
VCC AK20
VCC AK22
VCC AK24
VCC AK26
VCC AK28
VCC AK30
VCC AK32
VCC AL33
VCC AM14
VCC AM16
VCC AM18
VCC AM20
VCC AM22
VCC AM24
VCC AM26
VCC AM28
VCC AM30
VCC AM32
VCC AN33
VCC AP14
VCC AP16
VCC AP18
VCC AP20
VCC AP22
VCC AP24
VCC AP26
VCC AP28
VCC AP30
VCC AP32
VCC AR33
VCC AT14
VCC AT16
VCC AT18
VCC AT20
VCC AT22
Signal Name Ball
Number
VCC AT24
VCC AT26
VCC AT28
VCC AT30
VCC AT32
VCC AT34
VCC AU33
VCC AV14
VCC AV16
VCC AV18
VCC AV20
VCC AV22
VCC AV24
VCC AV26
VCC AV28
VCC AV30
VCC AV32
VCC AY14
VCC AY16
VCC AY18
VCC AY20
VCC AY22
VCC AY24
VCC AY26
VCC AY28
VCC AY30
VCC AY32
VCC B16
VCC B18
VCC B20
VCC B22
VCC B24
VCC B26
VCC B28
VCC B30
VCC BB14
VCC BB16
VCC BB18
Signal Name Ball
Number
Datasheet 65
Package Mechanical Specifications and Pin Information
VCC BB20
VCC BB22
VCC BB24
VCC BB26
VCC BB28
VCC BB30
VCC BB32
VCC BD14
VCC BD16
VCC BD18
VCC BD20
VCC BD22
VCC BD24
VCC BD26
VCC BD28
VCC BD30
VCC BD32
VCC D16
VCC D18
VCC D20
VCC D22
VCC D24
VCC D26
VCC D28
VCC D30
VCC F16
VCC F18
VCC F20
VCC F22
VCC F24
VCC F26
VCC F28
VCC F30
VCC F32
VCC G33
VCC H16
VCC H18
VCC H20
Signal Name Ball
Number
VCC H22
VCC H24
VCC H26
VCC H28
VCC H30
VCC H32
VCC J33
VCC K16
VCC K18
VCC K20
VCC K22
VCC K24
VCC K26
VCC K28
VCC K30
VCC K32
VCC L33
VCC M16
VCC M18
VCC M20
VCC M22
VCC M24
VCC M26
VCC M28
VCC M30
VCC M32
VCC N33
VCC P16
VCC P18
VCC P20
VCC P22
VCC P24
VCC P26
VCC P28
VCC P30
VCC P32
VCC R33
VCC T16
Signal Name Ball
Number
Package Mechanical Specifications and Pin Information
66 Datasheet
VCC T18
VCC T20
VCC T22
VCC T24
VCC T26
VCC T28
VCC T30
VCC T32
VCC U33
VCC V16
VCC V18
VCC V20
VCC V22
VCC V24
VCC V26
VCC V28
VCC V30
VCC V32
VCC W33
VCC Y16
VCC Y18
VCC Y20
VCC Y22
VCC Y24
VCC Y26
VCC Y28
VCC Y30
VCC Y32
VCCA B34
VCCA D34
VCCP A13
VCCP A33
VCCP AA7
VCCP AA9
VCCP AA11
VCCP AA13
VCCP AA35
VCCP AA37
Signal Name Ball
Number
VCCP AB10
VCCP AB12
VCCP AB14
VCCP AB36
VCCP AB38
VCCP AC7
VCCP AC9
VCCP AC11
VCCP AC13
VCCP AC35
VCCP AC37
VCCP AD14
VCCP AE7
VCCP AE9
VCCP AE11
VCCP AE13
VCCP AE35
VCCP AE37
VCCP AF10
VCCP AF12
VCCP AF14
VCCP AF36
VCCP AF38
VCCP AG7
VCCP AG9
VCCP AG11
VCCP AG13
VCCP AG35
VCCP AG37
VCCP AH14
VCCP AJ7
VCCP AJ9
VCCP AJ11
VCCP AJ13
VCCP AJ35
VCCP AJ37
VCCP AK10
VCCP AK12
Signal Name Ball
Number
Datasheet 67
Package Mechanical Specifications and Pin Information
VCCP AK14
VCCP AK36
VCCP AK38
VCCP AL7
VCCP AL9
VCCP AL11
VCCP AL13
VCCP AL35
VCCP AL37
VCCP AN7
VCCP AN9
VCCP AN11
VCCP AN13
VCCP AN35
VCCP AN37
VCCP AP10
VCCP AP12
VCCP AP36
VCCP AP38
VCCP AR7
VCCP AR9
VCCP AR11
VCCP AR13
VCCP AU11
VCCP AU13
VCCP B12
VCCP B14
VCCP B32
VCCP C13
VCCP C33
VCCP D12
VCCP D14
VCCP D32
VCCP E11
VCCP E13
VCCP E33
VCCP E35
VCCP F12
Signal Name Ball
Number
VCCP F14
VCCP F34
VCCP F36
VCCP G11
VCCP G13
VCCP G35
VCCP H12
VCCP H14
VCCP H36
VCCP J11
VCCP J13
VCCP J35
VCCP J37
VCCP K10
VCCP K12
VCCP K14
VCCP K36
VCCP K38
VCCP L7
VCCP L9
VCCP L11
VCCP L13
VCCP L35
VCCP L37
VCCP M14
VCCP N7
VCCP N9
VCCP N11
VCCP N13
VCCP N35
VCCP N37
VCCP P10
VCCP P12
VCCP P14
VCCP P36
VCCP P38
VCCP R7
VCCP R9
Signal Name Ball
Number
Package Mechanical Specifications and Pin Information
68 Datasheet
VCCP R11
VCCP R13
VCCP R35
VCCP R37
VCCP T14
VCCP U7
VCCP U9
VCCP U11
VCCP U13
VCCP U35
VCCP U37
VCCP V10
VCCP V12
VCCP V14
VCCP V36
VCCP V38
VCCP W7
VCCP W9
VCCP W11
VCCP W13
VCCP W35
VCCP W37
VCCP Y14
VCCSENSE BD12
VID[0] BD8
VID[1] BC7
VID[2] BB10
VID[3] BB8
VID[4] BC5
VID[5] BB4
VID[6] AY4
VSS A5
VSS A7
VSS A9
VSS A11
VSS A15
VSS A17
VSS A19
Signal Name Ball
Number
VSS A21
VSS A23
VSS A25
VSS A27
VSS A29
VSS A31
VSS A39
VSS A41
VSS AA3
VSS AA15
VSS AA17
VSS AA19
VSS AA21
VSS AA23
VSS AA25
VSS AA27
VSS AA29
VSS AA31
VSS AA39
VSS AB6
VSS AB8
VSS AB34
VSS AB42
VSS AC3
VSS AC15
VSS AC17
VSS AC19
VSS AC21
VSS AC23
VSS AC25
VSS AC27
VSS AC29
VSS AC31
VSS AC39
VSS AD6
VSS AD8
VSS AD10
VSS AD12
Signal Name Ball
Number
Datasheet 69
Package Mechanical Specifications and Pin Information
VSS AD34
VSS AD36
VSS AD38
VSS AD42
VSS AE3
VSS AE15
VSS AE17
VSS AE19
VSS AE21
VSS AE23
VSS AE25
VSS AE27
VSS AE29
VSS AE31
VSS AE39
VSS AF6
VSS AF8
VSS AF34
VSS AF42
VSS AG3
VSS AG15
VSS AG17
VSS AG19
VSS AG21
VSS AG23
VSS AG25
VSS AG27
VSS AG29
VSS AG31
VSS AG39
VSS AH6
VSS AH8
VSS AH10
VSS AH12
VSS AH34
VSS AH36
VSS AH38
VSS AH42
Signal Name Ball
Number
VSS AJ3
VSS AJ15
VSS AJ17
VSS AJ19
VSS AJ21
VSS AJ23
VSS AJ25
VSS AJ27
VSS AJ29
VSS AJ31
VSS AJ39
VSS AK6
VSS AK8
VSS AK34
VSS AK42
VSS AL3
VSS AL15
VSS AL17
VSS AL19
VSS AL21
VSS AL23
VSS AL25
VSS AL27
VSS AL29
VSS AL31
VSS AL39
VSS AM6
VSS AM8
VSS AM10
VSS AM12
VSS AM34
VSS AM36
VSS AM38
VSS AM42
VSS AN3
VSS AN15
VSS AN17
VSS AN19
Signal Name Ball
Number
Package Mechanical Specifications and Pin Information
70 Datasheet
VSS AN21
VSS AN23
VSS AN25
VSS AN27
VSS AN29
VSS AN31
VSS AN39
VSS AP6
VSS AP8
VSS AP34
VSS AP42
VSS AR3
VSS AR15
VSS AR17
VSS AR19
VSS AR21
VSS AR23
VSS AR25
VSS AR27
VSS AR29
VSS AR31
VSS AR35
VSS AR37
VSS AR39
VSS AT6
VSS AT8
VSS AT10
VSS AT12
VSS AT36
VSS AT38
VSS AT42
VSS AU3
VSS AU7
VSS AU9
VSS AU15
VSS AU17
VSS AU19
VSS AU21
Signal Name Ball
Number
VSS AU23
VSS AU25
VSS AU27
VSS AU29
VSS AU31
VSS AU35
VSS AU37
VSS AU39
VSS AV6
VSS AV12
VSS AV34
VSS AV36
VSS AV42
VSS AV44
VSS AW1
VSS AW3
VSS AW9
VSS AW11
VSS AW13
VSS AW15
VSS AW17
VSS AW19
VSS AW21
VSS AW23
VSS AW25
VSS AW27
VSS AW29
VSS AW31
VSS AW33
VSS AW35
VSS AW37
VSS AW39
VSS AY6
VSS AY12
VSS AY34
VSS AY42
VSS AY44
VSS B4
Signal Name Ball
Number
Datasheet 71
Package Mechanical Specifications and Pin Information
VSS B6
VSS B36
VSS B42
VSS BA1
VSS BA3
VSS BA9
VSS BA11
VSS BA13
VSS BA15
VSS BA17
VSS BA19
VSS BA21
VSS BA23
VSS BA25
VSS BA27
VSS BA29
VSS BA31
VSS BA33
VSS BA39
VSS BA43
VSS BB2
VSS BB6
VSS BB12
VSS BB36
VSS BB42
VSS BC3
VSS BC9
VSS BC11
VSS BC15
VSS BC17
VSS BC19
VSS BC21
VSS BC23
VSS BC25
VSS BC27
VSS BC29
VSS BC31
VSS BC33
Signal Name Ball
Number
VSS BC41
VSS BD4
VSS BD6
VSS BD36
VSS BD38
VSS BD40
VSS C3
VSS C11
VSS C15
VSS C17
VSS C19
VSS C21
VSS C23
VSS C25
VSS C27
VSS C29
VSS C31
VSS C39
VSS D2
VSS D6
VSS D36
VSS D42
VSS D44
VSS E1
VSS E3
VSS E9
VSS E15
VSS E17
VSS E19
VSS E21
VSS E23
VSS E25
VSS E27
VSS E29
VSS E31
VSS E39
VSS F6
VSS F42
Signal Name Ball
Number
Package Mechanical Specifications and Pin Information
72 Datasheet
VSS F44
VSS G1
VSS G3
VSS G9
VSS G15
VSS G17
VSS G19
VSS G21
VSS G23
VSS G25
VSS G27
VSS G29
VSS G31
VSS G37
VSS H6
VSS H10
VSS H34
VSS H38
VSS H42
VSS J3
VSS J15
VSS J17
VSS J19
VSS J21
VSS J23
VSS J25
VSS J27
VSS J29
VSS J31
VSS J39
VSS K6
VSS K8
VSS K34
VSS K42
VSS L3
VSS L15
VSS L17
VSS L19
Signal Name Ball
Number
VSS L21
VSS L23
VSS L25
VSS L27
VSS L29
VSS L31
VSS L39
VSS M6
VSS M8
VSS M10
VSS M12
VSS M34
VSS M36
VSS M38
VSS M42
VSS N3
VSS N15
VSS N17
VSS N19
VSS N21
VSS N23
VSS N25
VSS N27
VSS N29
VSS N31
VSS N39
VSS P6
VSS P8
VSS P34
VSS P42
VSS R3
VSS R15
VSS R17
VSS R19
VSS R21
VSS R23
VSS R25
VSS R27
Signal Name Ball
Number
Datasheet 73
Package Mechanical Specifications and Pin Information
VSS R29
VSS R31
VSS R39
VSS T6
VSS T8
VSS T10
VSS T12
VSS T34
VSS T36
VSS T38
VSS T42
VSS U3
VSS U5
VSS U15
VSS U17
VSS U19
VSS U21
VSS U23
VSS U25
VSS U27
VSS U29
VSS U31
VSS U39
VSS V6
VSS V8
VSS V34
VSS V42
VSS W3
VSS W15
VSS W17
VSS W19
VSS W21
VSS W23
VSS W25
VSS W27
VSS W29
VSS W31
VSS W39
Signal Name Ball
Number
VSS Y6
VSS Y8
VSS Y10
VSS Y12
VSS Y34
VSS Y36
VSS Y38
VSS Y42
VSSSENSE BC13
Signal Name Ball
Number
Package Mechanical Specifications and Pin Information
74 Datasheet
Datasheet 75
Package Mechanical Specifications and Pin Information
4.3 Alphabetical Signals Reference
Table 22. Signal Description (Sheet 1 of 7)
Name Type Description
A[35:3]# Input/
Output
A[35:3]# (Address) define a 236-byte physical memory address space. In sub-
phase 1 of the address phase, these pins transmit the address of a transaction. In
sub-phase 2, these pins transmit transaction type information. These signals must
connect the appropriate pins of both agents on the processor FSB. A[35:3]# are
source synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#. Address signals are used as straps which are sampled before
RESET# is deasserted.
A20M# Input
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/
write transaction on the bus. Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS# Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
ADSTB[1:0]# Input/
Output
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
BCLK[1:0] Input
The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB
agents must receive these signals to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing VCROSS.
BNR# Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
BPM[2:1]#
BPM[3,0]#
Output
Input/
Output
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[3:0]#
should connect the appropriate pins of all processor FSB agents.This includes
debug or performance monitoring tools.
BPRI# Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must
connect the appropriate pins of both FSB agents. Observing BPRI# active (as
asserted by the priority agent) causes the other agent to stop issuing new
requests, unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
BR0# Input/
Output
BR0# is used by the processor to request the bus. The arbitration is done between
processor (Symmetric Agent) and (G)MCH (High Priority Agent).
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[35:17]# ADSTB[1]#
Package Mechanical Specifications and Pin Information
76 Datasheet
BSEL[2:0] Output
BSEL[2:0] (Bus Select) are used to select the processor input clock frequency.
Ta b l e 3 defines the possible combinations of the signals and the frequency
associated with each combination. The required frequency is determined by the
processor, chipset and clock synthesizer. All agents must operate at the same
frequency.
COMP[3:0] Analog COMP[3:0] must be terminated on the system board using precision (1%
tolerance) resistors.
D[63:0]# Input/
Output
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the FSB agents, and must connect the appropriate pins on both agents.
The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and are driven four times in a common clock
period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and
DSTBN[3:0]#. Each group of 16 data signals corresponds to a pair of one DSTBP#
and one DSTBN#. The following table shows the grouping of data signals to data
strobes and DINV#.
Furthermore, the DINV# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DINV# signal. When the DINV# signal
is active, the corresponding data group is inverted and therefore sampled active
high.
DBR# Output
DBR# (Data Bus Reset) is used only in processor systems where no debug port is
implemented on the system board. DBR# is used by a debug port interposer so
that an in-target probe can drive system reset. If a debug port is implemented in
the system, DBR# is a no-connect in the system. DBR# is not a processor signal.
DBSY# Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on
the FSB to indicate that the data bus is in use. The data bus is released after
DBSY# is deasserted. This signal must connect the appropriate pins on both FSB
agents.
DEFER# Input
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or Input/Output agent. This signal must connect the
appropriate pins of both FSB agents.
Table 22. Signal Description (Sheet 2 of 7)
Name Type Description
Quad-Pumped Signal Groups
Data
Group
DSTBN#/
DSTBP# DINV#
D[15:0]# 0 0
D[31:16]# 1 1
D[47:32]# 2 2
D[63:48]# 3 3
Datasheet 77
Package Mechanical Specifications and Pin Information
DINV[3:0]# Input/
Output
DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity
of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on
the data bus is inverted. The bus agent inverts the data bus signals if more than
half the bits, within the covered group, would change level in the next cycle.
DPRSTP# Input
DPRSTP# when asserted on the platform causes the processor to transition from
the Deep Sleep State to the Deeper Sleep state. In order to return to the Deep
Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the Intel
82801HBM ICH8M I/O Controller Hub-based chipset.
DPSLP# Input
DPSLP# when asserted on the platform causes the processor to transition from the
Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP#
must be deasserted. DPSLP# is driven by the Intel 82801HBM ICH8M chipset.
DPWR# Input/
Output
DPWR# is a control signal used by the chipset to reduce power on the processor
data bus input buffers. The processor drives this pin during dynamic FSB frequency
switching.
DRDY# Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of both FSB agents.
DSTBN[3:0]# Input/
Output
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]# Input/
Output
Data strobe used to latch in D[63:0]#.
Table 22. Signal Description (Sheet 3 of 7)
Name Type Description
DINV[3:0]# Assignment To Data Bus
Bus Signal Data Bus
Signals
DINV[3]# D[63:48]#
DINV[2]# D[47:32]#
DINV[1]# D[31:16]#
DINV[0]# D[15:0]#
Signals Associated
Strobe
D[15:0]#, DINV[0]# DSTBN[0]#
D[31:16]#, DINV[1]# DSTBN[1]#
D[47:32]#, DINV[2]# DSTBN[2]#
D[63:48]#, DINV[3]# DSTBN[3]#
Signals Associated Strobe
D[15:0]#, DINV[0]# DSTBP[0]#
D[31:16]#, DINV[1]# DSTBP[1]#
D[47:32]#, DINV[2]# DSTBP[2]#
D[63:48]#, DINV[3]# DSTBP[3]#
Package Mechanical Specifications and Pin Information
78 Datasheet
FERR#/PBE# Output
FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal
and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/
PBE# indicates a floating point when the processor detects an unmasked floating-
point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor,
and is included for compatibility with systems using MS-DOS*-type floating-point
error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates
that the processor has a pending break event waiting for service. The assertion of
FERR#/PBE# indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it remains asserted until
STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active also causes
an FERR# break event.
For additional information on the pending break event functionality, including
identification of support of the feature and enable/disable information, refer to
Volumes 3A and 3B of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual and the Intel® Processor Identification and CPUID Instruction application
note.
GTLREF Input
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should
be set at 2/3 VCCP
. GTLREF is used by the AGTL+ receivers to determine if a signal
is a logical 0 or logical 1.
HIT#
HITM#
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Either FSB agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
IERR# Output
IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the
FSB. This transaction may optionally be converted to an external error signal (e.g.,
NMI) by system core logic. The processor keeps IERR# asserted until the assertion
of RESET#, BINIT#, or INIT#.
IGNNE# Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
INIT# Input
INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor then
begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure recognition of this
signal following an Input/Output Write instruction, it must be valid along with the
TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT#
must connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST)
Table 22. Signal Description (Sheet 4 of 7)
Name Type Description
Datasheet 79
Package Mechanical Specifications and Pin Information
LINT[1:0] Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus
agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable
interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR
and NMI are backward compatible with the signals of those names on the Intel®
Pentium® processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# Input/
Output
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of both FSB agents. For a locked sequence of
transactions, LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it
waits until it observes LOCK# deasserted. This enables symmetric agents to retain
ownership of the FSB throughout the bus locked operation and ensure the
atomicity of lock.
PRDY# Output Probe Ready signal used by debug tools to determine processor debug readiness.
PREQ# Input Probe Request signal used by debug tools to request debug operation of the
processor.
PROCHOT# Input/
Output
As an output, PROCHOT# (Processor Hot) goes active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system activates the TCC, if enabled. The TCC remains active
until the system deasserts PROCHOT#.
By default PROCHOT# is configured as an output. The processor must be enabled
via the BIOS for PROCHOT# to be configured as bidirectional.
This signal may require voltage translation on the motherboard.
PSI# Output
Processor Power Status Indicator signal. This signal is asserted when the processor
is in both in the Normal state (HFM to LFM) and in lower power states (Deep Sleep
and Deeper Sleep).
PWRGOOD Input
PWRGOOD (Power Good) is a processor input. The processor requires this signal to
be a clean indication that the clocks and power supplies are stable and within their
specifications. ‘Clean’ implies that the signal remains low (capable of sinking
leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition
monotonically to a high state. PWRGOOD can be driven inactive at any time, but
clocks and power must again be stable before a subsequent rising edge of
PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB
agents. They are asserted by the current bus owner to define the currently active
transaction type. These signals are source synchronous to ADSTB[0]#.
Table 22. Signal Description (Sheet 5 of 7)
Name Type Description
Package Mechanical Specifications and Pin Information
80 Datasheet
RESET# Input
Asserting the RESET# signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK
have reached their proper specifications. On observing active RESET#, both FSB
agents deasserts their outputs within two clocks. All processor straps must be valid
within the specified setup time before RESET# is deasserted. There is a 55-Ω
(nominal) on die pull-up resistor on this signal.
RS[2:0]# Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of both FSB agents.
RSVD
Reserved
/No
Connect
These pins are RESERVED and must be left unconnected on the board. However, it
is recommended that routing channels to these pins on the board be kept open for
possible future use.
SLP# Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state does not recognize snoops or interrupts. The processor
recognizes only assertion of the RESET# signal, deassertion of SLP#, and removal
of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits
Sleep state and returns to Stop-Grant state, restarting its internal clock signals to
the bus and processor core units. If DPSLP# is asserted while in the Sleep state,
the processor exits the Sleep state and transition to the Deep Sleep state.
SMI# Input
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, the processor saves the current
state and enters System Management Mode (SMM). An SMI Acknowledge
transaction is issued and the processor begins program execution from the SMM
handler.
If an SMI# is asserted during the deassertion of RESET#, then the processor
tristates its outputs.
STPCLK# Input
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the FSB and
APIC units. The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor
restarts its internal clock to all units and resumes execution. The assertion of
STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
TCK Input TCK (Test Clock) provides the clock input for the processor Test Bus (also known as
the Test Access Port).
TDI Input TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO Output TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TEST1, TEST2,
TEST3,
TEST4,
TEST5,
TEST6
Input
TEST1 and TEST2 must have a stuffing option of separate pulldown resistors to
VSS. For the purpose of testability, route the TEST3 and TEST5 signals through a
ground-referenced Zo=55 Ω trace that ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
THRMDA Other Thermal Diode Anode.
THRMDC Other Thermal Diode Cathode.
Table 22. Signal Description (Sheet 6 of 7)
Name Type Description
Datasheet 81
Package Mechanical Specifications and Pin Information
§
THERMTRIP# Output
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor stops all execution when the
junction temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRDY# Input
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of both FSB agents.
TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset.
VCC Input Processor core power supply.
VSS Input Processor core ground node.
VCCA Input VCCA provides isolated power for the internal processor core PLL’s.
VCCP Input Processor I/O Power Supply.
VCC_SENSE Output
VCC_SENSE together with VSS_SENSE are voltage feedback signals to Intel® MVP-6
that control the 2.1-mΩ loadline at the processor die. It should be used to sense
voltage near the silicon with little noise.
VID[6:0] Output
VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply
voltages (VCC). Unlike some previous generations of processors, these are CMOS
signals that are driven by the processor. The voltage supply for these pins must be
valid before the VR can supply Vcc to the processor. Conversely, the VR output
must be disabled until the voltage supply for the VID pins becomes valid. The VID
pins are needed to support the processor voltage specification variations. See
Table 2 for definitions of these pins. The VR must supply the voltage that is
requested by the pins, or disable itself.
VSS_SENSE Output
VSS_SENSE together with VCC_SENSE are voltage feedback signals to Intel MVP-6
that control the 2.1-mΩ loadline at the processor die. It should be used to sense
ground near the silicon with little noise.
Table 22. Signal Description (Sheet 7 of 7)
Name Type Description
Package Mechanical Specifications and Pin Information
82 Datasheet
Datasheet 83
Thermal Specifications and Design Considerations
5 Thermal Specifications and
Design Considerations
Maintaining the proper thermal environment is key to reliable, long-term system
operation. A complete thermal solution includes both component and system level
thermal management features. The system/processor thermal solution should be
designed so that the processor remains within the minimum and maximum junction
temperature (Tj) specifications at the corresponding thermal design power (TDP) value
listed in Ta b l e 2 4 through Ta b le 2 6 .
Caution: Operating the processor outside these limits may result in permanent damage to the
processor and potentially other components in the system.
NOTES:
1. The TDP specification should be used to design the processor thermal solution. The TDP is not the
maximum theoretical power the processor can generate.
2. Not 100% tested. These power specifications are determined by characterization of the processor currents
at higher temperatures and extrapolating the values for the temperature indicated.
Table 23. Power Specifications for the 3x00 Celeron Processors
Symbol Processor
Number Core Frequency & Voltage Thermal Design
Power Unit Notes
TDP T1600 1.66 GHz 35 W 1, 4, 5, 6, 9
TDP T1700 1.83 GHz 35 W 1, 4, 5, 6, 9
Symbol Parameter Min Typ Max Unit
PAH,
PSGNT
Auto Halt, Stop Grant Power at HFM VCC 13.9 W 2, 5, 7
PSLP Sleep Power at VCC 13.1 W 2, 5, 7
PDSLP Deep Sleep Power at VCC 5.5 W 2, 5, 8
TJJunction Temperature 0 105 °C3, 4
Table 24. Power Specifications for the Intel Celeron Dual-Core Processor - Standard
Voltage
Symbol Processor
Number Core Frequency & Voltage Thermal Design
Power Unit Notes
TDP T1600 1.66 GHz 35 W 1, 4, 5, 6, 9
TDP T1700 1.83 GHz 35 W 1, 4, 5, 6, 9
Symbol Parameter Min Typ Max Unit
PAH,
PSGNT
Auto Halt, Stop Grant Power at HFM VCC 13.5 W 2, 5, 7
PSLP Sleep Power at VCC 12.9 W 2, 5, 7
PDSLP Deep Sleep Power at VCC 7.7 W 2, 5, 8
TJJunction Temperature 0 100 °C3, 4
Thermal Specifications and Design Considerations
84 Datasheet
3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic
mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for details.
4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.
5. At Tj of 100 oC
6. At Tj of 50 oC
7. At Tj of 35 oC
8. 512-KB L2 cache
Table 25. Power Specifications for the Ultra Low Voltage Dual-Core 1M Cache Intel
Celeron (SFF) Genuine Intel Processor
NOTES:
1. The TDP specification should be used to design the processor thermal solution. The TDP is not the
maximum theoretical power the processor can generate.
2. Not 100% tested. These power specifications are determined by characterization of the processor currents
at higher temperatures and extrapolating the values for the temperature indicated.
3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic
mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.
5. At Tj of 100 oC
6. At Tj of 50 °C
7. At Tj of 35 oC
5.1 Monitoring Die Temperature
The processor incorporates three methods of monitoring die temperature:
•Thermal Diode
• Intel Thermal Monitor
• Digital Thermal Sensor
Symbol Processor
Number Core Frequency Thermal Design
Power Unit Notes
TDP SU2300 1.2 GHz 10 W 1, 4, 5
Symbol Parameter Min Typ Max Unit Notes
PAH,
PSGNT
Auto Halt, Stop Grant Power 2.9 W 2, 6
PSLP Sleep Power 2.9 W 2, 6
PDSLP Deep Sleep Power 1.3 W 2,7
PDPRSLP Deeper Sleep Power 0.6 W 2, 7
TJJunction Temperature 0 100 °C3,4
Datasheet 85
Thermal Specifications and Design Considerations
5.1.1 Thermal Diode
The processor incorporates an on-die PNP transistor whose base emitter junction is
used as a thermal diode, with its collector shorted to ground. The thermal diode can be
read by an off-die analog/digital converter (a thermal sensor) located on the
motherboard or a stand-alone measurement kit. The thermal diode may be used to
monitor the die temperature of the processor for thermal management or
instrumentation purposes but is not a reliable indication that the maximum operating
temperature of the processor has been reached. When using the thermal diode, a
temperature offset value must be read from a processor MSR and applied. See
Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage
recommendation when the PROCHOT# signal is not asserted.
The reading of the external thermal sensor (on the motherboard) connected
to the processor thermal diode signals does not reflect the temperature of the
hottest location on the die. This is due to inaccuracies in the external thermal
sensor, on-die temperature gradients between the location of the thermal diode and the
hottest location on the die, and time based variations in the die temperature
measurement. Time-based variations can occur when the sampling rate of the thermal
diode (by the thermal sensor) is slower than the rate at which the TJ temperature can
change.
Offset between the thermal diode-based temperature reading and the Intel Thermal
Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic
mode activation of the thermal control circuit. This temperature offset must be taken
into account when using the processor thermal diode to implement power management
events. This offset is different than the diode Toffset value programmed into the
processor Model Specific Register (MSR).
Ta b l e 2 6 to Ta b l e 2 9 provide the diode interface and specifications. The diode model
parameters apply to the traditional thermal sensors that use the diode equation to
determine the processor temperature. Transistor model parameters have been added
to support thermal sensors that use the transistor equation method. The Transistor
model may provide more accurate temperature measurements when the diode ideality
factor is closer to the maximum or minimum limits. Contact your external sensor
supplier for recommendations. The thermal diode is separate from the Intel Thermal
Monitor’s thermal sensor and cannot be used to predict the behavior of the Intel
Thermal Monitor.
Table 26. Thermal Diode Interface
Signal Name Pin/Ball Number Signal Description
THERMDA A24 Thermal diode anode
THERMDC A25 Thermal diode cathode
Thermal Specifications and Design Considerations
86 Datasheet
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
Intel does not support or recommend operation of the thermal diode when the processor
power supplies are not within their specified tolerance range.
2. Characterized across a temperature range of 50-100°C.
3. Not 100% tested. Specified by design characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by
the diode equation:
IFW = IS * (e qVD/nkT –1)
where IS = saturation current, q = electronic charge, VD = voltage across the diode, k =
Boltzmann Constant, and T = absolute temperature (Kelvin).
5. The series resistance, RT
, is provided to allow for a more accurate measurement of the
junction temperature. RT
, as defined, includes the lands of the processor but does not
include any socket resistance or board trace resistance between the socket and the
external remote diode thermal sensor. RT can be used by remote diode thermal sensors
with automatic series resistance cancellation to calibrate out this error term. Another
application is that a temperature offset can be manually calculated and programmed into
an offset register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N]
where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann
Constant, q = electronic charge.
Table 27. Thermal Diode Parameters Using Diode Model
Symbol Parameter Min Typ Max Unit Notes
IFW Forward Bias Current 5 200 µA 1
n Diode Ideality Factor 1.000 1.009 1.050 2, 3, 4
RTSeries Resistance 2.79 4.52 6.24 Ω2, 3, 5
Datasheet 87
Thermal Specifications and Design Considerations
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Same as IFW in Ta b l e 27 .
3. Characterized across a temperature range of 50-100°C.
4. Not 100% tested. Specified by design characterization.
5. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as
exemplified by the equation for the collector current:
IC = IS * (e qVBE/nQkT –1)
where IS = saturation current, q = electronic charge, VBE = voltage across the transistor
base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
temperature (Kelvin).
6. The series resistance, RT
, provided in the Diode Model Table (Tab l e 27) can be used for
more accurate readings as needed.
When calculating a temperature based on the thermal diode measurements, a number
of parameters must be either measured or assumed. Most devices measure the diode
ideality and assume a series resistance and ideality trim value, although are capable of
also measuring the series resistance. Calculating the temperature is then accomplished
using the equations listed under Ta b l e 2 7 . In most sensing devices, an expected value
for the diode ideality is designed-in to the temperature calculation equation. If the
designer of the temperature sensing device assumes a perfect diode, the ideality value
(also called ntrim) is 1.000. Given that most diodes are not perfect, the designers
usually select an ntrim value that more closely matches the behavior of the diodes in
the processor. If the processor diode ideality deviates from that of the ntrim, each
calculated temperature offsets by a fixed amount. This temperature offset can be
calculated with the equation:
Terror(nf) = Tmeasured * (1 - nactual/ntrim)
where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured
ideality of the diode, and ntrim is the diode ideality assumed by the temperature
sensing device.
5.1.2 Thermal Diode Offset
In order to improve the accuracy of the diode-based temperature measurements, a
temperature offset value (specified as Toffset) is programmed in the processor MSR
which contains thermal diode characterization data. During manufacturing each
processor thermal diode is evaluated for its behavior relative to the theoretical diode.
Using the equation above, the temperature error created by the difference ntrim and the
actual ideality of the particular processor is calculated.
Table 28. Thermal Diode Parameters Using Transistor Model
Symbol Parameter Min Typ Max Unit Notes
IFW Forward Bias Current 5 200 μA1,2
IEEmitter Current 5 200 μA1
nQTransistor Ideality 0.997 1.001 1.005 3,4,5
Beta 0.3 0.760 3,4
RTSeries Resistance 2.79 4.52 6.24 Ω3,6
Thermal Specifications and Design Considerations
88 Datasheet
If the ntrim value used to calculate the Toffset differs from the ntrim value used to in a
temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset
can be adjusted by calculating nactual and then recalculating the offset using the ntrim as
defined in the temperature sensor manufacturer’s datasheet.
The ntrim used to calculate the Diode Correction Toffset are listed in Ta b l e 2 9 .
5.1.3 Intel® Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the
TCC (Thermal Control Circuit) when the processor silicon reaches its maximum
operating temperature. The temperature at which the Intel Thermal Monitor activates
the TCC is not user configurable. Bus traffic is snooped in the normal manner and
interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be minor and hence not detectable. An under-
designed thermal solution that is not able to prevent excessive activation of the TCC in
the anticipated ambient environment may cause a noticeable performance loss and
may affect the long-term reliability of the processor. In addition, a thermal solution that
is significantly under-designed may not be capable of cooling the processor even when
the TCC is active continuously.
The Intel Thermal Monitor controls the processor temperature by modulating (starting
and stopping) the processor core clocks when the processor silicon reaches its
maximum operating temperature. The Intel Thermal Monitor uses two modes to
activate the TCC: automatic mode and on-demand mode. If both modes are activated,
automatic mode takes precedence.
There are two automatic modes called Intel Thermal Monitor 1 and Intel Thermal
Monitor 2. These modes are selected by writing values to the MSRs of the processor.
After automatic mode is enabled, the TCC activates only when the internal die
temperature reaches the maximum allowed value for operation.
When Intel Thermal Monitor 1 is enabled and a high temperature situation exists, the
clocks modulates by alternately turning the clocks off and on at a 50% duty cycle.
Cycle times are processor speed dependent and decreases linearly as processor core
frequencies increase. Once the temperature has returned to a non-critical level,
modulation ceases and TCC goes inactive. A small amount of hysteresis has been
included to prevent rapid active/inactive transitions of the TCC when the processor
temperature is near the trip point. The duty cycle is factory configured and cannot be
modified. Also, automatic mode does not require any additional hardware, software
drivers, or interrupt handling routines. Processor performance decreases by the same
amount as the duty cycle when the TCC is active.
Note: Intel Thermal Monitor 1 and Intel Thermal Monitor 2 features are collectively referred
to as Adaptive Thermal Monitoring features. Intel recommends Intel Thermal Monitor 1
and 2 be enabled on the processors.
Table 29. Thermal Diode ntrim and Diode Correction Toffset
Symbol Parameter Value
ntrim Diode Ideality used to calculate Toffset 1.01
Datasheet 89
Thermal Specifications and Design Considerations
Intel Thermal Monitor 1 and 2 can co-exist within the processor. If both Intel Thermal
Monitor 1 and 2 bits are enabled in the auto-throttle MSR, Intel Thermal Monitor 2
takes precedence over Intel Thermal Monitor 1. However, if Force Intel Thermal Monitor
1 over Intel Thermal Monitor 2 is enabled in MSRs via BIOS and Intel Thermal Monitor
2 is not sufficient to cool the processor below the maximum operating temperature,
then Intel Thermal Monitor 1 also activates to help cool down the processor.
The TCC may also be activated via on-demand mode. If Bit 4 of the ACPI Intel Thermal
Monitor control register is written to a 1, the TCC activates immediately independent of
the processor temperature. When using on-demand mode to activate the TCC, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel
Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on,
50% off, however in on-demand mode, the duty cycle can be programmed from 12.5%
on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be
used at the same time automatic mode is enabled, however, if the system tries to
enable the TCC via on-demand mode at the same time automatic mode is enabled and
a high temperature condition exists, automatic mode takes precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects
that its temperature is above the thermal trip point. Bus snooping and interrupt
latching are also active while the TCC is active.
Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also
includes one ACPI register, one performance counter register, three MSR, and one I/O
pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal
Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt
upon the assertion or deassertion of PROCHOT#.
PROCHOT# is not be asserted when the processor is in the Stop Grant, Sleep, Deep
Sleep, and Deeper Sleep low power states, hence the thermal diode reading must be
used as a safeguard to maintain the processor junction temperature within maximum
specification. If the platform thermal solution is not able to maintain the processor
junction temperature within the maximum specification, the system must initiate an
orderly shutdown to prevent damage. If the processor enters one of the above low
power states with PROCHOT# already asserted, PROCHOT# will remain asserted until
the processor exits the low power state and the processor junction temperature drops
below the thermal trip point.
If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out
of specification. Regardless of enabling the automatic or on-demand modes, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached a temperature of approximately 125°C. At this point the
THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the
processor core voltage must be shut down within the time specified in Chapter 3.
In all cases, the Intel Thermal Monitor feature must be enabled for the processor to
remain within specification.
5.1.4 Digital Thermal Sensor
The processor also contains an on die Digital Thermal Sensor (DTS) that can be read
via an MSR (no I/O interface). Each core of the processor will have a unique digital
thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the
preferred method of reading the processor die temperature since it can be located
much closer to the hottest portions of the die and can thus more accurately track the
die temperature and potential activation of processor core clock modulation via the
Intel Thermal Monitor. The DTS is only valid while the processor is in the normal
operating state (the Normal package level low-power state).
Thermal Specifications and Design Considerations
90 Datasheet
Unlike traditional thermal devices, the DTS will output a temperature relative to the
maximum supported operating temperature of the processor (TJ,max). It is the
responsibility of software to convert the relative temperature to an absolute
temperature. The temperature returned by the DTS will always be at or below TJ,max.
Catastrophic temperature conditions are detectable via an Out Of Spec status bit. This
bit is also part of the DTS MSR. When this bit is set, the processor is operating out of
specification and immediate shutdown of the system should occur. The processor
operation and code execution is not guaranteed once the activation of the Out of Spec
status bit is set.
The DTS-relative temperature readout corresponds to the Intel Thermal Monitor 1/Intel
Thermal Monitor 2 trigger point. When the DTS indicates maximum processor core
temperature has been reached, the Intel Thermal Monitor 1 or 2 hardware thermal
control mechanism will activate. The DTS and Intel Thermal Monitor 1/Intel Thermal
Monitor 2 temperature may not correspond to the thermal diode reading because the
thermal diode is located in a separate portion of the die and thermal gradient between
the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode
can vary substantially due to changes in processor power, mechanical and thermal
attach, and software application. The system designer is required to use the DTS to
guarantee proper operation of the processor within its temperature operating
specifications.
Changes to the temperature can be detected via two programmable thresholds located
in the processor MSRs. These thresholds have the capability of generating interrupts
via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software
Developer’s Manual for specific register and programming details.
5.1.5 Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and
temperature gradient. This feature is intended for graceful shut down before the
THERMTRIP# is activated. If the processor’s Intel Thermal Monitor 1 or 2 are triggered
and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in
the status MSR register and generates thermal interrupt.
5.1.6 PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die
temperature has reached its maximum operating temperature. If Intel Thermal Monitor
1 or 2 is enabled, then the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or deassertion
of PROCHOT#. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s
Manual for specific register and programming details.
The processor implements a bi-directional PROCHOT# capability to allow system
designs to protect various components from overheating situations. The PROCHOT#
signal is bi-directional in that it can either signal when the processor has reached its
maximum operating temperature or be driven from an external source to activate the
TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal
protection of system components.
Only a single PROCHOT# pin exists at a package level of the processor. When either
core's thermal sensor trips, the PROCHOT# signal will be driven by the processor
package. If only Intel Thermal Monitor 1 is enabled, PROCHOT# will be asserted and
only the core that is above TCC temperature trip point will have its core clocks
modulated. If Intel Thermal Monitor 2 is enabled, then regardless of which core(s) are
above TCC temperature trip point, both cores will enter the lowest programmed Intel
Thermal Monitor 2 performance state. It is important to note that Intel recommends
both Intel Thermal Monitor 1 and 2 to be enabled.
Datasheet 91
Thermal Specifications and Design Considerations
When PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is
enabled on both cores, then both processor cores will have their core clocks modulated.
If Intel Thermal Monitor 2 is enabled on both cores, then both processor cores will
enter the lowest programmed Intel Thermal Monitor 2 performance state. It should be
noted that Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2, enabled via BIOS,
does not have any effect on external PROCHOT#. If PROCHOT# is driven by an external
agent when Intel Thermal Monitor 1, Intel Thermal Monitor 2, and Force Intel Thermal
Monitor 1 on Intel Thermal Monitor 2 are all enabled, then the processor will still apply
only Intel Thermal Monitor 2.
PROCHOT# may be used for thermal protection of voltage regulators (VR). System
designers can create a circuit to monitor the VR temperature and activate the TCC
when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low)
and activating the TCC, the VR will cool down as a result of reduced processor power
consumption. Bi-directional PROCHOT# can allow VR thermal designs to target
maximum sustained current instead of maximum current. Systems should still provide
proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case
of system cooling failure. The system thermal design should allow the power delivery
circuitry to operate within its temperature specification even while the processor is
operating at its TDP. With a properly designed and characterized thermal solution, it is
anticipated that bi-directional PROCHOT# would only be asserted for very short periods
of time when running the most power intensive applications. An under-designed
thermal solution that is not able to prevent excessive assertion of PROCHOT# in the
anticipated ambient environment may cause a noticeable performance loss.
§
Thermal Specifications and Design Considerations
92 Datasheet
Datasheet 1
1 Coordination of Core-Level Low-Power States at the Package Level................................. 11
2 Voltage Identification Definition ................................................................................ 19
3 BSEL[2:0] Encoding for BCLK Frequency ..................................................................... 23
4 FSB Pin Groups........................................................................................................ 24
5 Processor Absolute Maximum Ratings ......................................................................... 25
6 DC Voltage and Current Specifications for the T3x00 Celeron Processors ......................... 27
7 DC Voltage and Current Specifications for the T1x00 Celeron Mobile Processors................ 28
8 Voltage and Current Specifications for the Ultra Low Voltage Dual-Core 1M Cache Intel
Celeron SFF Genuine Intel Processor........................................................................... 29
9 FSB Differential BCLK Specifications ........................................................................... 30
10 AGTL+ Signal Group DC Specifications........................................................................ 31
11 CMOS Signal Group DC Specifications ......................................................................... 32
12 Open Drain Signal Group DC Specifications.................................................................. 32
13 The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 1 of 2).......................................................................................................... 39
14 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of
2) .......................................................................................................................... 40
15 SFF Processor Top View Upper Left Side ...................................................................... 41
16 SFF Processor Top View Upper Right Side .................................................................... 42
17 SFF Processor Top View Lower Left Side ...................................................................... 43
18 SFF Processor Top View Lower Right Side .................................................................... 44
19 Pin Listing by Pin Name............................................................................................. 45
20 Pin Listing by Pin Number.......................................................................................... 52
21 SFF Listing by Ball Name........................................................................................... 61
22 Signal Description .................................................................................................... 75
23 Power Specifications for the 3x00 Celeron Processors.................................................... 83
24 Power Specifications for the Intel Celeron Dual-Core Processor - Standard Voltage............ 83
25 Power Specifications for the Ultra Low Voltage Dual-Core 1M Cache Intel Celeron (SFF)
Genuine Intel Processor ............................................................................................ 84
26 Thermal Diode Interface ........................................................................................... 85
27 Thermal Diode Parameters Using Diode Model.............................................................. 86
28 Thermal Diode Parameters Using Transistor Model........................................................ 87
29 Thermal Diode ntrim and Diode Correction Toffset ........................................................ 88
2Datasheet
Datasheet 1
1 Package-Level Low-Power States ............................................................................... 11
2 Core Low-Power States ............................................................................................. 12
3 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................ 34
4 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................ 35
5 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)........................................ 36
6 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)........................................ 37
7 SFF (ULV DC) Die Micro-FCBGA Processor Package Drawing........................................... 38
2Datasheet
Datasheet 1
1Introduction..............................................................................................................7
1.1 Terminology .......................................................................................................8
1.2 References .........................................................................................................9
2 Low Power Features ................................................................................................ 11
2.1 Clock Control and Low Power States .................................................................... 11
2.1.1 Core Low-Power States ........................................................................... 12
2.1.1.1 C0 State .................................................................................. 12
2.1.1.2 C1/AutoHALT Powerdown State .................................................. 12
2.1.1.3 C1/MWAIT Powerdown State ...................................................... 13
2.1.1.4 Core C2 State........................................................................... 13
2.1.1.5 Core C3 State........................................................................... 13
2.1.1.6 Core C4 State........................................................................... 13
2.1.2 Package Low-Power States ...................................................................... 13
2.1.2.1 Normal State............................................................................ 13
2.1.2.2 Stop-Grant State ...................................................................... 13
2.1.2.3 Stop Grant Snoop State............................................................. 14
2.1.2.4 Sleep State .............................................................................. 14
2.1.2.5 Deep Sleep State...................................................................... 15
2.1.2.6 Deeper Sleep State ................................................................... 15
2.2 Enhanced Intel SpeedStep® Technology .............................................................. 15
2.3 Low-Power FSB Features .................................................................................... 16
2.4 Processor Power Status Indicator (PSI#) Signal..................................................... 17
3 Electrical Specifications ........................................................................................... 19
3.1 Power and Ground Pins ...................................................................................... 19
3.2 FSB Clock (BCLK[1:0]) and Processor Clocking...................................................... 19
3.3 Voltage Identification......................................................................................... 19
3.4 Catastrophic Thermal Protection .......................................................................... 22
3.5 Reserved and Unused Pins.................................................................................. 22
3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 23
3.7 FSB Signal Groups............................................................................................. 23
3.8 CMOS Signals ................................................................................................... 25
3.9 Maximum Ratings.............................................................................................. 25
3.10 Processor DC Specifications ................................................................................ 26
4 Package Mechanical Specifications and Pin Information .......................................... 33
4.1 Package Mechanical Specifications ....................................................................... 33
4.2 Processor Pinout and Pin List .............................................................................. 39
4.3 Alphabetical Signals Reference ............................................................................ 75
5 Thermal Specifications and Design Considerations .................................................. 83
5.1 Monitoring Die Temperature ............................................................................... 84
5.1.1 Thermal Diode ....................................................................................... 85
5.1.2 Thermal Diode Offset .............................................................................. 87
5.1.3 Intel® Thermal Monitor........................................................................... 88
5.1.4 Digital Thermal Sensor............................................................................ 89
5.1.5 Out of Specification Detection .................................................................. 90
5.1.6 PROCHOT# Signal Pin ............................................................................. 90
2Datasheet
