Product specification -Feb 22, 2005 V.1 Supersedes Date of Mar. 06, 2003 DATA SHEET ARRAY CHIP RESISTORS YC324 (8Pin/4R; Pb Free) sizes 1220 5%, 1% Product specification Chip Resistor Surface Mount YC SERIES 2 8 324 (Pb Free) SCOPE This specification describes YC324 series chip resistor arrays with lead-free terminations made by thick film process. ORDERING INFORMATION Part number is identified by the series, size, tolerance, packing type, temperature coefficient, taping reel and resistance value. YAGEO ORDERING CODE CTC ORDERING EXAMPLE CODE YC324 - X X X XX XXXX L (1) (2) (3) (4) (5) (6) (1) TOLERANCE F = 1% J = 5% (2) PACKAGING TYPE K = Embossed taping reel (3) TEMPERATURE COEFFICIENT OF RESISTANCE - = Base on spec The ordering code of a YC324 convex chip resistor array, value 1,000 X with 5% tolerance, supplied in 7-inch tape reel is: YC324-JK-071KL. NOTE 1. The "L" at the end of the code is only for ordering. On the reel label, the standard CTC will be mentioned an additional stamp "LFP"= lead free production. 2. Products with lead in terminations fulfil the same requirements as mentioned in this datasheet. 3. Products with lead in terminations will be phased out in the coming months (before July 1st, 2006) (4) TAPING REEL 07 = 7 inch dia. Reel (5) RESISTANCE VALUE 56R, 560R, 5K6, 56K, 1M (6) RESISTOR TERMINATIONS L = Lead free terminations (pure Tin) www.yageo.com Feb 22, 2005 V.1 Product specification Chip Resistor Surface Mount YC 3 8 324 (Pb Free) SERIES MARKING YC324 E-24 series: 3 digits 2 First two digits for significant figure and 3rd digit for number of zeros YNSC031 Fig. 1 Value = 240 K For marking codes, please see EIA-marking code rules in data sheet "Chip resistors marking". CONSTRUCTION The resistors are constructed out of a high-grade ceramic body. Internal metal electrodes are added at each end and connected by a resistive paste. The composition of the paste is adjusted to give the approximate required resistance and laser cutting of this resistive layer that achieves Fig. 2 Chip resistor construction tolerance trims the value. The resistive layer is covered with a protective coat. Finally, the eight external terminations (pure Tin) are added. See fig. 2. protective coat resistor layer inner electrode end termination ceramic substrate YNSC053 DIMENSIONS Table 1 TYPE YC324 B (mm) 0.50 0.20 H (mm) 1.10 0.15 P (mm) 1.27 0.05 L (mm) 5.08 0.20 H2 (mm) 0.90 0.15 T (mm) 0.60 0.10 W1 (mm) 0.50 0.15 W2 (mm) 3.20 0.20 H a T B W1 W2 P L a CCB257_b H2 Fig. 3 YC324 series chip resistors dimension For dimension see Table 1 SCHEMATIC For dimension see Fig. 3 and Table 1 8 7 6 5 handbook, 2 columns R1 R2 R3 R4 CCA862_c Fig. 4 Equivalent circuit diagram R1=R2=R3=R4 1 2 3 4 www.yageo.com Feb 22, 2005 V.1 Product specification Chip Resistor Surface Mount YC SERIES ELECTRICAL CHARACTERISTICS FOOTPRINT AND SOLDERING PROFILES Table 2 YC324 1/8 W CHARACTERISTICS Operating Temperature Range -55 C to +155 C Maximum Working Voltage 200 V Maximum Overload Voltage 500 V Dielectric Withstanding Voltage 500 V Number of Resistors 4 5% (E24) 10 to 1 M Resistance Range 4 8 324 (Pb Free) 1% (E24/E96) 10 to 1 M Temperature Coefficient 200 ppm/C For recommended footprint and soldering profiles, please see the special data sheet "Chip resistors mounting". ENVIRONMENTAL DATA For material declaration information (IMDS-data) of the products, please see the separated info "Environmental data" conformed to EU RoHS. PACKING STYLE AND PACKAGING QUANTITY Table 3 Packing style and packaging quantity PRODUCT TYPE PACKING STYLE REEL DIMENSION YC324 Embossed taping reel (K) 7" (178 mm) QUANTITY PER REEL 4,000 units NOTE 1. For embossed tape and reel specification/dimensions, please see the special data sheet "Packing" document. FUNCTIONAL DESCRIPTION POWER RATING YC324 rated power at 70C is 1/8 W RATED VOLTAGE The DC or AC (rms) continuous working voltage corresponding to the rated power is determined by the following formula: V = (P X R) Where V = Continuous rated DC or AC (rms) working voltage (V) P = Rated power (W) MRA632 Pmax (%Prated) 100 50 0 -55 0 50 70 155 100 Tamb (C) Fig. 5 Maximum dissipation (Pmax) in percentage of rated power as a function of the operating ambient temperature (Tamb ) R = Resistance value (X) www.yageo.com Feb 22, 2005 V.1 Product specification Chip Resistor Surface Mount YC 5 8 324 (Pb Free) SERIES TESTS AND REQUIREMENTS Table 4 Test condition, procedure and requirements TEST Temperature Coefficient of Resistance (T.C.R.) TEST METHOD PROCEDURE REQUIREMENTS MIL-STD-202F-method 304; At +25/-55 C and +25/+125 C Refer to table 2 JIS C 5202-4.8 Formula: R 2 - R1 T.C.R = ------------------------x 106 (ppm/C) R1(t2 - t1) Where t1 = +25 C or specified room temperature t2 = -55 C or +125 C test temperature R1 = resistance at reference temperature in ohms R2 = resistance at test temperature in ohms Thermal Shock MIL-STD-202F-method 107G; IEC 60115-1 4.19 Low Temperature Operation MIL-R-55342D-Para 4.7.4 Short Time Overload MIL-R-55342D-Para 4.7.5; At -65 (+0/-10) C for 2 minutes and at +155 (+10/-0) C for 2 minutes; 25 cycles (0.5% +0.05 ) for 1% tol. At -65 (+0/-5) C for 1 hour; RCWV applied for 45 (+5/-0) minutes (0.5% +0.05 ) for 1% tol . (1.0% +0.05 ) for 5% tol. (1.0% +0.05 ) for 5% tol. No visible damage IEC 60115-1 4.13 2.5 x RCWV applied for 5 seconds at room temperature (1.0% +0.05 ) for 1% tol. (2.0% +0.05 ) for 5% tol. No visible damage Insulation Resistance MIL-STD-202F-method 302; RCOV for 1 minute IEC 60115-1 4.6.1.1 Type Voltage (DC) Dielectric Withstand Voltage 10 G YC324 500 V MIL-STD-202F-method 301; Maximum voltage (Vrms) applied for 1 minute IEC 60115-1 4.6.1.1 Type Voltage (AC) Resistance to Soldering Heat MIL-STD-202F-method 210C; Life MIL-STD-202F-method 108A; No breakdown or flashover YC324 500 Vrms Unmounted chips; 260 5 C for 10 1 seconds IEC 60115-1 4.18 (0.5% +0.05 ) for 1% tol. (1.0% +0.05 ) for 5% tol. No visible damage IEC 60115-1 4.25.1 At 70 2 C for 1,000 hours; RCWV applied for 1.5 hours on and 0.5 hour off (1% +0.05 ) for 1% tol. (3% +0.05 ) for 5% tol. www.yageo.com Feb 22, 2005 V.1 Product specification Chip Resistor Surface Mount TEST Solderability Bending Strength Resistance to Solvent Noise YC SERIES TEST METHOD PROCEDURE REQUIREMENTS MIL-STD-202F-method 208A; Solder bath at 245 3 C Well tinned (95% covered) IEC 60115-1 4.17 Dipping time: 2 0.5 seconds No visible damage Resistors mounted on a 90 mm glass epoxy resin PCB (FR4) (1.0% +0.05 ) for 1% tol. Bending: 1 mm No visible damage No smeared IEC 60115-1 4.29 lsopropylalcohol (C3H7OH) or dichloromethane (CH2Cl2) followed by brushing JIS C 5202 5.9; Maximum voltage (Vrms) applied. Resistors range Value R < 100 10 dB 100 R < 1 K 20 dB 1 K R < 10 K 30 dB 10 K R < 100 K 40 dB 100 K R < 1 M 46 dB 1 M R 22 M 48 dB JIS C 5202.6.14; IEC 60115-1 4.15 MIL-STD-202F-method 215; IEC 60115-1 4.12 Humidity (steady state) Leaching Intermittent Overload Resistance to Vibration Moisture Resistance Heat 6 8 324 (Pb Free) (1.0% +0.05 ) for 5% tol. JIS C 5202 7.5; 1,000 hours; 40 2 C; 93(+2/-3)% RH IEC 60115-8 4.24.8 (0.5% +0.05 ) for 1% tol. RCWV applied for 1.5 hours on and 0.5 hour off (2.0% +0.05 ) for 5% tol. EIA/IS 4.13B; Solder bath at 260 5 C No visible damage IEC 60115-8 4.18 Dipping time: 30 1 seconds JIS C 5202 5.8 At room temperature; 2.5 x RCWV applied for 1 second on and 25 seconds off; total 10,000 cycles (1.0% +0.05 ) for 1% tol. (2.0% +0.05 ) for 5% tol. On request On request MIL-STD-202F-method 106F; 42 cycles; total 1,000 hours (0.5% +0.05) for 1% tol. IEC 60115-1 4.24.2 Shown as Fig. 6 (2.0% +0.05) for 5% tol. No visible damage www.yageo.com Feb 22, 2005 V.1 Product specification Chip Resistor Surface Mount 75 YC 80 - 98% RH 90 - 98% RH temperature [C] SERIES 90 - 98% RH 7 8 324 (Pb Free) 80 - 98% RH 90 - 98% RH initial drying 24 hours rate of change of temperature is unspecified, however, specimens shall not be subjected to radiant heating from chamber conditioning processes 50 end of final cycle; measurements as specified in 2.7 +10 C (+18 F) -2 C (-3.6 F) 25 initial measurements as specified in 2.2 0 temperature tolerance 2 C (3.6 F) unless otherwise specified voltage applied as specified in 2.4 STEP1 STEP2 prior to first cycle only HBK073 optional sub-cycle if specified (2.3); sub-cycle performed during any 5 of the first 9 cycles; humidity uncontrolled during sub-cycle circulation of conditioning air shall be at a minimum cubic rate per minute equivalent to 10 times the volume of the chamber STEP3 STEP4 STEP5 STEP6 STEP7 one cycle 24 hours; repeat as specified in 2.5 0 5 10 15 20 25 time [h] Fig. 6 Moisture resistance test requirements www.yageo.com Feb 22, 2005 V.1 Product specification Chip Resistor Surface Mount YC SERIES 324 (Pb Free) 8 8 REVISION HISTORY REVISION DATE CHANGE NOTIFICATION DESCRIPTION Version 1 Feb 22, 2005 - - Test method and procedure updated Version 0 Nov. 10, 2003 - - First issue of PbFree specification www.yageo.com Feb 22, 2005 V.1