DATA SHEE
T
ARRAY CHIP RESISTORS
YC324 (8Pin/4R; Pb Free)
5%, 1%
sizes 1220
Product specification –Feb 22, 2005 V.1 Supersedes Date of Mar. 06, 2003
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Feb 22, 2005 V.1
Product specification
Chip Resistor Surface Mount
2
8
SERIES
YC 324 (Pb Free)
Y
YA
AG
GE
EO
O
O
OR
RD
DE
ER
RI
IN
NG
G
C
CO
OD
DE
E
CTC CODE
YC324 – X X X XX XXXX L
(1) (2) (3) (4) (5) (6)
(1) TOLERANCE
F = ±1%
J = ±5%
(2) PACKAGING TYPE
K = Embossed taping reel
(3) TEMPERATURE COEFFICIENT OF RESISTANCE
– = Base on spec
(4) TAPING REEL
07 = 7 inch dia. Reel
(5) RESISTANCE VALUE
56R, 560R, 5K6, 56K, 1M
(6) RESISTOR TERMINATIONS
L = Lead free terminations (pure Tin)
ORDERING EXAMPLE
The ordering code of a YC324 convex chip resistor
array, value 1,000 X with ±5% tolerance, supplied in
7-inch tape reel is: YC324-JK-071KL.
NOTE
1. The “L” at the end of the code is only for ordering. On the reel
label, the standard CTC will be mentioned an additional stamp
“LFP”= lead free production.
2. Products with lead in terminations fulfil the same requirements
as mentioned in this datasheet.
3. Products with lead in terminations will be phased out in the
coming months (before July 1st, 2006)
SCOPE
This specification describes YC324 series chip resistor arrays with lead-free terminations made by thick film
process.
ORDERING INFORMATION
Part number is identified by the series, size, tolerance, packing type, temperature coefficient, taping reel and
resistance value.
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Feb 22, 2005 V.1
Product specification
Chip Resistor Surface Mount
3
8
SERIES
YC 324 (Pb Free)
DIMENSIONS
TYPE YC324
B (mm) 0.50 ±0.20
H (mm) 1.10 ±0.15
P (mm) 1.27 ±0.05
L (mm) 5.08 ±0.20
H2 (mm) 0.90 ±0.15
T (mm) 0.60 ±0.10
W1 (mm) 0.50 ±0.15
W2 (mm) 3.20 ±0.20
Table 1
protective coat. Finally, the eight external terminations (pure Tin) are added. See fig. 2.
CONSTRUCTION
The resistors are constructed out of
a high-grade ceramic body. Internal
metal electrodes are added at each
end and connected by a resistive
paste. The composition of the paste
is adjusted to give the approximate
required resistance and laser cutting
of this resistive layer that achieves
tolerance trims the value. The
resistive layer is covered with a
protective coat
resistor layer
inner electrode
end termination
ceramic substrate
YNSC053
Fig. 2 Chip resistor construction
CCB257_b
H
2
Ha
a
P
L
B
T
W1
W2
Fig. 3
Y
C324 series chip resistors dimension For dimension see Table 1
SCHEMATIC
handbook, 2 columns
R1 R2 R3 R4
CCA862_c
12
87
3
6
4
5
Fig. 4 Equivalent circuit diagram
For dimension see Fig. 3 and Table 1
R1=R2=R3=R4
MARKING
YC324
E-24 series: 3 digits
First two digits for significant figure and 3rd digit for number of zeros
For marking codes, please see EIA-marking code rules in data sheet “Chip resistors marking”.
Fig. 1 Value = 240 KΩ
YNSC031
2
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Feb 22, 2005 V.1
Product specification
Chip Resistor Surface Mount
4
8
SERIES
YC 324 (Pb Free)
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS YC324 1/8 W
Operating Temperature Range –55 °C to +155 °C
Maximum Working Voltage 200 V
Maximum Overload Voltage 500 V
Dielectric Withstanding Voltage 500 V
Number of Resistors 4
5% (E24) 10 Ω to 1 MΩ
Resistance Range 1% (E24/E96) 10 Ω to 1 MΩ
Temperature Coefficient ±200 ppm/°C
FOOTPRINT AND SOLDERING
PROFILES
For recommended footprint and
soldering profiles, please see the
special data sheet “Chip resistors
mounting”.
ENVIRONMENTAL DATA
For material declaration
information (IMDS-data) of the
products, please see the
separated info “Environmental
data" conformed to EU RoHS.
Table 2
MRA632
70 100
−55 50
Tamb (°C)
(%Prated)
0
0
50
100
155
Pmax
Fig. 5 Maximum dissipation (Pmax) in percentage of rated power
as a function of the operating ambient temperature (Tamb)
FUNCTIONAL DESCRIPTION
P
PO
OW
WE
ER
R
R
RA
AT
TI
IN
NG
G
YC324 rated power at 70°C is 1/8 W
RATED VOLTAGE
The DC or AC (rms) continuous working voltage
corresponding to the rated power is determined by
the following formula:
V = √(P X R)
Where
V = Continuous rated DC or
AC (rms) working voltage (V)
P = Rated power (W)
R = Resistance value (X)
PACKING STYLE AND P
A
CKAGING QUANTITY
PRODUCT TYPE PACKING STYLE REEL DIMENSION QUANTITY PER REEL
YC324 Embossed taping reel (K) 7" (178 mm) 4,000 units
NOTE
1. For embossed tape and reel specification/dimensions, please see the special data sheet “Packing” document.
Table 3 Packing style and packaging quantity
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Feb 22, 2005 V.1
Product specification
Chip Resistor Surface Mount
5
8
SERIES
YC 324 (Pb Free)
TESTS AND REQUIREMENTS
TEST TEST METHOD PROCEDURE REQUIREMENTS
At +25/–55 °C and +25/+125 °C Temperature
Coefficient o
f
Resistance
(T.C.R.)
MIL-STD-202F-method 304;
JIS C 5202-4.8
Formula:
T.C.R = ------------------------- × 106 (ppm/°C)
Where
t1 = +25 °C or specified room temperature
t2 = –55 °C or +125 °C test temperature
R1 = resistance at reference temperature in ohms
R2 = resistance at test temperature in ohms
Refer to table 2
Thermal Shoc
k
MIL-STD-202F-method 107G;
IEC 60115-1 4.19
At –65 (+0/–10) °C for 2 minutes and at +155
(+10/–0) °C for 2 minutes; 25 cycles
±(0.5% +0.05 Ω) for 1% tol.
±(1.0% +0.05 Ω) for 5% tol.
Low
Temperature
Operation
MIL-R-55342D-Para 4.7.4 At –65 (+0/–5) °C for 1 hour; RCWV applied for
45 (+5/–0) minutes
±(0.5% +0.05 Ω) for 1% tol .
±(1.0% +0.05 Ω) for 5% tol.
No visible damage
Short Time
Overload
MIL-R-55342D-Para 4.7.5;
IEC 60115-1 4.13
2.5 × RCWV applied for 5 seconds at room
temperature
±(1.0% +0.05 Ω) for 1% tol.
±(2.0% +0.05 Ω) for 5% tol.
No visible damage
Insulation
Resistance
MIL-STD-202F-method 302;
IEC 60115-1 4.6.1.1
RCOV for 1 minute
Type YC324
Voltage (DC) 500 V
≥10 GΩ
Dielectric
Withstand
Voltage
MIL-STD-202F-method 301;
IEC 60115-1 4.6.1.1
Maximum voltage (Vrms) applied for 1 minute
Type YC324
Voltage (AC) 500 Vrms
No breakdown or flashover
Resistance to
Soldering
Heat
MIL-STD-202F-method 210C;
IEC 60115-1 4.18
Unmounted chips; 260 ±5 °C for 10 ±1 seconds ±(0.5% +0.05 Ω) for 1% tol.
±(1.0% +0.05 Ω) for 5% tol.
No visible damage
Life MIL-STD-202F-method 108A;
IEC 60115-1 4.25.1
At 70 ±2 °C for 1,000 hours; RCWV applied for
1.5 hours on and 0.5 hour off
±(1% +0.05 Ω) for 1% tol.
±(3% +0.05 Ω) for 5% tol.
R2 – R1
R1(t2 – t1)
Table 4 Test condition, procedure and requirements
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Feb 22, 2005 V.1
Product specification
Chip Resistor Surface Mount
6
8
SERIES
YC 324 (Pb Free)
TEST TEST METHOD PROCEDURE REQUIREMENTS
Solderabilit
y
MIL-STD-202F-method 208A;
IEC 60115-1 4.17
Solder bath at 245 ±3 °C
Dipping time: 2 ±0.5 seconds
Well tinned (≥95% covered)
No visible damage
Bending
Strength
JIS C 5202.6.14;
IEC 60115-1 4.15
Resistors mounted on a 90 mm glass epoxy
resin PCB (FR4)
Bending: 1 mm
±(1.0% +0.05 Ω) for 1% tol.
±(1.0% +0.05 Ω) for 5% tol.
No visible damage
Resistance to
Solvent
MIL-STD-202F-method 215;
IEC 60115-1 4.29
lsopropylalcohol (C3H7OH) or dichloromethane
(CH2Cl2) followed by brushing
No smeared
Noise JIS C 5202 5.9;
IEC 60115-1 4.12
Maximum voltage (Vrms) applied. Resistors range
V
alue
R < 100 Ω 10 dB
100 Ω ≤ R < 1 KΩ 20 dB
1 KΩ ≤ R < 10 KΩ 30 dB
10 KΩ ≤ R < 100 KΩ40 dB
100 KΩ ≤ R < 1 MΩ46 dB
1 MΩ ≤ R ≤ 22 MΩ48 dB
Humidit
(steady state)
JIS C 5202 7.5;
IEC 60115-8 4.24.8
1,000 hours; 40 ±2 °C; 93(+2/–3)% RH
RCWV applied for 1.5 hours on and 0.5 hour of
f
±(0.5% +0.05 Ω) for 1% tol.
±(2.0% +0.05 Ω) for 5% tol.
Leaching EIA/IS 4.13B;
IEC 60115-8 4.18
Solder bath at 260 ±5 °C
Dipping time: 30 ±1 seconds
No visible damage
Intermittent
Overload
JIS C 5202 5.8
At room temperature; 2.5 × RCWV applied for
1 second on and 25 seconds off; total 10,000
cycles
±(1.0% +0.05 Ω) for 1% tol.
±(2.0% +0.05 Ω) for 5% tol.
Resistance to
Vibration
On request On request
Moisture
Resistance
Heat
MIL-STD-202F-method 106F;
IEC 60115-1 4.24.2
42 cycles; total 1,000 hours
Shown as Fig. 6
±(0.5% +0.05Ω) for 1% tol.
±(2.0% +0.05Ω) for 5% tol.
No visible damage
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Feb 22, 2005 V.1
Product specification
Chip Resistor Surface Mount
7
8
SERIES
YC 324 (Pb Free)
75
initial drying
24 hours
90 − 98% RH
80 − 98%
RH
temperature
tolerance
±2 °C (±3.6 °F)
unless otherwise
specified
initial measurements
as specified in 2.2
0
STEP1 STEP3STEP2
prior to first
cycle only
STEP4
one cycle 24 hours; repeat as specified in 2.5
voltage applied as specified in 2.4
circulation of conditioning air shall be at a
minimum cubic rate per minute equivalent to
10 times the volume of the chamber
STEP6 STEP7
HBK073
STEP5
51015
end of final cycle;
measurements
as specified in 2.7
optional sub-cycle if specified
(2.3); sub-cycle performed during
any 5 of the first 9 cycles; humidity
uncontrolled during sub-cycle
20
time [h]
temperature
[°C]
25
50
25
0
90 − 98% RH 90 − 98% RH
+10 °C (+18 °F)
−2 °C (−3.6 °F)
80 − 98%
RH
rate of change of temperature is unspecified,
however, specimens shall not be subjected to
radiant heating from chamber conditioning processes
Fig. 6 Moisture resistance test requirements
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Feb 22, 2005 V.1
Product specification
Chip Resistor Surface Mount
8
8
SERIES
YC 324 (Pb Free)
REVISION HISTORY
REVISION DATE CHANGE NOTIFICATION DESCRIPTION
Version 1 Feb 22, 2005 - - Test method and procedure updated
Version 0 Nov. 10, 2003 - - First issue of PbFree specification