HUF75545S3ST_F101 - FAIRCHILD SEMICONDUCTOR

HUF75545P3, HUF75545S3, HUF75545S3S

75A, 80V, 0.010 Ohm, N-Channel,

UltraFET® Power MOSFET

Packaging

Symbol

Features

• Ultra Low On-Resistance

-r

DS(ON) = 0.010Ω, VGS = 10V

• Simulation Models

- Temperature Compensated PSPICE® and SABER™

Electrical Models

- Spice and SABER Thermal Impedance Models

- www.fairchildsemi.com

• Peak Current vs Pulse Width Cur ve

• UIS Rating Curve

Ordering Information

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

Product r e liability infor m a tion can be found at http ://www.fairchildsemi.com/products/dis crete/reliability/index . ht m l

For severe environments, see our Automotive HUFA series.

All Fairchi ld semiconductor products are manufactured, assembled and t ested under ISO9000 and QS9000 quality systems certificat ion.

JEDEC TO-220AB JEDEC TO-263AB

JEDEC TO-262AA

DRAIN

(FLANGE)

DRAIN

SOURCE

GATE

HUF75545P3

GATE

SOURCE

DRAIN

(FLANGE)

HUF75545S3S

DRAIN

(FLANGE)

DRAIN

SOURCE

GATE

HUF75545S3

PART NUMBER PACKAGE BRAND

HUF75545P3 TO-220AB 75545P

HUF75545S3 TO-262AA 75545S

HUF75545S3S TO-263AB 75545S

NO TE: Whe n orde ring, use the enti re pa rt nu mber . A dd th e suf fix T to

obtain the TO-263AB variant in tape and reel, e.g., HUF75545S3ST.

HUF75545P3, HUF75545S3,

HUF75545S3S UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 80 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 80 V

Gate to Sou rc e Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

GS ±20 V

Drain Current

Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID

Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM

Figure 4

Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figure 6

Powe r Dis sipatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

1.8 W

W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC

Maximum Temperature for Solder ing

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL

P ackage Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300

260

NOTES:

1. TJ = 25oC to 150oC.

CAUTION: Stresse s above those listed in “Ab solute Maximum Ratings” may cause perman ent damage to the device. This is a stre ss only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Data Sheet September 2002

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 80 - - V

Zero Gate Voltage Drain Current IDSS VDS = 75V, VGS = 0V - - 1 µA

VDS = 70V, VGS = 0V, TC = 150oC - - 250 µA

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

ON STAT E SPECIFICATIONS

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V

Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figure 9) - 0.0082 0.010 Ω

THERMAL SP ECIFICA T I ONS

Thermal Resistance Junction to Case RθJC TO-220 and TO-263 - - 0.55 oC/W

Thermal Resistance Junction to

Ambient RθJA --62

oC/W

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time tON VDD = 40V, ID = 75A

VGS = 10V,

RGS = 2.5Ω

- - 210 ns

Turn-On Delay Time td(ON) -14-ns

Rise Time tr- 125 - ns

Turn-Off Delay Time td(OFF) -40-ns

Fall Ti me tf- 90 - ns

Turn-Off Time tOFF - - 195 ns

GATE CHARGE SPECIFICATIONS

Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 40V,

ID = 75A,

Ig(REF) = 1.0mA

(Figure 13)

- 195 235 nC

Gate Charge at 10V Qg(10) VGS = 0V to 10V - 105 125 nC

Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 6.8 8. 2 nC

Gate to Source Gate Charge Qgs -15-nC

Gate to Drain “Miller” Charge Qgd -43-nC

CAPACITANCE SPECIFICATIONS

Input Capacitance CISS VDS = 25V, VGS = 0V,

f = 1MHz

(Figure 12)

- 3750 - pF

Output Capacitance COSS - 1100 - pF

Reverse Transfer Capacitance CRSS - 350 - pF

Sour ce to Drain Diode Specific ations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage VSD ISD = 75A - - 1.25 V

ISD = 35A - - 1.00 V

Reverse Recovery Time trr ISD = 75A, dISD/dt = 100A/µs - - 100 ns

Reverse Recovered Charge QRR ISD = 75A, dISD/dt = 100 A/ µs - - 300 nC

HUF75545P3, HUF75545S3, HUF75545S3S

Typical Performance Curves

FIGURE 1. NORMALIZED PO WER DISSIPA TION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

FIGURE 4. PEAK CURRENT CAPABILITY

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00 25 50 75 100 175

0.2

0.4

0.6

0.8

1.0

1.2

125 150

50 75 100 125 150

025

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

VGS = 10V

175

0.1

10-4 10-3 10-2 10-1 100101

0.0110-5

t, RECTANGULAR PULSE DURATION (s)

ZθJC, NORMALIZED

THERMAL IMPED ANCE

SINGLE PULSE NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.01

0.02

100

2000

10-4 10-3 10-2 10-1 100101

10-5

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

TC = 25oC

I = I25 175 - TC

150

FOR TEMPERATURES

ABO VE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 10V

1000

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

HUF75545P3, HUF75545S3, HUF75545S3S

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

NOT E: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

FIGURE 9. NORMALIZED DRAIN T O SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD V OLT AGE vs

JUNCTION TEMPERATURE

Typical Performance Curves (Continued)

100

110100

600

200

100µs

10ms

1ms

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

TJ = MAX RATED

TC = 25oC

SINGLE PULSE

100

600

0.001 0.01 0.1 10

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

STARTING TJ = 25oC

STARTING TJ = 150oC

120

150

23456

ID, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15V

TJ = 175oC

TJ = 25oC TJ = -55oC30

120

150

01234

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS =5V

VGS = 20V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

TC = 25oC

VGS = 10V VGS = 7V

VGS = 6V

0.5

1.0

1.5

2.0

2.5

-80 -40 0 40 80 120 200

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

VGS = 10V, ID = 75A

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

160 0.4

0.8

1.0

1.2

-80 -40 0 40 80 120 200

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

THRESHOLD VOLTAGE

0.6

160

HUF75545P3, HUF75545S3, HUF75545S3S

FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDO WN

VOLTAGE vs JUNCTIO N TEMP ERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

NOT E : Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

Typical Performance Cur ves (Contin ued)

0.9

1.0

1.1

1.2

-80 -40 0 40 80 120 160 200

0.8

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE

ID = 250µA

1000

10000

0.1 1 10 80

100

C, CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 0V, f = 1MHz

CISS = CGS + CGD

COSS ≅ CDS + CGD

CRSS = CGD

0 30 60 90 120

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = 40V

Qg, GATE CHARGE (nC)

ID = 75A

ID = 35A

WAVEFORM S IN

DESCENDING ORDER:

HUF75545P3, HUF75545S3, HUF75545S3S

Test Circuits and Waveforms

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PE AK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 2V

Qg(10)

VGS = 10V

Qg(TOT)

VGS = 20V

VDS

VGS

Ig(REF)

Qgs Qgd

VGS

RGS DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

PSPICE Elec trical Model

.SUBCKT HUF75545 2 1 3 ; rev 21 May 1999

CA 12 8 5.4e-9

CB 15 14 5.3e-9

CIN 6 8 3.4e-9

DBODY 7 5 DBODYMOD

DBREAK 5 11 DBREAKMOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 87.4

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTHRES 6 21 19 8 1

EVTEM P 20 6 18 22 1

IT 8 17 1

LDRA IN 2 5 1.0 e - 9

LGATE 1 9 5.1e-9

LSOURCE 3 7 4.4e-9

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 MSTROMOD

MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 4.80e-3

RGATE 9 20 0.87

RLDRAIN 2 5 10

RLGATE 1 9 51

RLSOURCE 3 7 44

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 1.6e-3

RVTHRES 22 8 RVTHRESMOD 1

RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AM OD

S1B 13 12 13 8 S1BMOD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VA LUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*320) ,3))}

.MODEL DBODYMOD D (IS = 3.6e-12 RS = 2.1e-3 TRS1 = 1.5e-3 TRS2 = 5.1e-6 CJO = 4.6e-9 TT = 3.3e-8 M = 0.55)

.MODEL DBREAKMOD D (RS = 2.3e-1 TRS1 = 0 TRS2 = -1.8e-5)

.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10 VJ = 1 M = 0.8)

.MODEL MMEDMOD NMOS (VTO = 3.04 KP = 6 IS = 1e-3 0 N = 10 T OX = 1 L = 1u W = 1u RG = 0.87)

.MODEL MSTROMOD NMOS (VTO = 3.5 KP = 105 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MOD EL MWEAKMOD NMOS (VTO = 2.65 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8. 7 )

.MODEL RBREAKMOD RES (TC1 = 1.3e-3 TC2 = -1e-6)

.MODEL RDRAINMOD R ES (TC1 = 9e-3 TC2 = 2.8e-5)

.MODEL RSLCMOD RES (TC1 = 1.53e- 3 TC2 = 2e-5)

.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)

.MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.2e-5)

.MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 5e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5 VOFF= -3)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= 0.5)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.5)

.ENDS

NOT E: For furth er discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the P ower MOSFET Feat ur ing Global

Temperature Options; IEEE Po wer Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. F rank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

HUF75545P3, HUF75545S3, HUF75545S3S

SABER Electrical Model

REV 21 may 1999

template huf75545 n2 ,n1,n3

electrical n2,n1,n3

{

var i iscl

d..model dbodymod = (is = 3. 6e-12, cjo = 4.6e-9, tt = 3.3e-8, m = 0. 55)

d..model dbreakmod = ()

d..model dplcapmod = (cjo = 4.8 e-9, is = 1e-30, vj=1.0, m = 0.8 )

m..model mmedmod = (type=_n, v to = 3.04, kp = 6, is = 1e-30, tox = 1)

m..model mstrongmod = (type=_n, vto = 3.5, kp = 105, is = 1e-30, tox = 1)

m..model mweakmod = (type=_n, vto = 2.65, kp = 0.12, is = 1e-30, tox = 1)

sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3)

sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -5)

sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0.5)

sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.5)

c.ca n12 n8 = 5. 4e-9

c.cb n15 n14 = 5.3e-9

c.ci n n6 n8 = 3. 4e-9

d.dbody n7 n71 = model=dbodymod

d.dbreak n72 n11 = model=dbreakmod

d.dplc ap n10 n5 = model=dplcapmod

i.it n8 n17 = 1

l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 5.1e-9

l.lsou rce n3 n7 = 4.4e-9

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc 1 = 1.3e-3, tc2 = -1e-6

res.rdbody n71 n5 = 2.1e-3, tc1 = 1.5e-3, tc2 = 5.1e-6

res.rdbreak n72 n5 = 2.3e-1, tc1 = 0, tc2 = -1.8e-5

res.rdrain n50 n16 = 4.8e-3 , tc1 = 9e-3, tc2 = 2.8e-5

res.rgate n9 n20 = 0.87

res.rldrain n2 n5 = 10

res.r l gate n1 n9 = 51

res.rlsource n3 n7 = 44

res.rslc1 n5 n51 = 1e- 6, tc1 = 1. 53e-3, tc2 = 2e-5

res.rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 1.6e-3, tc1 = 1e-3, tc2 = 1e -6

res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 5e-7

res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.2e-5

spe.e b reak n11 n7 n17 n18 = 87.4

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

spe.evthres n6 n21 n1 9 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equa tions {

i (n51- >n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+ab s(v(n5,n51))))*((abs(v(n5,n51)*1e6/320))** 3))

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

RDBODY

RDBREAK

SPICE Thermal Model

REV 21 May 1999

HUF75545T

CTHERM1 th 6 6.4e-3

CTHERM2 6 5 3.0e-2

CTHERM3 5 4 1.4e-2

CTHERM4 4 3 1.6e-2

CTHERM5 3 2 5.5e-2

CTHERM6 2 tl 1.5

RTHERM1 th 6 3.2e-3

RTHERM2 6 5 8.1e-3

RTHERM3 5 4 2.3e-2

RTHERM4 4 3 1.3e-1

RTHERM5 3 2 1.8e-1

RTHERM6 2 tl 3.8e-2

SABER Thermal Model

SABER thermal mode l HUF75545T

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm1 th 6 = 6.4e-3

ctherm.ctherm2 6 5 = 3.0e-2

ctherm.ctherm3 5 4 = 1.4e-2

ctherm.ctherm4 4 3 = 1.6e-2

ctherm.ctherm5 3 2 = 5.5e-2

ctherm.ctherm 6 2 tl = 1.5

rtherm.rtherm1 th 6 = 3.2e-3

rtherm.rtherm2 6 5 = 8.1e-3

rtherm.rtherm3 5 4 = 2.3e-2

rtherm.rtherm4 4 3 = 1.3e-1

rtherm.rtherm5 3 2 = 1.8e-1

rtherm.rtherm6 2 tl = 3.8e-2

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

HUF75545P3, HUF75545S3, HUF75545S3S

Rev. I1

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not

intended to be an exhaustive list of all such trademarks.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHE R NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used herein:

1. Life support devices or s yst ems are dev ices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

ACEx™

ActiveArray™

Bottomless™

CoolFET™

CROSSVOLT™

DOME™

EcoSPARK™

E2CMOS™

EnSigna™

FACT™

FACT Quiet Series™

FAST®

FASTr™

FRFET™

GlobalOptoisolator™

GTO™

HiSeC™

I2C™

ImpliedDisconnect™

ISOPLANAR™

LittleFET™

MicroFET™

MicroPak™

MICROWIRE™

MSX™

MSXPro™

OCX™

OCXPro™

OPTOLOGIC®

OPTOPLANAR™

PACMAN™

POP™

Power247™

PowerTrench®

QFET™

QS™

QT Optoelectronics™

Quiet Serie s™

RapidConfigure™

RapidConnect™

SILENT SWITCHER®

SMART START™

SPM™

Stealth™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

TinyLogic™

TruTranslation™

UHC™

UltraFET®

VCX™

Across the board. Around the world.™

The Power Franchise™

Programmable Active Droop™

Datasheet Identification Product Status Definition

Advance Inf ormation F ormative or In

Design This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semi conductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.