SEMICONDUCTOR
4-254
August 1997
HI-5701
6-Bit, 30 MSPS, Flash A/D Converter
Features
• 30 MSPS with No Missing Codes
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . 20MHz
• No Missing Codes Over Temperature
• Sample and Hold Not Required
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .+5V
• Power Dissipation (Max) . . . . . . . . . . . . . . . . . . .300mW
• CMOS/TTL Compatible
• Overflow Bit
• /883 Version Available
Applications
• Video Digitizing
• Radar Systems
• Communication Systems
• High Speed Data Acquisition Systems
Description
The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-to-
Digital Conver ter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 30 MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5701 delivers ±0.7 LSB
differential nonlinearity while consuming only 250mW (Typ)
at 30 MSPS. Microprocessor compatible data output latches
are provided which present valid data to the output bus 1.5
clock cycles after the convert command is received. An
overflow bit is provided to allow the series connection of two
converters to achieve 7-bit resolution.
The HI-5701 is available in Commercial and Industrial tem-
perature ranges and is supplied in 18 lead Plastic DIP and
SOIC packages.
Pinout
HI-5701
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HI3-5701K-5 0 to 70 18 Ld PDIP E18.3
HI9P5701K-5 0 to 70 18 Ld SOIC M18.3
HI3-5701B-9 -40 to 85 18 Ld PDIP E18.3
HI9P5701B-9 -40 to 85 18 Ld SOIC M18.3
HI5701-EV 25 Evaluation Board
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1D4
1/2R
D2
D1
D0 (LSB)
VDD
VIN
D3
VREF-
D5 (MSB)
OVF
VSS
NC
CE2
CE1
PHASE
CLK
VREF+
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997 File Number 2937.6
4-255
Functional Block Diagram
VIN
VREF+R/2
R
R
R
R
R/2
1/2R
VREF-
COMPARATOR
LATCHES
AND
63 TO 6
ENCODER
LOGIC
D
CL Q
D
CL Q
D
CL Q
D
CL Q
D
CL Q
D
CL Q
D
CL Q
OVERFLOW
(OVF)
D5 (MSB)
D4
D3
D2
D1
D0 (LSB)
CE1
CE2
φ2 (SAMPLE)
φ1 (AUTO BALANCE)
CLOCK
PHASE
VDD
VSS
φ2φ1φ1φ1φ2
COMP 64
COMP 63
COMP 32
COMP 2
COMP 1
R
R
HI-5701
4-256
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD to VSS. . . . . . . . . . . .(VSS - 0.5) < VDD < +7V
Analog and Reference Input Pins. . . . .(VSS - 0.5) < VINA < (VDD +0.5V)
Digital I/O Pins . . . . . . . . . . . . . . . (VSS - 0.5) < VI/O < (VDD +0.5V)
Operating Conditions
Operating Temperature Range
HI3-5701-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
HI9P5701-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum Power Dissipation at 70oC . . . . . . . . . . . . . . . . . . 635mW
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications VDD = +5.0V ; VREF+ = +4.0V; VREF- = VSS = GND; fS = Specified Cloc k Frequency at 50% Duty Cycle;
CL = 30pF; Unless Otherwise Specified
PARAMETER TEST CONDITIONS
25oC
(NOTE 2)
0oC TO 70oC
-40oC TO 85oC
UNITSMIN TYP MAX MIN MAX
SYSTEM PERFORMANCE
Resolution 6 - - 6 - Bits
Integral Linearity Error, INL
(Best Fit Line) fS = 20MHz - ±0.5 ±1.25 - ±2.0 LSB
fS = 30MHz - ±1.5 - - - LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes) fS = 20MHz - ±0.3 ±0.6 - ±0.75 LSB
fS = 30MHz - ±0.7 - - LSB
Offset Error, VOS
(Adjustable to Zero) fS = 20MHz (Note 2) - ±0.5 ±2.0 - ±2.5 LSB
fS = 30MHz - ±0.5 - - - LSB
Full Scale Error, FSE
(Adjustable to Zero) fS= 20MHz (Note 2) - ±0.25 ±2.0 - ±2.5 LSB
fS = 30MHz - ±0.25 - - - LSB
DYNAMIC CHARACTERISTICS
Maximum Conversion Rate No Missing Codes 30 40 - 30 - MSPS
Minimum Conversion Rate No Missing Codes (Note 2) - - 0.125 - 0.125 MSPS
Full Power Input Bandwidth fS = 30MHz - 20 - - - MHz
Signal to Noise Ratio, SNR fS = 1MHz, fIN = 100kHz - 36 - - - dB
fS = 30MHz, fIN = 4MHz - 31 - - - dB
Signal to Noise Ratio, SINAD fS = 1MHz, fIN = 100kHz - 35 - - - dB
fS = 30MHz, fIN = 4MHz - 30 - - - dB
Total Harmonic Distortion fS = 1MHz, fIN = 100kHz - -44 - - - dBc
fS= 30MHz, fIN = 4MHz - -38 - - - dBc
Differential Gain fS = 14.32MHz, fIN = 3.58MHz - 2 - - - %
Differential Phase fS = 14.32MHz, fIN = 3.58MHz - 2 - - - Degree
RMS Signal
RMS Noise
---------------------------------=
RMS Signal
RMS Noise + Distortion
--------------------------------------------------------------=
HI-5701
4-257
ANALOG INPUTS
Analog Input Resistance, RIN VIN = 4V - 30 - - - MΩ
Analog Input Capacitance, CIN VIN = 0V - 20 - - - pF
Analog Input Bias Current, IB VIN = 0V, 4V - 0.01 ±1.0 - ±1.0 µA
REFERENCE INPUTS
Total Reference Resistance, RL250 370 - 235 - Ω
Reference Resistance Tempco, TC- +0.266 - - - Ω/oC
DIGITAL INPUTS
Input Logic High Voltage, VIH 2.0 - - 2.0 - V
Input Logic Low Voltage, VIL - - 0.8 - 0.8 V
Input Logic High Current, IIH VIN = 5V - - 1.0 - 1.0 µA
Input Logic Low Current, IIL VIN = 0V - - 1.0 - 1.0 µA
Input Capacitance, CIN -7---pF
DIGITAL OUTPUTS
Output Logic Sink Current, IOL VO = 0.4V 3.2 - - 3.2 - mA
Output Logic Source Current, IOH VO = 4.5V -3.2 - - -3.2 - mA
Output Leakage, IOFF CE2 = 0V - - ±1.0 - ±1.0 µA
Output Capacitance, COUT CE2 = 0V - 5.0 - - - pF
TIMING CHARACTERISTICS
Aperture Delay, tAP -6---ns
Aperture Jitter, tAJ -30---ps
Data Output Enable Time, tEN (Note 2) - 12 20 - 20 ns
Data Output Disable Time, tDIS (Note 2) - 11 20 - 20 ns
Data Output Delay, tOD (Note 2) - 14 20 - 20 ns
Data Output Hold, tH(Note 2) 5 10 - 5 - ns
POWER SUPPLY REJECTION
Offset Error PSRR, ∆VOS VDD = 5V ±10% - ±0.1 ±1.0 - ±1.5 LSB
Gain Error PSRR, ∆FSE VDD = 5V ±10% - ±0.1 ±1.0 - ±1.5 LSB
POWER SUPPLY CURRENT
Supply Current, IDD fS = 30MHz - 50 60 - 75 mA
NOTES:
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Parameter guaranteed by design or characterization and not production tested.
Electrical Specifications VDD = +5.0V ; VREF+ = +4.0V; VREF- = VSS = GND; fS = Specified Cloc k Frequency at 50% Duty Cycle;
CL = 30pF; Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
25oC
(NOTE 2)
0oC TO 70oC
-40oC TO 85oC
UNITSMIN TYP MAX MIN MAX
HI-5701
4-258
Timing Waveforms
FIGURE 1. INPUT-TO-OUTPUT TIMING
FIGURE 2. OUTPUT ENABLE TIMING
N - 2
COMPARATOR DATA
IS LATCHED ENCODED DATA IS
LATCHED INTO THE
OUTPUT REGISTERS
tAP
tAJ tH
tOD
DATA N - 4 DATA N - 3 DATA N - 2 DATA N - 1 DATA N
CLOCK
INPUT
PHASE - HIGH
CLOCK
INPUT
PHASE - LOW
ANALOG
INPUT
DATA
OUTPUT
φ2φ2φ2φ2
φ1φ1φ1φ1
SAMPLE AUTO
BALANCE
tAB
SAMPLE
N - 1 AUTO
BALANCE
SAMPLE
NAUTO
BALANCE
SAMPLE
N + 1 AUTO
BALANCE
SAMPLE
N + 2
φ2
tS
CE1
CE2
D0 - D5
OVF
tDIS tEN tDIS tEN
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DATA
DATADATA
DATA DATA
HIGH
IMPEDANCE
HI-5701
4-259
Typical Performance Curves
FIGURE 3. EFFECTIVE NUMBER OF BITS vs fIN FIGURE 4. ENOB vs TEMPERATURE
FIGURE 5. SNR vs TEMPERATURE FIGURE 6. TOTAL HARMONIC DISTORTION vs TEMPERATURE
FIGURE 7. INL vs TEMPERATURE FIGURE 8. DNL vs TEMPERATURE
6
5
4
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT FREQUENCY (fIN)- MHz
EFFECTIVE BITS
VDD = 5V, VREF+ = 4V
TA = 25oC
fS = 20MHz
fS = 30MHz
fS = 40MHz
6
5
4
3
VDD = 5V, VREF+ = 4V
fS = 1MHz, fIN = 100kHz
fS = 30MHz, fIN = 4MHz
-40 -30 -20 -100 102030405060708090
EFFECTIVE BITS
TEMPERATURE (oC)
VDD = 5V, VREF+ = 4V
fS = 30MHz, fIN = 4MHz
fS = 1MHz, fIN = 100kHz
38
36
34
32
30
28
26
24 -40 -30 -20 -100 102030405060708090
dB
TEMPERATURE (oC)
fS = 30MHz, fIN = 4MHz
VDD = 5V, VREF+ = 4V
fS = 1MHz, fIN = 100kHz
-40 -30 -20 -100 102030405060708090
-34
-36
-38
-40
-42
-44
-46
dBc
TEMPERATURE (oC)
fS = 30MHz
fIN = 100kHz
VDD = 5V, VREF+ = 4V
2
1.5
1
0.5
0-40 -30 -20 -100 102030405060708090
TEMPERATURE (oC)
LSBs
fS = 1MHz
1
0.75
0.5
0.25
0
LSBs
TEMPERATURE (oC)
-40 -30 -20 -100 102030405060708090
f
S
= 30MHz
fS = 1MHz
fIN = 100kHz
VDD = 5V, VREF+ = 4V
HI-5701
4-260
FIGURE 9. POWER SUPPLY REJECTION vs TEMPERATURE FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
FIGURE 11. SUPPLY CURRENT vs CLOCK AND DUTY CYCLE FIGURE 12. EFFECTIVE NUMBER OF BITS vs CLOCK
FREQUENCY
Typical Performance Curves
(Continued)
PSRR FSE
PSRR VOS
1
0.5
0
-1-40 -30 -20 -100 102030405060708090
TEMPERATURE (oC)
LSBs
-0.5
VDD = 5V ±10%, VREF+ = 4V
-200 20406080100
TEMPERATURE (oC)
IDD (mA)
60
55
45
40
35
30
25
20
15
10
50
fS = 1MHz
-40
VDD = 5V, VREF+ = 4V
fS = 30MHz
60
55
45
40
35
30
25
20
15
10
50
0.1 1 10 100
CLOCK FREQUENCY (MHz)
IDD (mA)
VDD = 5V, VREF + = 4V
TA = 25oCD = 50%
D = 25%
D = 10%
DtAB
tAB tS
+
------------------------=
30 40 50 60
CLOCK FREQUENCY (MHz)
fI= 1MHz
1.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
EFFECTIVE BITS
HI-5701
4-261
Theory of Operation
The HI-5701 is a 6-bit analog-to-digital converter based on a
parallel CMOS “flash” architecture. This flash technique is an
extremely fast method of A/D conversion because all bit
decisions are made simultaneously. In all, 64 comparators
are used in the HI-5701; 63 comparators to encode the
output word, plus an additional comparator to detect an
overflow condition.
The CMOS HI-5701 works by alternately switching between
a “Sample” mode and an “Auto Balance” mode. Splitting up
the comparison process in this CMOS technique offers a
number of significant advantages. The offset voltage of each
CMOS comparator is dynamically canceled with each
conversion cycle such that offset voltage drift is virtually
eliminated during operation. The block diagram and timing
diagram illustrate how the HI-5701 CMOS flash converter
operates.
The input clock which controls the operation of the HI-5701
is first split into a non-inver ting φ1 clock and an inver ting φ2
clock. These two clocks, in turn, synchronize all internal
timing of analog switches and control logic within the
converter.
In the “Auto Balance” mode (φ1), all φ1 switches close and
φ2 switches open. The output of each comparator is
momentarily tied to its own input, self-biasing the comparator
midway between VSS and VDD and presenting a low
impedance to a small input capacitor. Each capacitor, in
turn, is connected to a reference voltage tap from the
resistor ladder. The Auto Balance mode quickly precharges
all 64 input capacitors between the self-bias voltage and
each respective tap voltage.
In the “Sample” mode (φ2), all φ1 switches open and φ2
switches close. This places each comparator in a sensitive
high gain amplifier configuration. In this open loop state, the
input impedance is very high and any small voltage shift at
the input will drive the output either high or low. The φ2 state
also switches each input capacitor from its reference tap to
the input signal. This instantly transfers any voltage
diff erence between the ref erence tap and input voltage to the
comparator input. All 64 comparators are thus driven
simultaneously to a defined logic state. For example, if the
input voltage is at mid-scale, capacitors precharged near
zero during φ1 will push comparator inputs higher than the
self bias voltage at φ2; capacitors precharged near the
reference voltage push the respective comparator inputs
lower than the bias point. In general, all capacitors
precharged by taps above the input voltage force a “low”
voltage at comparator inputs; those precharged below the
input voltage force “high” inputs at the comparators.
During the next φ1 state, comparator output data is
latched into the encoder logic block and the first stage of
encoding takes place. The following φ2 state completes
the encoding process. The 6 data bits (plus overflow bit)
are latched into the output flip-flops at the next falling
clock edge. The Overflow bit is set if the input voltage
exceeds VREF+-1
/
2
LSB. The output bus may be either
enabled or disabled according to the state of CE1 and
CE2 (See Table 2). When disabled, output bits assume a
high impedance state.
As shown in the timing diagram, the digital output word
becomes valid after the second φ1 state. There is thus a one
and a half cycle pipeline delay between input sample and
digital output. “Data Output Delay” time indicates the slight
time dela y f or data to become v alid at the end of the φ1 state .
Refer to the Glossary of Terms for other definitions.
TABLE 1. PIN DESCRIPTIONS
PIN # NAME DESCRIPTION
1 D5 Bit 6, Output (MSB).
2 OVF Overflow, Output.
3V
SS Digital Ground.
4 NC No Connection.
5 CE2 Three-State Output Enable Input, Active
High (See Table 2).
6CE1 Three-State Output Enable Input, Active
Low (See Table 2).
7 CLK Clock Input.
8 PHASE Sample Clock Phase Control Input.
When Phase is Low, Sample Unknown
(φ1) Occurs When the Clock is Low and
Auto Balance (φ2) Occurs When the
Clock is High (See Text).
9V
REF+ Reference Voltage Positive Input.
10 VREF- Reference Voltage Negative Input.
11 VIN Analog Signal Input.
12 VDD Power Supply, +5V.
13 D0 Bit 1, Output (LSB).
14 D1 Bit 2, Output.
15 D2 Bit 3, Output.
16 1/2 R2 Reference Ladder Midpoint.
17 D3 Bit 4, Output.
18 D4 Bit 5, Output.
TABLE 2. CHIP ENABLE TRUTH TABLE
CE1 CE2 D0 - D5 OVF
0 1 Valid Valid
1 1 Three-State Valid
X 0 Three-State Three-State
X = Don’t Care
HI-5701
4-262
Application Information
Voltage Reference
The ref erence voltage is applied across the resistor ladder at
the input of the converter, between VREF+ and VREF-. In
most applications, VREF- is simply tied to analog ground
such that the reference source drives VREF+. The reference
must be capable of supplying enough current to drive the
minimum ladder resistance of 235Ω over temperature.
The HI-5701 is specified for a reference voltage of 4.0V, but will
operate with voltages as high as the VDD supply. In the case of
4.0V reference operation, the converter encodes the analog
input into a binary output in LSB increments of
(VREF+-V
REF)/64, or 62.5mV. Reducing the reference voltage
reduces the LSB size proportionately and thus increases linearity
errors. The minimum practical reference voltage is about 2V.
Because the reference voltage terminals are subjected to inter-
nal transient currents during conversion, it is important to drive
the ref erence pins from a low impedance source and to decouple
thoroughly. Again, ceramic and tantalum (0.01µF and 10µF)
capacitors near the package pin are recommended. It is not nec-
essary to decouple the 1/2R tap point pin f or most applications.
It is possible to elevate VREF- from ground if necessary. In
this case, the VREF- pin must be driv en from a low impedance
reference capable of sinking the current through the resistor
ladder. Careful decoupling is again recommended.
Digital Control and Interface
The HI-5701 provides a standard high speed interface to
external CMOS and TTL logic families. Four digital inputs
are provided to control the function of the converter. The
clock and phase inputs control the sample and auto balance
modes. The digital outputs change state on the clock phase
which begins the sample mode. Two chip enable inputs
control the three-state outputs of output bits D0 through D5
and the Overflow OVF bit. As indicated in Table 2, all output
bits are high impedance when CE2 is low, and output bits D0
through D5 are independently controlled by CE1.
Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge
currents will produce supply and local ground disturbances.
Therefore, an external bus driver is recommended.
Clock
The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the
conversion frequency and controls the converter as
described in the “Theory of Operation” section. The Auto
Balance φ1 half cycle of the clock may be reduced to 16ns;
the Sample φ2 half cycle may be varied from a minimum of
16ns to a maximum of 8µs.
TABLE 3. PHASE CONTROL
Gain and Offset Adjustment
In applications where accuracy is of utmost importance,
three adjustments can be made; i.e., offset, gain, and
midpoint trim. In general, offset and gain correction can be
done in the preamp circuitry.
Offset Adjustment
The preferred offset correction method is to introduce a DC
component to VIN of the converter. An alternate method is to
adjust the VREF- input to produce the desired offset
adjustment. The theoretical input voltage to produce the first
transition is 1/2 LSB.
VIN (0 to 1 transition) = 1/2 LSB = 1/2(VREF/64) = VREF/128.
CLOCK
INPUT
+4V VREF+
PHASE
CLK
CE1
CE2
VSS
OVF
D5
+5V
10µF0.01µF
D4
D3
1/2R
D2
D1
D0
VDD
VIN
VREF-
NC
+5V
0.01µF10µF
+9V to +12V
0.01µF 10µF
ANALOG
SIGNAL
INPUT
50Ω
HA-5033
100Ω
0.01µF10µF
-9V to -12V
DATA
OUPUT
50Ω
FIGURE 13. TEST CIRCUIT
CLOCK PHASE INTERNAL GENERATION
0 0 Sample Unknown (φ2)
0 1 Auto Balance (φ1)
1 0 Auto Balance (φ1)
1 1 Sample Unknown (φ2)
HI-5701
4-263
Gain Adjustment
In general, full scale error correction can be done in the preamp
circuitry by adjusting the gain of the op amp. An alternate
method is to adjust the VREF+ input voltage . This adjustment is
performed by setting VIN to the 63 to overflow transition. The
theoretical input voltage to produce the transition is 1/2 LSB
less than VREF+ and is calculated as follo ws:
VIN (63 to 64 transition) = VREF - (VREF/128) = VREF(127/128).
To perform the gain trim, first do the offset trim and then
apply the required VIN for the 63 to overflow transition. Now
adjust VREF+ until that transition occurs on the outputs.
Midpoint Trim
The reference center (1/2R) is available to the user as the
midpoint of the resistor ladder. The 1/2R point can be used
to improve linearity or create unique transfer functions. The
offset and gain trims should be done prior to adjusting the
midpoint. The theoretical transition from count 31 to 32
occurs at 31.5 LSBs. That voltage is calculated as follows:
VIN (31 to 32 transition) = 31.5(VREF/64) = VREF(63/128).
An adjustable voltage follow er can be used to driv e the 1/2R
pin. Set VIN to the 31 to 32 transition v oltage, then adjust the
voltage follower until the transition occurs on the output bits.
Signal Source
A current pulse is present at the analog input (VIN) at the
beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch
feed through in the capacitor array. It varies with the
amplitude of the analog input and the sampling rate.
The signal source must be capable of recovering from the
transient prior to the end of the sample period to ensure a valid
signal for conversion. Suitable broad band amplifiers or buff ers
which exhibit low output impedance and high output drive
include the HFA-0005, HA-5004, HA-5002, and HA-5033.
The signal source may drive above or below the power
supply rails, but should not exceed 0.5V beyond the rails or
damage may occur. Input voltages of -0.5V to +1/2 LSB are
conver ted to all zeros; input voltages of VREF+ - 1/2 LSB to
VDD + 0.5 are conv erted to all ones with the Overflow bit set.
Power Supply
The HI-5701 operates nominally from a 5V supply, but will
function from 3V to 6V. The supply should be well regulated
and “clean” of significant noise, especially high frequency
noise. It is recommended that power supply decoupling
capacitors be placed as close to the supply pin as possible.
A combination of 0.01µF ceramic and 10µF tantalum
capacitors is recommended for this purpose as shown in the
test circuit Figure 13.
Reducing Power Consumption
Power dissipation in the HI-5701 is related to clock frequency
and clock duty cycle . F or a fixed 50% clock duty cycle, po wer
ma y be reduced by lowering the clock frequency. F or a given
conversion frequency, power may be reduced by shor tening
the Auto Balance φ1 portion of the clock duty cycle.
TABLE 3. OUTPUT CODE TABLE
† The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.
CODE
DESCRIPTION
INPUT VOLTAGE†
VREF+ = 4V
VREF- = 0V
(V) DECIMAL
COUNT
BINARY OUTPUT CODE
MSB LSB
OVF D5 D4 D3 D2 D1 D0
Overflow (OVF) 4.000 127 1111111
Full Scale (FS) 3.9063 63 0111111
FS - 1 LSB 3.8438
•
•
62 0111
•
•
•
110
3
/
4
FS 2.9688
•
•
•
48 0110
•
•
•
000
1
/
2
FS 1.9688
•
•
•
32 0100
•
•
•
000
1
/
4
FS 0.9688
•
•
•
16 0010
•
•
•
000
1 LSB 0.0313 1 0000001
Zero 0 0 0000000
HI-5701
4-264
Glossary of Terms
Aperture Delay, is the time delay between the external
sample command (the rising edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter, tAJ, This is the RMS variation in the
aperture delay due to variation of internal φ1 and φ2 clock
path delays and variation between the individual comparator
switching times.
Differential Linearity Error, DNL, The differential linearity
error is the difference in LSBs between the spacing of the
measured midpoint of adjacent codes and the spacing of
ideal midpoints of adjacent codes. The ideal spacing of each
midpoint is 1 LSB. The range of values possible is from
-1 LSB (which implies a missing code) to greater than
+1 LSB.
Full Power Input Bandwidth, Full power bandwidth is the
frequency at which the amplitude of the fundamental of the
digital output word has decreased 3dB below the amplitude of
an input sine wave. The input sine wave has a peak-to-peak
amplitude equal to the reference voltage. The bandwidth
given is measured at the specified sampling frequency.
Full Scale Error, FSE, is the difference between the actual
input voltage of the 63 to 64 code transition and the ideal
value of VREF+ - 1.5 LSB. This error is expressed in LSBs.
Integral Linearity Error, INL, The integral linearity error is
the difference in LSBs between the measured code centers
and the ideal code centers. The ideal code centers are
calculated using a best fit line through the converter’s
transfer function.
LSB, Least Significant Bit = (VREF+ - VREF -)/64. All
HI-5701 specifications are given for a 62.5mV LSB size
VREF+ = 4V, VREF- = 0V.
Offset Error, VOS,Offset error is the difference between
the actual input voltage of the 0 to 1 code transition and
the ideal value of VREF- + 0.5 LSB. VOS error is
expressed in LSBs.
Power Supply Rejection Ratio, PSRR, is expressed in
LSBs and is the maximum shift in code transition points
due to a power supply voltage shift. This is measured at
the 0 to 1 code transition point and the 62 to 63 code
transition point with a power supply voltage shift from the
nominal value of 5.0V.
Signal to Noise Ratio, SNR, SNR is the ratio in dB of the
RMS signal to RMS noise at specified input and sampling
frequencies.
Signal to Noise and Distortion Ratio, SINAD, is the ratio
in dB of the RMS signal to the RMS sum of the noise and
harmonic distortion at specified input and sampling
frequencies.
Total Harmonic Distortion, THD, is the ratio in dBc of the
RMS sum of the first five harmonic components to the RMS
signal for a specified input and sampling frequency.
HI-5701
4-265
Die Characteristics
DIE DIMENSIONS:
86.6 mils x 130.7 mils x 19 mils ±1 mil
METALLIZATION:
Type: SiAl
Thickness: 11kű1kÅ
PASSIVATION:
Type: SiO2
Thickness: 8kű1kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105 A/cm2
TRANSISTOR COUNT:
4000
SUBSTRATE POTENTIAL (Powered Up):
V+
Metallization Mask Layout
HI-5701
(3) VSS
(2) OVF
(1) D5
(18) D4
(17) D3
(16) 1/2 R
(15) D2
(14) D1
(13) D0
(12) VDD
CLK (7)
PHASE (8)
VREF+ (9)
VIN (11)
VDD (12)
VSS (3)
CE2 (5)
CE1 (6)
VREF- (10)
HI-5701
