256-Position I2C(R)-Compatible Digital Potentiometer AD5245 APPLICATIONS Mechanical potentiometer replacement in new designs LCD panel VCOM adjustment LCD panel brightness and contrast control Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment FUNCTIONAL BLOCK DIAGRAM VDD A SCL I2C INTERFACE SDA W AD0 WIPER REGISTER B POR 03436-001 256-position End-to-end resistance 5 k, 10 k, 50 k, 100 k Compact SOT-23-8 (2.9 mm x 3 mm) package Fast settling time: tS = 5 s typ on power-up Full read/write of wiper register Power-on preset to midscale Extra package address decode pin AD0 Computer software replaces C in factory programming applications Single supply: 2.7 V to 5.5 V Low temperature coefficient 45 ppm/C Low power: IDD = 8 A Wide operating temperature: -40C to +125C Evaluation board available GND Figure 1. PIN CONFIGURATION W 1 VDD 2 GND 3 SCL 4 8 AD5245 A B TOP VIEW 6 AD0 (Not to Scale) 5 SDA 7 03436-002 FEATURES Figure 2. GENERAL DESCRIPTION The AD5245 provides a compact 2.9 mm x 3 mm packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. Operating from a 2.7 V to 5.5 V power supply and consuming less than 8 A allows usage in portable battery-operated applications. Note that the terms digital potentiometer, VR, and RDAC are used interchangeably. The wiper settings are controllable through an I2C-compatible digital interface, which can also be used to read back the wiper register content. AD0 can be used to place up to two devices on the same bus. Command bits are available to reset the wiper position to midscale or to shut down the device into a state of zero power consumption. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. AD5245 TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits..................................................................................... 12 Applications....................................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagram .............................................................. 1 Programming the Variable Resistor......................................... 13 Pin Configuration............................................................................. 1 Programming the Potentiometer Divider............................... 14 General Description ......................................................................... 1 ESD Protection ........................................................................... 14 Revision History ............................................................................... 2 Terminal Voltage Operating Range ......................................... 14 Electrical Characteristics ................................................................. 3 Power-Up Sequence ................................................................... 14 5 k Version.................................................................................. 3 Layout and Power Supply Bypassing ....................................... 14 10 k, 50 k, 100 k Versions .................................................. 4 Constant Bias to Retain Resistance Setting............................. 15 Timing Characteristics..................................................................... 5 Evaluation Board ........................................................................ 15 5 k, 10 k, 50 k, 100 k Versions........................................ 5 I2C Interface .................................................................................... 16 Absolute Maximum Ratings............................................................ 6 I2C-Compatible 2-Wire Serial Bus ........................................... 16 ESD Caution.................................................................................. 6 Outline Dimensions ....................................................................... 19 Pin Configuration and Function Descriptions............................. 7 Ordering Guide .......................................................................... 19 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 1/06--Rev. A to Rev. B Changes to Table 3........................................................................... 5 Changes to Ordering Guide ......................................................... 19 3/04--Rev. 0 to Rev. A Updated Format................................................................ Universal Changes to Features......................................................................... 1 Changes to Applications ................................................................. 1 Changes to Figure 1......................................................................... 1 Changes to Electrical Characteristics--5 k Version ................ 3 Changes to Electrical Characteristics--10 k, 50 k, and 100 k Versions ....................................................................... 4 Changes to Timing Characteristics ............................................... 5 Changes to Absolute Maximum Ratings ...................................... 6 Moved ESD Caution to Page .......................................................... 6 Changes to Pin Configuration and Function Descriptions ....... 7 Changes to Figures 22 and 23 ...................................................... 11 Moved Figure 25 to Figure 26 ...................................................... 11 Moved Figure 26 to Figure 27 ...................................................... 11 Moved Figure 27 to Figure 25 ...................................................... 11 Deleted Figures 31 and 32 ............................................................ 12 Changes to Figure 32, Figure 33 and Figure 34 ......................... 12 Changes to Rheostat Operation Section..................................... 13 Added Figure 35............................................................................. 13 Changes to Equation 1 and Equation 2 ...................................... 13 Changes to Table 6 and Table 7.................................................... 13 Added Figure 37 ............................................................................ 14 Changes to Equation 4 .................................................................. 14 Deleted Readback RDAC Value Section .................................... 14 Deleted Level Shifting for Bidirectional Interface Section ...... 14 Moved ESD Protection Section to Page ..................................... 14 Changes to Figure 38 and Figure 39............................................ 14 Moved Terminal Voltage Operating Range Section to Page.... 14 Changes to Figure 40..................................................................... 14 Moved Power-Up Sequence Section to Page ............................. 14 Moved Layout and Power Supply Bypassing Section to Page . 15 Added Constant Bias to Retain Resistance Setting Section..... 15 Added Figure 42 ............................................................................ 15 Added Evaluation Board Section ................................................ 15 Added Figure 43 ............................................................................ 15 Moved I2C Interface Section to Page........................................... 16 Changes to I2C Compatible 2-Wire Serial Bus Section ........... 16 Moved Table 5 and Table 6 to Page ............................................. 17 (Renumbered as Table 8 and Table 9) Moved Figure 36, Figure 37, and Figure 38 to Page.................. 17 (Renumbered as Figure 44, Figure 45, and Figure 46) Moved Multiply Devices on One Bus Section to Page ............. 18 Updated Ordering Guide ............................................................. 19 Updated Outline Dimensions...................................................... 19 Moved I2C Disclaimer to Page ..................................................... 20 5/03--Revision 0: Initial Version Rev. B | Page 2 of 20 AD5245 ELECTRICAL CHARACTERISTICS 5 k VERSION VDD = 5 V 10% or 3 V 10%, VA = VDD, VB = 0 V, -40C < TA < +125C, unless otherwise noted. Table 1. Parameter Symbol Conditions DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect Nominal Resistor Tolerance3 RAB TA = 25C Resistance Temperature Coefficient (RAB/RAB)/T x 106 VAB = VDD, wiper = no connect Wiper Resistance RW DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Differential Nonlinearity4 DNL Integral Nonlinearity4 INL Voltage Divider Temperature Coefficient (VW/VW)/T x 106 Code = 0x80 Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA, VB, VW f = 1 MHz, measured to GND, Capacitance A, B6 CA, CB code = 0x80 f = 1 MHz, measured to GND, Capacitance W6 CW code = 0x80 Shutdown Supply Current7 IA_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V Input Logic Low VIL VDD = 5 V Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance6 CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = +5 V 10%, code = midscale DYNAMIC CHARACTERISTICS6, 9 Bandwidth -3 dB BW_5K RAB = 5 k, code = 0x80 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz VW Settling Time tS VA = 5 V, VB = 0 V, 1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 2.5 k, RS = 0 1 Min Typ1 Max Unit -1.5 -4 -30 0.1 0.75 +1.5 +4 +30 LSB LSB % ppm/C 45 50 -1.5 -1.5 -6 0 0.1 0.6 15 -2.5 2 GND 120 +1.5 +1.5 0 6 LSB LSB ppm/C LSB LSB VDD V 90 95 0.01 1 pF 1 2.4 0.8 2.1 0.6 1 5 2.7 3 0.02 5.5 8 44 0.05 1.2 0.1 1 6 Typical specifications represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 8 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use VDD = 5 V. 2 Rev. B | Page 3 of 20 pF A nA V V V V A pF V A W %/% MHz % s nV/Hz AD5245 10 k, 50 k, 100 k VERSIONS VDD = 5 V 10% or 3 V 10%, VA = VDD, VB = 0 V, -40C < TA < +125C, unless otherwise noted. Table 2. Parameter Symbol Conditions DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect Nominal Resistor Tolerance3 RAB TA = 25C Resistance Temperature Coefficient (RAB/RAB)/T x 106 VAB = VDD, wiper = no connect Wiper Resistance RW VDD = 5 V DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Differential Nonlinearity4 DNL Integral Nonlinearity4 INL Voltage Divider Temperature Coefficient (VW/VW)/T x 106 Code = 0x80 Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA, VB, VW Capacitance A, B6 CA, CB f = 1 MHz, measured to GND, code = 0x80 Capacitance W6 CW f = 1 MHz, measured to GND, code = 0x80 Shutdown Supply Current IA_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V Input Logic Low VIL VDD = 5 V Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V 6 Input Capacitance CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation7 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = 5 V 10%, code = midscale 6, 8 DYNAMIC CHARACTERISTICS Bandwidth -3 dB BW RAB = 10 k/50 k/100 k, code = 0x80 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VW Settling Time (10 k/50 k/100 k) tS VA = 5 V, VB = 0 V, 1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 5 k, RS = 0 1 Min Typ1 Max Unit -1 -2 -30 0.1 0.25 +1 +2 +30 LSB LSB % ppm/C 45 50 -1 -1 -3 0 0.1 0.3 15 -1 1 GND 120 +1 +1 0 3 VDD 90 V pF 95 pF 0.01 1 1 2.4 0.8 2.1 0.6 1 5 2.7 3 0.02 5.5 8 44 0.05 Rev. B | Page 4 of 20 A nA V V V V A pF V A W %/% 600/100/40 kHz 0.1 % 2 s 9 nV/Hz Typical specifications represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. 2 LSB LSB ppm/C LSB LSB AD5245 TIMING CHARACTERISTICS 5 K, 10 K, 50 K, 100 K VERSIONS VDD = 5 V 10% or 3 V 10%, VA = VDD, VB = 0 V, -40C < TA < +125C, unless otherwise noted. Table 3. Parameter Symbol Conditions I2C INTERFACE TIMING CHARACTERISTICS2, 3, 4 (Specifications Apply to All Parts) SCL Clock Frequency fSCL tBUF Bus Free Time Between STOP and START t1 tHD;STA Hold Time (Repeated START) t2 After this period, the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time for Repeated START Condition t5 tHD;DAT Data Hold Time t6 tSU;DAT Data Setup Time t7 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU;STO Setup Time for STOP Condition t10 1 Typical specifications represent average readings at 25C and VDD = 5 V. Guaranteed by design and not subject to production test. See timing diagram (Figure 44) for locations of measured values. 4 Standard I2C mode operation guaranteed by design. 2 3 Rev. B | Page 5 of 20 Min Typ1 Max Unit 400 kHz s s 1.3 0.6 1.3 0.6 0.6 0.9 100 300 300 0.6 s s s s ns ns ns s AD5245 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 4. Parameter VDD to GND VA, VB, VW to GND Terminal Current, A to B, A to W, B to W1 Pulsed Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance2 JA: SOT-23-8 Value -0.3 V to +7 V VDD 20 mA 5 mA 0 V to 7 V -40C to +125C 150C -65C to +150C 245C 230C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Maximum terminal current is bound by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 20 AD5245 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 3 SCL 4 8 AD5245 A B TOP VIEW 6 AD0 (Not to Scale) 5 SDA 7 03436-002 W 1 VDD 2 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic W VDD GND SCL SDA AD0 B A Description W Terminal. GND VW VDD. Positive Power Supply. Digital Ground. Serial Clock Input. Positive edge triggered. Pull-up resistor required. Serial Data Input/Output. Pull-up resistor required. Programmable Address Bit 0 for Two-Device Decoding. B Terminal. GND VB VDD. A Terminal. GND VA VDD. Rev. B | Page 7 of 20 AD5245 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 5V 0.8 -40C +25C +85C +125C 0.8 POTENTIOMETER MODE DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 03436-003 -0.8 0.6 0 96 128 160 192 224 256 Figure 7. DNL vs. Code vs. Temperature, VDD = 5 V 1.0 1.0 5V 3V 5V 3V 0.8 POTENTIOMETER MODE INL (LSB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 32 64 96 128 160 192 224 256 CODE (Decimal) -1.0 03436-004 -1.0 0 128 160 192 224 1.0 256 5V 0.8 POTENTIOMETER MODE DNL (LSB) 0.6 96 Figure 8. INL vs. Code vs. Supply Voltages -40C +25C +85C +125C 0.8 64 CODE (Decimal) Figure 5. R-DNL vs. Code vs. Supply Voltages 1.0 32 03436-007 RHEOSTAT MODE DNL (LSB) 64 CODE (Decimal) Figure 4. R-INL vs. Code vs. Supply Voltages 0.4 0.2 0 -0.2 -0.4 -0.6 3V 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.8 -1.0 0 32 64 96 128 160 192 224 CODE (Decimal) 256 03436-005 POTENTIOMETER MODE INL (LSB) 32 Figure 6. INL vs. Code vs. Temperature, VDD = 5 V -1.0 0 32 64 96 128 160 192 CODE (Decimal) Figure 9. DNL vs. Code vs. Supply Voltages Rev. B | Page 8 of 20 224 256 03436-008 RHEOSTAT MODE INL (LSB) 3V 0.6 03436-006 1.0 AD5245 1.0 0.6 2.0 ZSE, ZERO-SCALE ERROR (A) 0.8 RHEOSTAT MODE INL (LSB) 2.5 -40 C +25C +85C +125C 0.4 0.2 0 -0.2 -0.4 -0.6 1.5 VDD = 5.5V 1.0 VDD = 2.7V 0.5 0 32 64 96 128 160 192 224 0 -40 03436-009 -1.0 256 CODE (Decimal) 120 10 IDD SUPPLY CURRENT (A) RHEOSTAT MODE DNL (LSB) 0.6 80 Figure 13. Zero-Scale Error vs. Temperature -40C +25C +85C +125C 0.8 40 TEMPERATURE (C) Figure 10. R-INL vs. Code vs. Temperature, VDD = 5 V 1.0 0 03436-012 -0.8 0.4 0.2 0 -0.2 -0.4 -0.6 VDD = 5.5V 1 VDD = 2.7V 0 32 64 96 128 160 192 224 03436-010 -1.0 256 CODE (Decimal) 0.1 -40 40 80 120 TEMPERATURE (C) Figure 11. R-DNL vs. Code vs. Temperature, VDD = 5 V Figure 14. Supply Current vs. Temperature 2.5 70 60 IA SHUTDOWN CURRENT (nA) 2.0 VDD = 2.7V 1.5 VDD = 5.5V 1.0 0.5 50 40 30 VDD = 5V 20 0 40 80 TEMPERATURE (C) 120 Figure 12. Full-Scale Error vs. Temperature 0 -40 0 40 80 TEMPERATURE (C) Figure 15. Shutdown Current vs. Temperature Rev. B | Page 9 of 20 120 03436-014 10 0 -40 03436-011 FSE, FULL-SCALE ERROR (LSB) 0 03436-013 -0.8 AD5245 REF LEVEL 0.000dB 0 0x40 -12 0x20 -18 100 0x10 -24 0x08 -30 50 MARKER 510 634.725Hz MAG (A/R) -9.049dB 0x80 -6 150 0x04 -36 0x02 0x01 -42 0 -48 32 64 96 128 160 192 224 03436-015 0 256 CODE (Decimal) -60 1k START 1 000.000Hz Figure 16. Rheostat Mode Tempco RWB/T vs. Code 10k 100k 1M STOP 1 000 000.000Hz 03436-018 -54 -50 Figure 19. Gain vs. Frequency vs. Code, RAB = 10 k REF LEVEL 0.000dB 0 160 /DIV 6.000dB 140 0x80 -6 120 0x40 -12 100 0x20 -18 80 -24 60 -30 40 -36 20 -42 MARKER 100 885.289Hz MAG (A/R) -9.014dB 0x10 0x08 0x04 0x02 0x01 -48 0 -54 0 32 64 96 128 160 192 224 03436-016 -20 256 CODE (Decimal) -60 1k START 1 000.000Hz /DIV 6.000dB REF LEVEL 0.000dB 0 MARKER 1 000 000.000Hz MAG (A/R) -8.918dB -18 -24 -30 0x20 -18 0x10 -24 0x08 -30 0x04 0x40 0x20 0x10 0x08 0x04 -36 0x02 0x01 -36 0x02 -42 -42 0x01 -48 -48 MARKER 54 089.173Hz MAG (A/R) -9.052dB 0x80 -12 0x40 -12 /DIV 6.000dB -6 0x80 -6 100k 1M STOP 1 000 000.000Hz Figure 20. Gain vs. Frequency vs. Code, RAB = 50 k Figure 17. Potentiometer Mode Tempco VWB/T vs. Code REF LEVEL 0.000dB 0 10k 03436-019 POTENTIOMETER MODE TEMPCO (ppm/C) /DIV 6.000dB -54 -54 1k START 1 000.000Hz 10k 100k 1M STOP 1 000 000.000Hz 03436-017 -60 -60 1k START 1 000.000Hz 10k 100k 1M STOP 1 000 000.000Hz Figure 21. Gain vs. Frequency vs. Code, RAB = 100 k Figure 18. Gain vs. Frequency vs. Code, RAB = 5 k Rev. B | Page 10 of 20 03436-020 RHEOSTAT MODE TEMPCO (ppm/C) 200 AD5245 REF LEVEL -5.000dB /DIV 0.500dB -5.5 5k - 1.026MHz 10k - 511kHz 50k - 101kHz 100k - 54kHz -6.0 -6.5 -7.0 -7.5 -8.0 1 -8.5 R = 50k VW R = 5k -9.0 SCL R = 10k R = 100k 2 03436-024 -9.5 -10.0 100k 1M START 1 000.000Hz 10M STOP 1 000 000.000Hz Figure 22. -3 dB Bandwidth @ Code = 0x80 60 Ch 2 5.00 V BW M 100ns A CH2 3.00 V 03436-021 Ch 1 200mV BW -10.5 10k Figure 25. Large Signal Settling Time, Code 0xFF 0x00 CODE = 0x80, VA= VDD, VB = 0V VA = 5V VB = 0V PSRR (-dB) 40 PSRR @ VDD = 3V DC 10% p-p AC 1 VW 20 SCL 2 1k 10k 100k 1M FREQUENCY (Hz) Ch 1 100mV BW 03436-022 0 100 Ch 2 5.00 V BW M 200ns A CH1 152mV Figure 26. Digital Feedthrough Figure 23. PSRR vs. Frequency 900 03436-025 PSRR @ VDD = 5V DC 10% p-p AC VDD = 5V 800 VA = 5V VB = 0V 700 500 1 CODE = 0x55 400 VW 300 CODE = 0xFF SCL 200 0 10k 100k 1M FREQUENCY (Hz) 10M Ch 1 5.00V BW Ch 2 5.00 V BW M 200ns A CH1 3.00 V Figure 27. Midscale Glitch, Code 0x80 0x7F Figure 24. IDD vs. Frequency Rev. B | Page 11 of 20 03436-026 2 100 03436-023 IDD (A) 600 AD5245 TEST CIRCUITS Figure 28 to Figure 34 illustrate the test circuits that define the test conditions used in the product specification tables (Table 1 through Table 3). V+ = VDD 1LSB = V+/2N DUT W VOUT B OFFSET GND -15V 2.5V Figure 32. Test Circuit for Gain vs. Frequency NO CONNECT DUT B 0.1V ISW 03436-028 VMS 0.1V ISW CODE = 0x00 W B GND TO VDD Figure 29. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 33. Test Circuit for Incremental On Resistance NC IW = VDD/RNOMINAL DUT VW A VDD VMS1 RW = [VMS1 - VMS2]/IW GND 03436-029 B W ICM B NC VCM NC = NO CONNECT 03436-033 DUT W RSW = DUT IW A W 03436-031 VMS Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) VMS2 AD8610 VIN B A +15V W 03436-032 V+ DUT A 03436-027 A Figure 34. Test Circuit for Common-Mode Leakage Current Figure 30. Test Circuit for Wiper Resistance VA V+ = VDD 10% A V+ B W PSS (%/%) = VMS V (VMS ) DD VMS% VDD % 03436-030 VDD PSRR (dB) = 20 log Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Rev. B | Page 12 of 20 AD5245 THEORY OF OPERATION The general equation determining the digitally programmed output resistance between W and B is The AD5245 is a 256-position digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminals A and B is available in 5 k, 10 k, 50 k, and 100 k. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. 03436-034 B B B Figure 35. Rheostat Mode Configuration Assuming that a 10 k part is used, the wiper's first connection starts at the B terminal for Data 0x00. Because there is a 50 wiper contact resistance, such a connection yields a minimum of 100 (2 x 50 ) resistance between Terminals W and B. The second connection is the first tap point, which corresponds to 139 (RWB = RAB/256 + 2 x RW = 39 + 2 x 50 ) for Data 0x01. The third connection is the next tap point, representing 178 (2 x 39 + 2 x 50 ) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 (RAB + 2 x RW). A RS D7 D6 D5 D4 D3 D2 D1 D0 (1) where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 10 k and the A terminal is open circuited, then the following output resistance RWB is set for the indicated RDAC latch codes. D (Dec.) 255 128 1 0 W W W D x R AB + 2 x RW 256 Table 6. Codes and Corresponding RWB Resistance A A A RWB (D) = RWB () 9,961 5,060 139 100 Output State Full Scale (RAB - 1 LSB + RW) Midscale 1 LSB Zero Scale (Wiper Contact Resistance) Note that in the zero-scale condition, a finite wiper resistance of 100 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is RWA (D) = RS 256 - D x R AB + 2 x RW 256 (2) For RAB = 10 k and the B terminal open circuited, the following output resistance RWA is set for the indicated RDAC latch codes. RS W Table 7. Codes and Corresponding RWA Resistance RDAC RS B 03436-035 LATCH AND DECODER Figure 36. AD5245 Equivalent RDAC Circuit D (Dec.) 255 128 1 0 RWA () 139 5,060 9,961 10,060 Output State Full Scale Midscale 1 LSB Zero Scale Typical device-to-device matching is process lot dependent and can vary by up to 30%. Because the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 45 ppm/C temperature coefficient. Rev. B | Page 13 of 20 AD5245 PROGRAMMING THE POTENTIOMETER DIVIDER TERMINAL VOLTAGE OPERATING RANGE Voltage Output Operation The AD5245 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminals A, B, and W that exceed VDD or GND are clamped by the internal forward-biased diodes (see Figure 40). The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A to B. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. VDD A W A B VO 03436-036 W B GND 03436-039 VI Figure 40. Maximum Terminal Voltages Set by VDD and GND Figure 37. Potentiometer Mode Configuration POWER-UP SEQUENCE If ignoring the effect of the wiper resistance for approximation, then connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A and B divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminals A and B is VW (D) = D 256 - D VA + VB 256 256 (3) LAYOUT AND POWER SUPPLY BYPASSING A more accurate calculation, which includes the effect of wiper resistance, VW, is VW (D) = R (D) RWB (D) V A + WA VB R AB R AB (4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, not the absolute values. Therefore, the temperature drift reduces to 15 ppm/C. ESD PROTECTION All digital inputs are protected with a series of input resistors and parallel Zener ESD structures, shown in Figure 38 and Figure 39. This applies to the digital input pins SDA, SCL, and AD0. GND It is good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disk or chip ceramic capacitors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 41). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. VDD LOGIC 03436-037 340 Because the ESD protection diodes limit the voltage compliance at Terminals A, B, and W (see Figure 40), it is important to power VDD and GND before applying any voltage to Terminals A, B, and W; otherwise, the diode is forward biased such that VDD is powered unintentionally and can affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA, VB, and VW. The relative order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD and GND. C3 10F + C1 0.1F VDD AD5245 Figure 38. ESD Protection of Digital Pins GND 03436-038 GND 03436-040 A, B, W Figure 41. Power Supply Bypassing Figure 39. ESD Protection of Resistor Terminals Rev. B | Page 14 of 20 AD5245 CONSTANT BIAS TO RETAIN RESISTANCE SETTING For users who desire nonvolatility but cannot justify the additional cost for the EEMEM, the AD5245 can be considered a low cost alternative by maintaining a constant bias to retain the wiper setting. The AD5245 is designed specifically with low power in mind, which allows low power consumption even in battery-operated systems. Figure 42 demonstrates the power consumption from a 3.4 V, 450 mA-hr Li-Ion cell phone battery that is connected to the AD5245. The measurement over time shows that the device draws approximately 1.3 A and consumes negligible power. Over a course of 30 days, the battery is depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. 110% Although the resistance setting of the AD5245 is lost when the battery needs replacement, such events occur rather infrequently so that this inconvenience is justified by the lower cost and smaller size offered by the AD5245. If total power is lost, then the user should be provided with a means to adjust the setting accordingly. EVALUATION BOARD An evaluation board, along with all necessary software, is available to program the AD5245 from any PC running Windows(R) 98/2000/XP. The graphical user interface, as shown in Figure 43, is straightforward and easy to use. More detailed information is available in the user manual, which is provided with the board. TA = 25C 108% 104% 102% 100% 98% 96% 03436-042 BATTERY LIFE DEPLETED 106% 94% 92% Figure 43. AD5245 Evaluation Board Software 0 5 10 15 DAYS 20 25 30 03436-041 90% Figure 42. Battery Operating Life Depletion This demonstrates that constantly biasing the potentiometer can be a practical approach. Most portable devices do not require the removal of batteries for charging. The AD5245 starts at midscale upon power-up. To increment or decrement the resistance, the user can simply move the scrollbars on the left. To write a specific value, the user should use the bit pattern in the upper screen and click the Run button. The format of writing data to the device is shown in Table 8. To read the data from the device, the user can simply click the Read button. The format of the read bits is shown in Table 9. Rev. B | Page 15 of 20 AD5245 I2C INTERFACE I2C-COMPATIBLE 2-WIRE SERIAL BUS The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 45). The next byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data is read from or written to the slave device). The AD5245 has one configurable address bit, AD0 (see Table 8). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master reads from the slave device. On the other hand, if the R/W bit is low, the master writes to the slave device. 2. In write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is a don't care. The second MSB, RS, is the midscale reset. A logic high on this bit moves the wiper to the center tap, where RWA = RWB. This feature effectively overwrites the contents of the register; therefore, when taken out of reset mode, the RDAC remains at midscale. The third MSB, SD, is a shutdown bit. A logic high causes an open circuit at Terminal A while shorting the wiper to Terminal B. This operation yields almost 0 in rheostat mode or 0 V in potentiometer mode. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting is applied to the RDAC. Also during shutdown, new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting is applied to the RDAC. 3. After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 45). 4. In read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with write mode, in which eight data bits are followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 46). 5. After all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a STOP condition (see Figure 45). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, which goes high to establish a STOP condition (see Figure 46). A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in the write mode, the RDAC output updates on each successive byte. If different instructions are needed, then the write/read mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed. The remainder of the bits in the instruction byte are don't cares (see Table 8). Rev. B | Page 16 of 20 AD5245 Table 8. Write Mode S 0 1 0 1 1 0 AD0 A W X RS SD Slave Address Byte X X X X X A D7 D6 D5 D4 Instruction Byte D3 D2 D1 D0 A P Data Byte Table 9. Read Mode 0 1 0 1 1 0 AD0 Slave Address Byte R A D7 D6 D5 S = START condition P = STOP condition A = Acknowledge X = Don't care W = Write D4 D3 Data Byte D2 D1 D0 A P R = Read RS = Reset wiper to midscale 0x80 SD = Shutdown connects wiper to B terminal and open circuits A terminal, but does not change contents of wiper register D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits t8 t2 t9 SCL t6 t2 t3 t7 t4 t10 t5 t9 t8 SDA P S S 03436-043 t1 P Figure 44. I2C Interface Detailed Timing Diagram 1 9 9 1 1 9 SCL 0 1 1 0 1 0 X AD0 R/W RS SD X X X X X ACK BY AD5245 START BY MASTER D7 D6 D5 D4 D3 D2 D1 D0 ACK BY AD5245 FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE FRAME 3 DATA BYTE ACK BY AD5245 STOP BY MASTER Figure 45. Writing to the RDAC Register 1 9 1 9 SCL SDA START BY MASTER 0 1 0 1 1 0 FRAME 1 SLAVE ADDRESS BYTE AD0 D7 R/W D6 ACK BY AD5245 D5 D4 D3 D2 D1 FRAME 2 RDAC REGISTER Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode Rev. B | Page 17 of 20 D0 NO ACK BY MASTER STOP BY MASTER 03436-044 SDA 03436-045 S AD5245 +5V Multiple Devices on One Bus RP RP SDA MASTER SCL +5V SDA SCL SDA SCL AD0 AD0 AD5245 AD5245 Figure 47. Multiple AD5245 Devices on One I2C Bus Rev. B | Page 18 of 20 03436-046 Figure 47 shows two AD5245 devices on the same serial bus. Each has a different slave address because the states of their AD0 pins are different. This allows the RDAC within each device to be written to or read from independently. The master device's output bus line drivers are open-drain pull-downs in a fully I2C-compatible interface. AD5245 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 1.45 MAX 0.15 MAX 0.38 0.22 0.22 0.08 8 4 0 SEATING PLANE 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 48. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model AD5245BRJ5-R2 AD5245BRJ5-RL7 AD5245BRJZ5-R21 AD5245BRJZ5-RL71 AD5245BRJ10-R2 AD5245BRJ10-RL7 AD5245BRJZ10-R21 AD5245BRJZ10-RL71 AD5245BRJ50-R2 AD5245BRJ50-RL7 AD5245BRJZ50-R21 AD5245BRJZ50-RL71 AD5245BRJ100-R2 AD5245BRJ100-RL7 AD5245BRJZ100-R21 AD5245BRJZ100-RL71 AD5245EVAL2 1 2 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 Evaluation Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 Branding D0G D0G D0G D0G D0H D0H D0H D0H D0J D0J D0J D0J D0K D0K D0K D0K RAB () 5k 5k 5k 5k 10 k 10 k 10 k 10 k 50 k 50 k 50 k 50 k 100 k 100 k 100 k 100 k Z = Pb-free part. The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options. Rev. B | Page 19 of 20 Ordering Quantity 250 3,000 250 3,000 250 3,000 250 3,000 250 3,000 250 3,000 250 3,000 250 3,000 AD5245 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03436-0-1/06(B) Rev. B | Page 20 of 20