PIC16LF648A-I/P - MICROCHIP TECHNOLOGY

PIC16F627A/628A/648A

Data Sheet

Flash-Based, 8-Bit CMOS

Microcontrollers with nanoWatt Technology

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Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

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SQTP is a service mark of Microchip Technology Incorporated

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Note the following details of the code protection feature on Microch ip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

PIC16F627A/628A/648A

High-Performance RISC CPU:

• Operating speeds from DC – 20 MHz

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

• 35 single-word instructions:

- All instructions single cycle except branches

S pecial Microcontroller Features:

• Internal and external oscillator options:

- Precision internal 4 MHz oscillator factory

calibrated to ±1%

- Low-power internal 48 kHz oscillator

- External Oscillator support for crystals and

resonators

• Power-saving Sleep mode

• Programmable weak pull-ups on PORTB

• Multiplexed Master Clear/Input-pin

• Watchdog Timer with independent oscillator for

reliable operation

• Low-voltage programming

• In-Circuit Serial Programming™ (via two pins)

• Programmable code protection

• Brown-out Reset

• Power-on Reset

• Power-up Timer and Oscillator Start-up Timer

• Wide operating voltage range (2.0-5.5V)

• Industrial and extended temperature range

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- 40 year data retention

Low-Power Features:

• Standby Current:

- 100 nA @ 2.0V, typical

• Operating Current:

-12μA @ 32 kHz, 2.0V, typical

-120μA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

• Timer1 Oscillator Current:

-1.2μA @ 32 kHz, 2.0V, typical

• Dual-speed Internal Oscillator:

- Run-time selectable between 4 MHz and

48 kHz

-4μs wake-up from Sleep, 3.0V, typical

Peripheral Feat ures:

• 16 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

(VREF) module

- Selectable internal or external reference

- Comparator outputs are externally accessible

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

• Timer1: 16-bit timer/counter with external crystal/

clock capability

• Timer2: 8-bit timer/counter with 8-bit period

• Capture, Compare, PWM module:

- 16-bit Capture/Compare

-10-bit PWM

• Addressable Universal Synchronous/Asynchronous

Receiver/Transmitter USART/SCI

Device

Program

Memory Data Memory I/O CCP

(PWM) USART Comparators Timers

8/16-bit

Flash

(words) SRAM

(bytes) EEPROM

(bytes)

PIC16F627A 1024 224 128 16 1 Y 2 2/1

PIC16F628A 2048 224 128 16 1 Y 2 2/1

PIC16F648A 4096 256 256 16 1 Y 2 2/1

18-pin Flash-Based, 8-Bit CMOS Microcontrollers

with nanoWatt Technology

PIC16F627A/628A/648A

Pin Diagrams

PDIP, SOIC

SSOP

27A/628A/648A

RA6/OSC2/CLKOUT

RA7/OSC1/CLKIN

VSS

VDD

RA1/AN1

RA0/AN0

RB6/T1OSO/T1CKI/PGC

RB7/T1OSI/PGD

RB1/RX/DT

RB2/TX/CK

RB3/CCP1 RB4/PGM

RB5

RA3/AN3/CMP1

RA4/T0CKI/CMP2

RA5/MCLR/VPP

RB0/INT

RA2/AN2/VREF

VSS

RB1/RX/DT

RB2/TX/CK

RB3/CCP1

RA3/AN3/CMP1

RA4/T0CKI/CMP2

RA5/MCLR/VPP

RB0/INT

RA2/AN2/VREF

RA6/OSC2/CLKOUT

RA7/OSC1/CLKIN

VDD

RA1/AN1

RA0/AN0

RB6/T1OSO/T1CKI/PGC

RB7/T1OSI/PGD

RB4/PGM

RB5

PIC16F627A/628A/648A

RA2/AN2/VREF

RA3/AN3/CMP1

RA4/T0CKI/CMP2

RA5/MCLR/VPP

VSS

RB0/INT

RB1/RX/DT

RB2/TX/CK

RB3/CCP1

RA1/AN1

RA0/AN0

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

RB7/T1OSI/PGD

RB6/T1OSO/T1CKI/PGC

RB5

VDD

RB4/PGM

VSS

VDD

PIC16F627A/628A

PIC16F648A

28-Pin

QFN

118

PIC16F627A/628A/648A

Table of Contents

1.0 General Description ........................................................................................................................................................................ 7

2.0 PIC16F627A/628A/648A Device Varieties...................................................................................................................................... 9

3.0 Architectural Overview .................................................................................................................................................................. 11

4.0 Memory Organization .................................................................................................................................................................... 17

5.0 I/O Ports........................................................................................................................................................................................ 33

6.0 Timer0 Module .............................................................................................................................................................................. 47

7.0 Timer1 Module .............................................................................................................................................................................. 50

8.0 Timer2 Module .............................................................................................................................................................................. 54

9.0 Capture/Compare/PWM (CCP) Module........................................................................................................................................ 57

10.0 Comparator Module .................................................................................................................................................................... 63

11.0 Voltage Reference Module ......................................................................................................................................................... 69

12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module......................................................................... 73

13.0 Data EEPROM Memory .............................................................................................................................................................. 91

14.0 Special Features of the CPU ...................................................................................................................................................... 97

15.0 Instruction Set Summary........................................................................................................................................................... 117

16.0 Development Support ............................................................................................................................................................... 131

17.0 Electrical Specifications ............................................................................................................................................................ 135

18.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 151

19.0 Packaging Information .............................................................................................................................................................. 163

Appendix A: Data Sheet Revision History......................................................................................................................................... 171

Appendix B: Device Differences ....................................................................................................................................................... 171

Appendix C: Device Migrations......................................................................................................................................................... 172

Appendix D: Migrating from other PIC® Devices .............................................................................................................................. 172

The Microchip Web Site .................................................................................................................................................................... 173

Customer Change Notification Service ............................................................................................................................................. 173

Customer Support ............................................................................................................................................................................. 173

Reader Response ............................................................................................................................................................................. 174

Product Identification System ........................................................................................................................................................... 179

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Most Current Data Sheet

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Customer No tific atio n Syst em

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

1.0 GENERAL DESCRIP T ION

The PIC16F627A/628A/648A are 18-pin Flash-based

members of the versatile PIC16F627A/628A/648A

family of low-cost, high-performance, CMOS, fully-

static, 8-bit microcontrollers.

All PIC® microcontrollers employ an advanced RISC

architecture. The PIC16F627A/628A/648A have

enhanced core features, an eight-level deep stack, and

multiple internal and external interrupt sources. The

separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

the separate 8-bit wide data. The two-stage instruction

pipeline allows all instructions to execute in a single-

cycle, except for program branches (which require two

cycles). A total of 35 instructions (reduced instruction

set) are available, complemented by a large register

set.

PIC16F627A/628A/648A microcontrollers typically

achieve a 2:1 code compression and a 4:1 speed

improvement over other 8-bit microcontrollers in their

class.

PIC16F627A/628A/648A devices have integrated

features to reduce external components, thus reducing

system cost, enhancing system reliability and reducing

power consumption.

The PIC16F627A/628A/648A has 8 oscillator

configurations. The single-pin RC oscillator provides a

low-cost solution. The LP oscillator minimizes power

consumption, XT is a standard crystal, and INTOSC is

a self-contained precision two-speed internal oscillator.

The HS mode is for High-Speed crystals. The EC mode

is for an external clock source.

The Sleep (Power-down) mode offers power savings.

Users can wake-up the chip from Sleep through several

external interrupts, internal interrupts and Resets.

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software lock-

up.

Table 1-1 shows the features of the PIC16F627A/628A/

648A mid-range microcontroller family.

A simplified block diagram of the PIC16F627A/628A/

648A is shown in Figure 3-1.

The PIC16F627A/628A/648A series fits in applications

ranging from battery chargers to low power remote

sensors. The Flash technology makes customizing

application programs (detection levels, pulse genera-

tion, timers, etc.) extremely fast and convenient. The

small footprint packages makes this microcontroller

series ideal for all applications with space limitations.

Low cost, low power, high performance, ease of use

and I/O flexibility make the PIC16F627A/628A/648A

very versatile.

1.1 Development Support

The PIC16F627A/628A/648A family is supported by a

full-featured macro assembler, a software simulator, an

in-circuit emulator, a low cost in-circuit debugger, a low

cost development programmer and a full-featured

programmer. A Third Party “C” compiler support tool is

also available.

TABLE 1-1: PIC16F627A/628A/648A FAMILY OF DEVICES

PIC16F627A PIC16F628A PIC16F648A PIC16LF627A PIC16LF628A PIC16LF648A

Clock Maximum Frequency

of Operation (MHz)

20 20 20 20 20 20

Flash Program

Memory (words)

1024 2048 4096 1024 2048 4096

Memory RAM Data Memory

(bytes)

224 224 256 224 224 256

EEPROM Data

Memory (bytes)

128 128 256 128 128 256

Timer module(s) TMR0, TMR1,

TMR2

TMR0, TMR1,

TMR2

TMR0, TMR1,

TMR2

TMR0, TMR1,

TMR2

TMR0, TMR1,

TMR2

TMR0, TMR1,

TMR2

Comparator(s) 222222

Peripherals Capture/Compare/

PWM modules

111111

Serial Communications USART USART USART USART USART USART

Internal Voltage

Reference

Yes Yes Ye s Yes Yes Ye s

Interrupt Sources101010101010

I/O Pins 16 16 16 16 16 16

Features Voltage Range (Volts) 3.0-5.5 3.0-5.5 3.0-5.5 2.0-5.5 2.0-5.5 2.0-5.5

Brown-out Reset Yes Yes Yes Yes Yes Yes

Packages 18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

All PIC® family devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect and high I/O current capability.

All PIC16F627A/628A/648A family devices use serial programming with clock pin RB6 and data pin RB7.

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

2.0 PIC16F627A/628A/648A

DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements, the proper device option can be selected

using the information in the PIC16F627A/628A/648A

Product Identification System, at the end of this data

sheet. When placing orders, please use this page of

the data sheet to specify the correct part number.

2.1 Flash Devices

Flash devices can be erased and re-programmed

electrically. This allows the same device to be used for

prototype development, pilot programs and production.

A further advantage of the electrically erasable Flash is

that it can be erased and reprogrammed in-circuit, or by

device programmers, such as Microchip’s PICSTART®

Plus or PRO MATE® II programmers.

2.2 Quick-Turnaround-Production

(QTP) Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who chose not to program a medium

to high quantity of units and whose code patterns have

stabilized. The devices are standard Flash devices, but

with all program locations and configuration options

already programmed by the factory. Certain code and

prototype verification procedures apply before

production shipments are available. Please contact

your Microchip Technology sales office for more

details.

2.3 Serialized Quick-Turnaround-

Production (SQTPSM) Devices

Microchip offers a unique programming service where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number, which can serve as an entry-code,

password or ID number.

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16F627A/628A/648A

family can be attributed to a number of architectural

features commonly found in RISC microprocessors. To

begin with, the PIC16F627A/628A/648A uses a

Harvard architecture in which program and data are

accessed from separate memories using separate

busses. This improves bandwidth over traditional Von

Neumann architecture where program and data are

fetched from the same memory. Separating program

and data memory further allows instructions to be sized

differently than 8-bit wide data word. Instruction

opcodes are 14-bits wide making it possible to have all

single-word instructions. A 14-bit wide program mem-

ory access bus fetches a 14-bit instruction in a single

cycle. A two-stage pipeline overlaps fetch and execu-

tion of instructions. Consequently, all instructions (35)

execute in a single-cycle (200 ns @ 20 MHz) except for

program branches.

Table 3-1 lists device memory sizes (Flash, Data and

EEPROM).

TABLE 3-1: DEVICE MEMORY LIST

The PIC16F627A/628A/648A can directly or indirectly

address its register files or data memory. All Special

Function Registers (SFR), including the program

counter, are mapped in the data memory. The

PIC16F627A/628A/648A have an orthogonal (symmet-

rical) instruction set that makes it possible to carry out

any operation, on any register, using any addressing

mode. This symmetrical nature and lack of ‘special

optimal situations’ makes programming with the

PIC16F627A/628A/648A simple yet efficient. In

addition, the learning curve is reduced significantly.

The PIC16F627A/628A/648A devices contain an 8-bit

ALU and working register. The ALU is a general

purpose arithmetic unit. It performs arithmetic and

Boolean functions between data in the working register

and any register file.

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two’s

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register). The other operand is a file register or an

immediate constant. In single operand instructions, the

operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the Status Register. The C and DC bits

operate as Borrow and Digit Borrow out bits,

respectively, in subtraction. See the SUBLW and SUBWF

instructions for examples.

A simplified block diagram is shown in Figure 3-1, and

a description of the device pins in Table 3-2.

Two types of data memory are provided on the

PIC16F627A/628A/648A devices. Nonvolatile

EEPROM data memory is provided for long term

storage of data, such as calibration values, look-up

table data, and any other data which may require

periodic updating in the field. These data types are not

lost when power is removed. The other data memory

provided is regular RAM data memory. Regular RAM

data memory is provided for temporary storage of data

during normal operation. Data is lost when power is

removed.

Device

Memory

Flash

Program RAM

Data EEPROM

Data

PIC16F627A 1024 x 14 224 x 8 128 x 8

PIC16F628A 2048 x 14 224 x 8 128 x 8

PIC16F648A 4096 x 14 256 x 8 256 x 8

PIC16LF627A 1024 x 14 224 x 8 128 x 8

PIC16LF628A 2048 x 14 224 x 8 128 x 8

PIC16LF648A 4096 x 14 256 x 8 256 x 8

PIC16F627A/628A/648A

FIGURE 3-1: BLOCK DIAGRAM

Note 1: Higher order bits are from the Status register.

Flash

Program

Memory

13 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

8-Level Stack

(13-bit)

RAM

File

Registers

Direct Addr 7

RAM Addr (1) 9

Addr MUX

Indirect

Addr

FSR Reg

Status Reg

MUX

ALU

W Reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

PORTA

PORTB

RA4/T0CK1/CMP2

RA5/MCLR/VPP

RB0/INT

Brown-out

Reset

USART

CCP1

Timer0 Timer1 Timer2

RA3/AN3/CMP1

RA2/AN2/VREF

RA1/AN1

RA0/AN0

RB1/RX/DT

RB2/TX/CK

RB3/CCP1

RB4/PGM

RB5

RB6/T1OSO/T1CKI/PGC

RB7/T1OSI/PGD

Low-Voltage

Programming

RA6/OSC2/CLKOUT

RA7/OSC1/CLKIN

VREF

Comparator

Data EEPROM

PIC16F627A/628A/648A

TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION

Name Function Input Type Output Type Description

RA0/AN0 RA0 ST CMOS Bidirectional I/O port

AN0 AN — Analog comparator input

RA1/AN1 RA1 ST CMOS Bidirectional I/O port

AN1 AN — Analog comparator input

RA2/AN2/VREF RA2 ST CMOS Bidirectional I/O port

AN2 AN — Analog comparator input

VREF —ANVREF output

RA3/AN3/CMP1 RA3 ST CMOS Bidirectional I/O port

AN3 AN — Analog comparator input

CMP1 — CMOS Comparator 1 output

RA4/T0CKI/CMP2 RA4 ST OD Bidirectional I/O port

T0CKI ST — Timer0 clock input

CMP2 — OD Comparator 2 output

RA5/MCLR/VPP RA5 ST — Input port

MCLR ST — Master clear. When configured as MCLR, this

pin is an active low Reset to the device.

Voltage on MCLR/VPP must not exceed VDD

during normal device operation.

VPP — — Programming voltage input

RA6/OSC2/CLKOUT RA6 ST CMOS Bidirectional I/O port

OSC2 — XTAL Oscillator crystal output. Connects to crystal

or resonator in Crystal Oscillator mode.

CLKOUT — CMOS In RC/INTOSC mode, OSC2 pin can output

CLKOUT, which has 1/4 the frequency of

OSC1.

RA7/OSC1/CLKIN RA7 ST CMOS Bidirectional I/O port

OSC1 XTAL — Oscillator crystal input

CLKIN ST — External clock source input. RC biasing pin.

RB0/INT RB0 TTL CMOS Bidirectional I/O port. Can be software

programmed for internal weak pull-up.

INT ST — External interrupt

RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software

programmed for internal weak pull-up.

RX ST — USART receive pin

DT ST CMOS Synchronous data I/O

RB2/TX/CK RB2 TTL CMOS Bidirectional I/O port. Can be software

programmed for internal weak pull-up.

TX — CMOS USART transmit pin

CK ST CMOS Synchronous clock I/O

RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software

programmed for internal weak pull-up.

CCP1 ST CMOS Capture/Compare/PWM I/O

Legend: O = Output CMOS = CMOS Output P = Power

— = Not used I = Input ST = Schmitt Trigger Input

TTL = TTL Input OD = Open Drain Output AN = Analog

PIC16F627A/628A/648A

RB4/PGM RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.

Can be software programmed for internal

weak pull-up.

PGM ST — Low-voltage programming input pin. When

low-voltage programming is enabled, the

interrupt-on-pin change and weak pull-up

resistor are disabled.

RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.

Can be software programmed for internal

weak pull-up.

RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.

Can be software programmed for internal

weak pull-up.

T1OSO — XTAL Timer1 oscillator output

T1CKI ST — Timer1 clock input

PGC ST — ICSP™ programming clock

RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.

Can be software programmed for internal

weak pull-up.

T1OSI XTAL — Timer1 oscillator input

PGD ST CMOS ICSP data I/O

VSS VSS Power — Ground reference for logic and I/O pins

VDD VDD Power — Positive supply for logic and I/O pins

TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION (CONTINUED)

Name Function Input Type Output Type Description

Legend: O = Output CMOS = CMOS Output P = Power

— = Not used I = Input ST = Schmitt Trigger Input

TTL = TTL Input OD = Open Drain Output AN = Analog

PIC16F627A/628A/648A

3.1 Clocking Scheme/Instruction

Cycle

The clock input (RA7/OSC1/CLKIN pin) is internally

divided by four to generate four non-overlapping

quadrature clocks namely Q1, Q2, Q3 and Q4.

Internally, the Program Counter (PC) is incremented

every Q1, the instruction is fetched from the program

memory and latched into the instruction register in Q4.

The instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution flow is shown in Figure 3-2.

3.2 Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

PC PC + 1 PC + 2

Fetch INST (PC)

Execute INST (PC - 1) Fetch INST (PC + 1)

Execute INST (PC) Fetch INST (PC + 2)

Execute INST (PC + 1)

Internal

phase

clock

Note: All instructions are single cycle except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, 3 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16F627A/628A/648A has a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. Only the first 1K x 14 (0000h-03FFh)

for the PIC16F627A, 2K x 14 (0000h-07FFh) for the

PIC16F628A and 4K x 14 (0000h-0FFFh) for the

PIC16F648A are physically implemented. Accessing a

location above these boundaries will cause a wrap-

around within the first 1K x 14 space (PIC16F627A),

2K x 14 space (PIC16F628A) or 4K x 14 space

(PIC16F648A). The Reset vector is at 0000h and the

interrupt vector is at 0004h (Figure 4-1).

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK

4.2 Data Memory Organization

The data memory (Figure 4-2 and Figure 4-3) is

partitioned into four banks, which contain the General

Purpose Registers (GPRs) and the Special Function

Registers (SFRs). The SFRs are located in the first 32

locations of each bank. There are General Purpose

Registers implemented as static RAM in each bank.

Table 4-1 lists the General Purpose Register available

in each of the four banks.

TABLE 4-1: GENERAL PURPOSE STATIC

RAM REGISTERS

Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are

implemented as common RAM and mapped back to

addresses 70h-7Fh.

Table 4-2 lists how to access the four banks of registers

via the Status register bits RP1 and RP0.

TABLE 4-2: ACCESS TO BANKS OF

REGISTERS

4.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 224 x 8 in the

PIC16F627A/628A and 256 x 8 in the PIC16F648A.

Each is accessed either directly or indirectly through

the File Select Register (FSR), See Section 4.4

“Indirect Addressing, INDF and FSR Registers”.

PC<12:0>

000h

0004

0005

03FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

07FFh

PIC16F627A,

PIC16F628A and

PIC16F648A

On-chip Program

Memory

PIC16F628A and

PIC16F648A

On-chip Program

Memory

PIC16F648A only

0FFFh

PIC16F627A/628A PIC16F648A

Bank0 20-7Fh 20-7Fh

Bank1 A0h-FF A0h-FF

Bank2 120h-14Fh, 170h-17Fh 120h-17Fh

Bank3 1F0h-1FFh 1F0h-1FFh

Bank RP1 RP0

000

101

210

311

PIC16F627A/628A/648A

FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A

Indirect addr.(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PIE1

PCON

PR2

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

7Fh FFh

Bank 0 Bank 1

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

File

Address

Indirect addr.(1) Indirect addr.(1)

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

17Fh 1FFh

Bank 2 Bank 3

Indirect addr.(1)

TMR0 OPTION

RCSTA

TXREG

RCREG

CMCON

TXSTA

SPBRG

VRCON

General

Purpose

1EFh

1F0h

accesses

70h-7Fh

EFh

F0h

accesses

70h-7Fh

16Fh

170h

accesses

70h-7Fh

80 Bytes

EEDATA

EEADR

EECON1

EECON2(1)

General

Purpose

80 Bytes

General

Purpose

48 Bytes

11Fh

120h

14Fh

150h

6Fh

70h

16 Bytes

PORTB TRISB

1Ch

1Dh

1Eh

PIC16F627A/628A/648A

FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A

Indirect addr.(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PIE1

PCON

PR2

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

7Fh FFh

Bank 0 Bank 1

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

File

Address

Indirect addr.(1) Indirect addr.(1)

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

17Fh 1FFh

Bank 2 Bank 3

Indirect addr.(1)

TMR0 OPTION

RCSTA

TXREG

RCREG

CMCON

TXSTA

SPBRG

VRCON

General

Purpose

1EFh

1F0h

accesses

70h-7Fh

EFh

F0h

accesses

70h-7Fh

16Fh

170h

accesses

70h-7Fh

80 Bytes

EEDATA

EEADR

EECON1

EECON2(1)

General

Purpose

80 Bytes

11Fh

120h

6Fh

70h

16 Bytes

PORTB TRISB

1Ch

1Dh

1Eh

General

Purpose

80 Bytes

PIC16F627A/628A/648A

4.2.2 SPECIAL FUNCTION REGISTERS

The SFRs are registers used by the CPU and Periph-

eral functions for controlling the desired operation of

the device (Table 4-3). These registers are static RAM.

The special registers can be classified into two sets

(core and peripheral). The SFRs associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

described in the section of that peripheral feature.

TABLE 4-3: SPECIAL REGISTERS SUMMARY BANK0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Reset(1) Details

on Page

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30

01h TMR0 Timer0 Module’s Register xxxx xxxx 47

02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30

03h STATUS IRP RP1 RP0 TO PD ZDC C0001 1xxx 24

04h FSR Indirect Data Memory Address Pointer xxxx xxxx 30

05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 33

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 38

07h —Unimplemented — —

08h —Unimplemented — —

09h —Unimplemented — —

0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30

0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26

0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 28

0Dh —Unimplemented — —

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 50

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 50

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 50

11h TMR2 TMR2 Module’s Register 0000 0000 54

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54

13h —Unimplemented — —

14h —Unimplemented — —

15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 57

16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 57

17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 57

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 74

19h TXREG USART Transmit Data Register 0000 0000 79

1Ah RCREG USART Receive Data Register 0000 0000 82

1Bh —Unimplemented — —

1Ch —Unimplemented — —

1Dh —Unimplemented — —

1Eh —Unimplemented — —

1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 63

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

PIC16F627A/628A/648A

TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK1

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Reset(1) Details

on Page

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical

xxxx xxxx 30

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 25

82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30

83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 24

84h FSR Indirect Data Memory Address Pointer xxxx xxxx 30

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 33

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 38

87h —Unimplemented — —

88h —Unimplemented — —

89h —Unimplemented — —

8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30

8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26

8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 27

8Dh —Unimplemented — —

8Eh PCON — — — — OSCF —PORBOR ---- 1-0x 29

8Fh —Unimplemented — —

90h —Unimplemented — —

91h —Unimplemented — —

92h PR2 Timer2 Period Register 1111 1111 54

93h —Unimplemented — —

94h —Unimplemented — —

95h —Unimplemented — —

96h —Unimplemented — —

97h —Unimplemented — —

98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 73

99h SPBRG Baud Rate Generator Register 0000 0000 75

9Ah EEDATA EEPROM Data Register xxxx xxxx 91

9Bh EEADR EEPROM Address Register xxxx xxxx 92

9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 92

9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 92

9Eh —Unimplemented — —

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 69

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

PIC16F627A/628A/648A

TABLE 4-5: SPECIAL FUNCTION REGISTERS SUMMARY BANK2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Reset(1) Details

on Page

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30

101h TMR0 Timer0 Module’s Register xxxx xxxx 47

102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30

103h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 24

104h FSR Indirect Data Memory Address Pointer xxxx xxxx 30

105h —Unimplemented — —

106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 38

107h —Unimplemented — —

108h —Unimplemented — —

109h —Unimplemented — —

10Ah PCLATH ——— Write Buffer for upper 5 bits of Program Counter ---0 0000 30

10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26

10Ch —Unimplemented — —

10Dh —Unimplemented — —

10Eh —Unimplemented — —

10Fh —Unimplemented — —

110h —Unimplemented — —

111h —Unimplemented — —

112h —Unimplemented — —

113h —Unimplemented — —

114h —Unimplemented — —

115h —Unimplemented — —

116h —Unimplemented — —

117h —Unimplemented — —

118h —Unimplemented — —

119h —Unimplemented — —

11Ah —Unimplemented — —

11Bh —Unimplemented — —

11Ch —Unimplemented — —

11Dh —Unimplemented — —

11Eh —Unimplemented — —

11Fh —Unimplemented — —

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented.

Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

PIC16F627A/628A/648A

TABLE 4-6: SPECIAL FUNCTION REGISTERS SUMMARY BANK3

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Reset(1) Details

on Page

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30

181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 25

182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30

183h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 24

184h FSR Indirect Data Memory Address Pointer xxxx xxxx 30

185h —Unimplemented — —

186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 38

187h —Unimplemented — —

188h —Unimplemented — —

189h —Unimplemented — —

18Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30

18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26

18Ch —Unimplemented — —

18Dh —Unimplemented — —

18Eh —Unimplemented — —

18Fh —Unimplemented — —

190h —Unimplemented — —

191h —Unimplemented — —

192h —Unimplemented — —

193h —Unimplemented — —

194h —Unimplemented — —

195h —Unimplemented — —

196h —Unimplemented — —

197h —Unimplemented — —

198h —Unimplemented — —

199h —Unimplemented — —

19Ah —Unimplemented — —

19Bh —Unimplemented — —

19Ch —Unimplemented — —

19Dh —Unimplemented — —

19Eh —Unimplemented — —

19Fh —Unimplemented — —

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

PIC16F627A/628A/648A

4.2.2.1 Status Register

The Status register, shown in Register 4-1, contains the

arithmetic status of the ALU; the Reset status and the

bank select bits for data memory (SRAM).

The Status register can be the destination for any

instruction, like any other register. If the Status register

is the destination for an instruction that affects the Z,

DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are non-

writable. Therefore, the result of an instruction with the

Status register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper-three

bits and set the Z bit. This leaves the Status register

as “000uu1uu” (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

Status register because these instructions do not affect

any Status bit. For other instructions, not affecting any

Status bits, see the “Instruction Set Summary”.

Note: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh)

0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh)

01 = Bank 1 (80h-FFh)

10 = Bank 2 (100h-17Fh)

11 = Bank 3 (180h-1FFh)

bit 4 TO: Time Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for Borrow the polarity

is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

4.2.2.2 OPTION Register

The Option register is a readable and writable register,

which contains various control bits to configure the

TMR0/WDT prescaler, the external RB0/INT interrupt,

TMR0 and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT

(PSA = 1). See Section 6.3.1 “Switching

Prescaler Assignment”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI/CMP2 pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI/CMP2 pin

0 = Increment on low-to-high transition on RA4/T0CKI/CMP2 pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F627A/628A/648A

4.2.2.3 INTCON Register

The INTCON register is a readable and writable

for all interrupt sources except the comparator module.

See Section 4.2.2.4 “PIE1 Register” and

Section 4.2.2.5 “PIR1 Register” for a description of

the comparator enable and flag bits.

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB<7:4> pins changes state (must be cleared in software)

0 = None of the RB<7:4> pins have changed state

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

4.2.2.4 PIE1 Register

This register contains interrupt enable bits.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable Bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt

0 = Disables the comparator interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit 3 Unimplemented: Read as ‘0’

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

4.2.2.5 PIR1 Register

This register contains interrupt flag bits.

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0

EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator output has changed

0 = Comparator output has not changed

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full

0 = The USART receive buffer is empty

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty

0 = The USART transmit buffer is full

bit 3 Unimplemented: Read as ‘0’

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

4.2.2.6 PCON Register

The PCON register contains flag bits to differentiate

between a Power-on Reset, an external MCLR Reset,

WDT Reset or a Brown-out Reset.

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent Resets to see if BOR is

cleared, indicating a brown-out has

occurred. The BOR Status bit is a “don’t

care” and is not necessarily predictable if

the brown-out circuit is disabled (by

clearing the BOREN bit in the

Configuration Word).

U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-0 R/W-x

— — — — OSCF —PORBOR

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3 OSCF: INTOSC Oscillator Frequency bit

1 = 4 MHz typical

0 = 48 kHz typical

bit 2 Unimplemented: Read as ‘0’

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

4.3 PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low

byte comes from the PCL register, which is a readable

and writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from PCLATH.

On any Reset, the PC is cleared. Figure 4-4 shows the

two situations for loading the PC. The upper example

in Figure 4-4 shows how the PC is loaded on a write to

PCL (PCLATH<4:0> → PCH). The lower example in

Figure 4-4 shows how the PC is loaded during a CALL

or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-4: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556 “Implementing a Table Read”

(DS00556).

4.3.2 STACK

The PIC16F627A/628A/648A family has an 8-level

deep x 13-bit wide hardware stack (Figure 4-1). The

stack space is not part of either program or data space

and the Stack Pointer is not readable or writable. The

PC is PUSHed onto the stack when a CALL instruction

is executed or an interrupt causes a branch. The stack

is POPed in the event of a RETURN, RETLW or a

RETFIE instruction execution. PCLATH is not affected

by a PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

4.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no-operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit

(STATUS<7>), as shown in Figure 4-5.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRES S ING

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions, or the vectoring to an

interrupt address.

MOVLW 0x20 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

;yes continue

PIC16F627A/628A/648A

FIGURE 4-5: DIRECT/INDIRECT A DDRESSING PIC16F627A/628A/648A

Note: For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1.

RAM

Indirect AddressingDirect Addressing

bank select location select

RP1 RP0 6 0

from opcode IRP FSR Register

bank select location select

00 01 10 11

180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

File

Registers

Status

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

5.0 I/O PORTS

The PIC16F627A/628A/648A have two ports, PORTA

and PORTB. Some pins for these I/O ports are

multiplexed with alternate functions for the peripheral

features on the device. In general, when a peripheral is

enabled, that pin may not be used as a general

purpose I/O pin.

5.1 PORTA and TRISA Registers

PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger

input and an open drain output. Port RA4 is multiplexed

with the T0CKI clock input. RA5(1) is a Schmitt Trigger

input only and has no output drivers. All other RA port

pins have Schmitt Trigger input levels and full CMOS

output drivers. All pins have data direction bits (TRIS

registers) which can configure these pins as input or

output.

A ‘1’ in the TRISA register puts the corresponding

output driver in a High-impedance mode. A ‘0’ in the

TRISA register puts the contents of the output latch on

the selected pin(s).

Reading the PORTA register reads the status of the

pins whereas writing to it will write to the port latch. All

write operations are read-modify-write operations. So a

write to a port implies that the port pins are first read,

then this value is modified and written to the port data

latch.

The PORTA pins are multiplexed with comparator and

voltage reference functions. The operation of these

pins are selected by control bits in the CMCON

(Comparator Control register) register and the VRCON

(Voltage Reference Control register) register. When

selected as a comparator input, these pins will read

as ‘0’s.

TRISA controls the direction of the RA pins, even when

they are being used as comparator inputs. The user

must make sure to keep the pins configured as inputs

when using them as comparator inputs.

The RA2 pin will also function as the output for the

voltage reference. When in this mode, the VREF pin is a

very high-impedance output. The user must configure

TRISA<2> bit as an input and use high-impedance

loads.

In one of the comparator modes defined by the

CMCON register, pins RA3 and RA4 become outputs

of the comparators. The TRISA<4:3> bits must be

cleared to enable outputs to use this function.

EXAMPLE 5-1: INITIALI ZING PORTA

FIGURE 5-1: BLOCK DIAGRAM OF

RA0/AN0:RA1/AN1 PINS

Note 1: RA5 shares function with VPP. When VPP

voltage levels are applied to RA5, the

device will enter Programming mode.

2: On Reset, the TRISA register is set to all

inputs. The digital inputs (RA<3:0>) are

disabled and the comparator inputs are

forced to ground to reduce current

consumption.

3: TRISA<6:7> is overridden by oscillator

configuration. When PORTA<6:7> is

overridden, the data reads ‘0’ and the

TRISA<6:7> bits are ignored.

CLRF PORTA ;Initialize PORTA by

;setting

;output data latches

MOVLW 0x07 ;Turn comparators off and

MOVWF CMCON ;enable pins for I/O

;functions

BCF STATUS, RP1

BSF STATUS, RP0 ;Select Bank1

MOVLW 0x1F ;Value used to initialize

;data direction

MOVWF TRISA ;Set RA<4:0> as inputs

;TRISA<5> always

;read as ‘1’.

;TRISA<7:6>

;depend on oscillator

;mode

Data

Bus QD

PORTA

TRISA

Data Latch

TRIS Latch

RD PORTA

Analog

I/O Pin

Input Mode

To Comparator

Schmitt Trigger

Input Buffer

VDD

VSS

TRISA

(CMCON Reg.)

PIC16F627A/628A/648A

FIGURE 5-2: BLOCK DIAGRAM OF

RA2/AN2/VREF PIN

FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3/CMP1 PIN

Data

Bus QD

PORTA

TRISA

Data Latch

TRIS Latch

RD PORTA

Analog

RA2 Pin

CK Input Mode

To Comparator

Schmitt Trigger

Input Buffer

VROE

VREF

VDD

VSS

TRISA

(CMCON Reg.)

Data

Bus QD

PORTA

TRISA

Data Latch

TRIS Latch

RD PORTA

Analog

RA3 Pin

To Comparator

Schmitt Trigger

Input Buffer

Input Mode

Comparator Output

Comparator Mode = 110 VDD

VSS

TRISA

(CMCON Reg.)

PIC16F627A/628A/648A

FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI/CMP2 PIN

FIGURE 5-5: BLOCK DIAGRAM OF THE

RA5/MCLR/VPP PIN FIGURE 5-6: BLOCK DIAGRAM OF

RA6/OSC2/CLKOUT PIN

Data

Bus QD

PORTA

TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

Vss

RA4 Pin

TMR0 Clock Input

Schmitt Trigger

Input Buffer

Comparator Output

Comparator Mode = 110

Vss

(CMCON Reg.)

HV Detect

MCLR Filter

RA5/MCLR/VPP

MCLR

Program

MCLRE

VSS

Data

Bus

VSS

PORTA

circuit

mode

Schmitt Trigger

Input Buffer

TRISA

(Configuration Bit)

WR D

PORTA

TRISA

VDD

VSS

CLKOUT(FOSC/4)

FOSC =

101, 111 (2)

RD PORTA

FOSC =

011, 100, 110 (1)

TRISA

From OSC1 OSC

Circuit

Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O.

2: INTOSC with RA6 = CLKOUT or RC with

RA6 = CLKOUT.

Schmitt

Trigger

Input Buffer

Data Latch

TRIS Latch

PIC16F627A/628A/648A

FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN

Data Bus QD

WR PORTA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

RA7/OSC1/CLKIN Pin

To Clock Circuits

FOSC = 100, 101(1)

VDD

VSS

Note 1: INTOSC with CLKOUT and INTOSC with I/O.

Schmitt Trigger

Input Buffer

PIC16F627A/628A/648A

TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Function Input

Type Output

Type Description

RA0/AN0 RA0 ST CMOS Bidirectional I/O port

AN0 AN — Analog comparator input

RA1/AN1 RA1 ST CMOS Bidirectional I/O port

AN1 AN — Analog comparator input

RA2/AN2/VREF RA2 ST CMOS Bidirectional I/O port

AN2 AN — Analog comparator input

VREF —ANVREF output

RA3/AN3/CMP1 RA3 ST CMOS Bidirectional I/O port

AN3 AN — Analog comparator input

CMP1 — CMOS Comparator 1 output

RA4/T0CKI/CMP2 RA4 ST OD Bidirectional I/O port. Output is open drain type.

T0CKI ST — External clock input for TMR0 or comparator output

CMP2 — OD Comparator 2 output

RA5/MCLR/VPP RA5 ST — Input port

MCLR ST — Master clear. When configured as MCLR, this pin is an

active low Reset to the device. Voltage on MCLR/VPP must

not exceed VDD during normal device operation.

VPP HV — Programming voltage input

RA6/OSC2/CLKOUT RA6 ST CMOS Bidirectional I/O port

OSC2 — XTAL Oscillator crystal output. Connects to crystal resonator in

Crystal Oscillator mode.

CLKOUT — CMOS In RC or INTOSC mode. OSC2 pin can output CLKOUT,

which has 1/4 the frequency of OSC1.

RA7/OSC1/CLKIN RA7 ST CMOS Bidirectional I/O port

OSC1 XTAL — Oscillator crystal input. Connects to crystal resonator in

Crystal Oscillator mode.

CLKIN ST — External clock source input. RC biasing pin.

Legend: O = Output CMOS = CMOS Output P = Power

— = Not used I = Input ST = Schmitt Trigger Input

TTL = TTL Input OD = Open Drain Output AN = Analog

Add r e s s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR

Value on

All Other

Resets

05h PORTA RA7 RA6 RA5(1) RA4 RA3 RA2 RA1 RA0 xxxx 0000 qqqu 0000

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

9Fh VRCON VREN VROE VRR —VR3 VR2 VR1 VR0 000- 0000 000- 0000

Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition. Shaded cells

are not used for PORTA.

Note 1: MCLRE configuration bit sets RA5 functionality.

PIC16F627A/628A/648A

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bidirectional port. The

corresponding data direction register is TRISB. A ‘1’ in

the TRISB register puts the corresponding output driver

in a High-impedance mode. A ‘0’ in the TRISB register

puts the contents of the output latch on the selected

pin(s).

PORTB is multiplexed with the external interrupt,

USART, CCP module and the TMR1 clock input/output.

The standard port functions and the alternate port

functions are shown in Table 5-3. Alternate port

functions may override the TRIS setting when enabled.

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are first read, then

this value is modified and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up

(≈200 μA typical). A single control bit can turn on all the

pull-ups. This is done by clearing the RBPU

(OPTION<7>) bit. The weak pull-up is automatically

turned off when the port pin is configured as an output.

The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB<7:4>, have an interrupt-on-

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB<7:4> pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB<7:4>)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB<7:4>

are OR’ed together to generate the RBIF interrupt (flag

latched in INTCON<0>).

This interrupt can wake the device from Sleep. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software configurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression (See Application Note

AN552 “Implementing Wake-up on Key Strokes”

(DS00552).

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

FIGURE 5-8: BLOCK DIAGRAM OF

RB0/INT PIN

Note: If a change on the I/O pin should occur

when a read operation is being executed

(start of the Q2 cycle), then the RBIF

interrupt flag may not get set.

Data Bus

WR PORTB

WR TRISB

RD PORTB

Data Latch

TRIS Latch

RB0/INT

INT

RD TRISB

RBPU

VDD

VSS

CK Q

Weak Pull-up

Schmitt

TTL

Input

Buffer

Trigger

PIC16F627A/628A/648A

FIGURE 5-9: BLOCK DIAGRAM OF

RB1/RX/D T PIN FIGURE 5-10: BLOCK DIAGRAM OF

RB2/TX/CK PIN

Data Latch

TRIS Latch

RD TRISB

WR PORTB

WR TRISB

Schmitt

Trigger

Peripheral OE(1)

Data Bus

SPEN

USART Data Output

USART Receive Input

RBPU

VDD

VSS

Note 1: Peripheral OE (output enable) is only active if

peripheral select is active.

RD PORTB

RX/DT

RB1/

TTL

Input

Buffer

Weak

Pull-up

Data Latch

TRIS Latch

RD TRISB

WR PORTB

WR TRISB

Schmitt

Trigger

Peripheral OE(1)

Data Bus

SPEN

USART TX/CK Output

USART Slave Clock In

RBPU

VDD

VSS

Note 1: Peripheral OE (output enable) is only active if

peripheral select is active.

RD PORTB

TTL

Input

Buffer

RB2/

TX/CK

Weak

Pull-up

PIC16F627A/628A/648A

FIGURE 5-11: BLOCK DIAGRAM OF

RB3/CCP1 PIN

Data Latch

TRIS Latch

RD TRISB

WR PORTB

WR TRISB

Schmitt

Trigger

Peripheral OE(2)

Data Bus

CCP1CON

CCP output

CCP In

RBPU

VDD

VSS

Note 1: Peripheral OE (output enable) is only active if

peripheral select is active.

RD PORTB

TTL

Input

Buffer

RB3/

CCP1

Weak

Pull-up

PIC16F627A/628A/648A

FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN

Data Latch

TRIS Latch

RD TRISB

RD PORTB

WR PORTB

WR TRISB

Schmitt

Trigger

PGM input

LVP

Data Bus

RB4/PGM

VDD

weak pull-up

From other QD

Set RBIF

RB<7:4> pins

TTL

input

buffer

VDD

VSS

Note: The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.

RBPU

(Configuration Bit)

PIC16F627A/628A/648A

FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN

Data Bus

WR PORTB

WR TRISB

RD PORTB

Data Latch

TRIS Latch

RB5 pin

TTL

input

buffer

RD TRISB

RBPU

VDD

weak

pull-up

From other QD

Set RBIF

RB<7:4> pins

VDD

VSS

PIC16F627A/628A/648A

FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/PGC PIN

Data Latch

TRIS Latch

RD TRISB

RD PORTB

WR PORTB

WR TRISB

Schmitt

Trigger

T1OSCEN

Data Bus

RB6/

TMR1 Clock

RBPU

VDD

weak pull-up

From RB7

T1OSO/

T1CKI/

PGC

From other QD

Set RBIF

RB<7:4> pins

Serial Programming Clock

TTL

input

buffer

TMR1 oscillator

VDD

VSS

PIC16F627A/628A/648A

FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI/PGD PIN

Data Latch

TRIS Latch

RD TRISB

RD PORTB

WR PORTB

WR TRISB

T10SCEN

Data Bus

RB7/T1OSI/

To R B 6

RBPU

VDD

weak pull-up

PGD pin

TTL

input

buffer

From other QD

Set RBIF

RB<7:4> pins

Serial Programming Input

Schmitt

Trigger

TMR1 oscillator

VDD

VSS

PIC16F627A/628A/648A

TABLE 5-3: PORTB FUNCTIONS

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Function Input Type Output

Type Description

RB0/INT RB0 TTL CMOS Bidirectional I/O port. Can be software programmed for

internal weak pull-up.

INT ST — External interrupt

RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software programmed for

internal weak pull-up.

RX ST — USART Receive Pin

DT ST CMOS Synchronous data I/O

RB2/TX/CK RB2 TTL CMOS Bidirectional I/O port

TX — CMOS USART Transmit Pin

CK ST CMOS Synchronous Clock I/O. Can be software programmed

for internal weak pull-up.

RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software programmed for

internal weak pull-up.

CCP1 ST CMOS Capture/Compare/PWM/I/O

RB4/PGM RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be

software programmed for internal weak pull-up.

PGM ST — Low-voltage programming input pin. When low-voltage

programming is enabled, the interrupt-on-pin change

and weak pull-up resistor are disabled.

RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be

software programmed for internal weak pull-up.

RB6/T1OSO/T1CKI/

PGC

RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be

software programmed for internal weak pull-up.

T1OSO — XTAL Timer1 Oscillator Output

T1CKI ST — Timer1 Clock Input

PGC ST — ICSP™ Programming Clock

RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be

software programmed for internal weak pull-up.

T1OSI XTAL — Timer1 Oscillator Input

PGD ST CMOS ICSP Data I/O

Legend: O = Output CMOS = CMOS Output P = Power

— = Not used I = Input ST = Schmitt Trigger Input

TTL = TTL Input OD = Open Drain Output AN = Analog

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

Resets

06h, 106h PORTB RB7 RB6 RB5 RB4(1) RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: u = unchanged, x = unknown. Shaded cells are not used for PORTB.

Note 1: LVP configuration bit sets RB4 functionality.

PIC16F627A/628A/648A

5.3 I/O Programming Considerations

5.3.1 BIDIRECTIONAL I/O PORTS

Any instruction that writes operates internally as a read

followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result

back to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs defined. For example, a BSF operation on bit 5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the BSF operation takes place on

bit 5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bidirectional I/O pin

(e.g., bit 0) and is defined as an input at this time, the

input signal present on the pin itself would be read into

the CPU and rewritten to the data latch of this particular

pin, overwriting the previous content. As long as the pin

stays in the Input mode, no problem occurs. However,

if bit 0 is switched into Output mode later on, the

content of the data latch may now be unknown.

Reading a port register reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(ex. BCF, BSF, etc.) on a port, the value of the port pins

is read, the desired operation is done to this value, and

this value is then written to the port latch.

Example 5-2 shows the effect of two sequential read-

modify-write instructions (ex., BCF, BSF, etc.) on an

I/O port.

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-OR”, “wired-

AND”). The resulting high output currents may damage

the chip.

EXAMPLE 5-2: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

5.3.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of

an instruction cycle, whereas for reading, the data

must be valid at the beginning of the instruction cycle

(Figure 5-16). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load

dependent) before the next instruction, which causes

that file to be read into the CPU, is executed. Other-

wise, the previous state of that pin may be read into

the CPU rather than the new state. When in doubt, it

is better to separate these instructions with a NOP or

another instruction not accessing this I/O port.

FIGURE 5-16: SUCCESSIVE I/O OPERATION

;Initial PORT settings:PORTB<7:4> Inputs

; PORTB<3:0> Outputs

;PORTB<7:6> have external pull-up and are

;not connected to other circuitry

;

; PORT latchPORT Pins

---------- ----------

BCF STATUS, RP0 ;

BCF PORTB, 7 ;01pp pppp 11pp pppp

BSF STATUS, RP0 ;

BCF TRISB, 7 ;10pp pppp 11pp pppp

BCF TRISB, 6 ;10pp pppp 10pp pppp

;

;Note that the user may have expected the

;pin values to be 00pp pppp. The 2nd BCF

;caused RB7 to be latched as the pin value

;(High).

Q1 Q2 Q3 Q4

Instruction

fetched

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC + 1

PC PC + 2 PC + 3

MOVWF PORTB

Write to PORTB

MOVF PORTB, W

Read to PORTB

NOP NOP

TPD

Execute

MOVWF

PORTB

Execute

MOVF

PORTB, W

Port pin

sampled here

Execute

NOP

Note 1: This example shows write to PORTB followed by a read from PORTB.

2: Data setup time = (0.25 T

CY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle

to output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic.

PIC16F627A/628A/648A

6.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Read/write capabilities

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module. Additional information is available in the “PIC®

Mid-Range MCU Fa mily Reference Manual” (DS33023).

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the TMR0 register value

will increment every instruction cycle (without

prescaler). If the TMR0 register is written to, the

increment is inhibited for the following two cycles. The

user can work around this by writing an adjusted value

to the TMR0 register.

Counter mode is selected by setting the T0CS bit. In

this mode the TMR0 register value will increment either

on every rising or falling edge of pin RA4/T0CKI/CMP2.

The incrementing edge is determined by the source

edge (T0SE) control bit (OPTION<4>). Clearing the

T0SE bit selects the rising edge. Restrictions on the

external clock input are discussed in detail in

Section 6.2 “Using Tim er0 with External Clock”.

The prescaler is shared between the Timer0 module

and the Watchdog Timer. The prescaler assignment is

controlled in software by the control bit PSA

(OPTION<3>). Clearing the PSA bit will assign the

prescaler to Timer0. The prescaler is not readable or

writable. When the prescaler is assigned to the Timer0

module, prescale value of 1:2, 1:4,..., 1:256 are

selectable. Section 6.3 “Timer0 Prescaler” details

the operation of the prescaler.

6.1 Timer0 Interrupt

Timer0 interrupt is generated when the TMR0 register

timer/counter overflows from FFh to 00h. This overflow

sets the T0IF bit. The interrupt can be masked by

clearing the T0IE bit (INTCON<5>). The T0IF bit

(INTCON<2>) must be cleared in software by the

Timer0 module interrupt service routine before re-

enabling this interrupt. The Timer0 interrupt cannot

wake the processor from Sleep since the timer is shut

off during Sleep.

6.2 Using Timer0 with External Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (T

OSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1 EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-1). Therefore, it is necessary for T0CKI to be

high for at least 2T

OSC (and a small RC delay of 20 ns)

and low for at least 2T

OSC (and a small RC delay of

20 ns). Refer to the electrical specification of the

desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple-counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4T

OSC (and a small RC delay of 40 ns)

divided by the prescaler value. The only requirement

on T0CKI high and low time is that they do not violate

the minimum pulse width requirement of 10 ns. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device. See Table 17-8.

PIC16F627A/628A/648A

6.3 Timer0 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. A prescaler assignment for the Timer0 module

means that there is no postscaler for the Watchdog

Timer, and vice-versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer. The prescaler

is not readable or writable.

FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT

T0CKI

T0SE

FOSC/4

SYNC

Cycles

TMR0 Reg

8-to-1MUX

Watchdog

Timer

PSA

WDT

Time-out

PS<2:0>

PSA

WDT Enable bit

Data Bus

Set flag bit T0IF

on Overflow

PSA

Note: T0SE, T0CS, PSA, PS<2:0> are bits in the Option Register.

T0CS

WDT Postscaler/

TMR0 Prescaler

TMR1 Clock Source

PIC16F627A/628A/648A

6.3.1 SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during

program execution). Use the instruction sequences

shown in Example 6-1 when changing the prescaler

assignment from Timer0 to WDT, to avoid an

unintended device Reset.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0 →WDT)

To change prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This

precaution must be taken even if the WDT is disabled.

EXAMPLE 6-2: CHANGING PRESCA LER

(WDT →TIMER0)

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

BCF STATUS, RP0 ;Skip if already in

;Bank 0

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 and

;Prescaler

BSF STATUS, RP0 ;Bank 1

MOVLW '00101111’b ;These 3 lines

;(5, 6, 7)

MOVWF OPTION_REG ;are required only

;if desired PS<2:0>

;are

CLRWDT ;000 or 001

MOVLW '00101xxx’b ;Set Postscaler to

MOVWF OPTION_REG ;desired WDT rate

BCF STATUS, RP0 ;Return to Bank 0

CLRWDT ;Clear WDT and

;prescaler

BSF STATUS, RP0

MOVLW b'xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

MOVWF OPTION_REG

BCF STATUS, RP0

Address Name Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

Resets

01h, 101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

81h, 181h OPTION(2) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used for Timer0.

Note 1: Option is referred by OPTION_REG in MPLAB® IDE Software.

PIC16F627A/628A/648A

7.0 TIMER1 MODULE

The Timer1 module is a 16-bit timer/counter consisting

of two 8-bit registers (TMR1H and TMR1L) which are

readable and writable. The TMR1 register pair

(TMR1H:TMR1L) increments from 0000h to FFFFh

and rolls over to 0000h. The Timer1 Interrupt, if

enabled, is generated on overflow of the TMR1 register

pair which latches the interrupt flag bit TMR1IF

(PIR1<0>). This interrupt can be enabled/disabled by

setting/clearing the Timer1 interrupt enable bit TMR1IE

(PIE1<0>).

Timer1 can operate in one of two modes:

•As a timer

•As a counter

The Operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

In Timer mode, the TMR1 register pair value

increments every instruction cycle. In Counter mode, it

increments on every rising edge of the external clock

input.

Timer1 can be enabled/disabled by setting/clearing

control bit TMR1ON (T1CON<0>).

Timer1 also has an internal “Reset input”. This Reset

can be generated by the CCP module (Section 9.0

“Capture/Compare/PWM (CCP) Module”).

For the PIC16F627A/628A/648A, when the Timer1

oscillator is enabled (T1OSCEN is set), the RB7/

T1OSI/PGD and RB6/T1OSO/T1CKI/PGC pins

become inputs. That is, the TRISB<7:6> value is

ignored.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled

0 = Oscillator is shut off(1)

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RB6/T1OSO/T1CKI/PGC (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

7.1 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS

(T1CON<1>) bit. In this mode, the input clock to the

timer is FOSC/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect since the internal clock is

always in sync.

7.2 Timer 1 Operation in Sync hronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mode, the TMR1 register pair value increments on

every rising edge of clock input on pin RB7/T1OSI/PGD

when bit T1OSCEN is set or pin RB6/T1OSO/T1CKI/

PGC when bit T1OSCEN is cleared.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The

prescaler stage is an asynchronous ripple-counter.

In this configuration, during Sleep mode, the TMR1

external clock is present, since the synchronization

circuit is shut off. The prescaler however will continue

to increment.

7.2.1 EXTERNAL CLOCK INPUT TIMING

FOR SYNCHRONIZED COUNTER

MODE

When an external clock input is used for Timer1 in

Synchronized Counter mode, it must meet certain

requirements. The external clock requirement is due to

internal phase clock (TOSC) synchronization. Also,

there is a delay in the actual incrementing of the TMR1

When the prescaler is 1:1, the external clock input is

the same as the prescaler output. The synchronization

of T1CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T1CKI to be high for at least 2 TOSC (and

a small RC delay of 20 ns) and low for at least 2 T

OSC

(and a small RC delay of 20 ns). Refer to Table 17-8 in

the Electrical Specifications Section, timing parameters

45, 46 and 47.

When a prescaler other than 1:1 is used, the external

clock input is divided by the asynchronous ripple-counter

type prescaler so that the prescaler output is symmetri-

cal. In order for the external clock to meet the sampling

requirement, the ripple-counter must be taken into

account. Therefore, it is necessary for T1CKI to have a

period of at least 4 TOSC (and a small RC delay of 40 ns)

divided by the prescaler value. The only requirement on

T1CKI high and low time is that they do not violate the

minimum pulse width requirements of 10 ns). Refer to

the appropriate electrical specifications in Table 17-8,

parameters 45, 46 and 47.

FIGURE 7-1: TIMER1 BLOCK DIAGRAM

TMR1H TMR1L

T1OSC T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR1ON

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

RB6/T1OSO/T1CKI/PGC

RB7/T1OSI/PGD

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

Set flag bit

TMR1IF on

Overflow

TMR1

PIC16F627A/628A/648A

7.3 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up the

processor. However, special precautions in software are

needed to read/write the timer (Section 7.3.2 “Reading

and Writing Timer1 in Asynchronous Counter

Mode”).

7.3.1 EXTERNAL CLOCK INPUT TIMING

WITH UNSYNCHRONIZED CLOCK

If control bit T1SYNC is set, the timer will increment

completely asynchronously. The input clock must meet

certain minimum high and low time requirements. Refer

to Table 17-8 in the Electrical Specifications Section,

timing parameters 45, 46 and 47.

7.3.2 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading the TMR1H or TMR1L register, while the timer

is running from an external asynchronous clock, will

produce a valid read (taken care of in hardware).

However, the user should keep in mind that reading the

16-bit timer in two 8-bit values itself poses certain

problems since the timer may overflow between the

reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers

while the register is incrementing. This may produce an

unpredictable value in the timer register.

Reading the 16-bit value requires some care.

Example 7-1 is an example routine to read the 16-bit

timer value. This is useful if the timer cannot be

stopped.

EXAMPLE 7-1: READING A 16-BIT FREE-

RUNNING TIMER

Note: In Asynchronous Counter mode, Timer1

cannot be used as a time base for capture

or compare operations.

; All interrupts are disabled

MOVF TMR1H, W ;Read high byte

MOVWF TMPH ;

MOVF TMR1L, W ;Read low byte

MOVWF TMPL ;

MOVF TMR1H, W ;Read high byte

SUBWF TMPH, W ;Sub 1st read with

;2nd read

BTFSC STATUS,Z ;Is result = 0

GOTO CONTINUE ;Good 16-bit read

;

; TMR1L may have rolled over between the

; read of the high and low bytes. Reading

; the high and low bytes now will read a good

; value.

;

MOVF TMR1H, W ;Read high byte

MOVWF TMPH ;

MOVF TMR1L, W ;Read low byte

MOVWF TMPL ;

; Re-enable the Interrupts (if required)

CONTINUE ;Continue with your

;code

PIC16F627A/628A/648A

7.4 Timer1 Oscillator

A crystal oscillator circuit is built in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). It will

continue to run during Sleep. It is primarily intended for

a 32.768 kHz watch crystal. Table 7-1 shows the

capacitor selection for the Timer1 oscillator.

The user must provide a software time delay to ensure

proper oscillator start-up.

TABLE 7-1: CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

7.5 Resetting Timer1 Using a CCP

Trigger Output

If the CCP1 module is configured in Compare mode to

generate a “special event trigger” (CCP1M<3:0> =

1011), this signal will reset Timer1.

Timer1 must be configured for either timer or

Synchronized Counter mode to take advantage of this

feature. If Timer1 is running in Asynchronous Counter

mode, this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

In this mode of operation, the CCPRxH:CCPRxL

Timer1.

7.6 Resetting Timer1 Register Pair

(TMR1H, TMR1L)

TMR1H and TMR1L registers are not reset to 00h on

a POR or any other Reset except by the CCP1 special

event triggers (see Section 9.2.4 “Special Event

Trigger”).

T1CON register is reset to 00h on a Power-on Reset or

a Brown-out Reset, which shuts off the timer and

leaves a 1:1 prescale. In all other Resets, the register

is unaffected.

7.7 Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Freq C1 C2

32.768 kHz 15 pF 15 pF

Note: These values are for design guidance only.

Consult Application Note AN826 “Crystal

Oscillator Basics and Crystal Selection for

rfPIC® and PIC® Devices” (DS00826) for

further information on Crystal/Capacitor

Selection.

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Bh, 8Bh,

10Bh, 18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC16F627A/628A/648A

8.0 TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a

postscaler. It can be used as the PWM time base for

PWM mode of the CCP module. The TMR2 register is

readable and writable, and is cleared on any device

Reset.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits T2CKPS<1:0>

(T2CON<1:0>).

The Timer2 module has an 8-bit period register PR2.

The TMR2 register value increments from 00h until it

matches the PR2 register value and then resets to 00h

on the next increment cycle. The PR2 register is a

readable and writable register. The PR2 register is

initialized to FFh upon Reset.

The match output of Timer2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a Timer2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

Timer2 can be shut off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

8.1 Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

The TMR2 register is not cleared when T2CON is

written.

8.2 TMR2 Output

The TMR2 output (before the postscaler) is fed to the

Synchronous Serial Port module which optionally uses

it to generate shift clock.

FIGURE 8-1: TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets flag

TMR2 Reg

output

Reset

Postscaler

Prescaler

PR2 Reg

FOSC/4

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

T2CKPS<1:0>

TOUTPS<3:0>

PIC16F627A/628A/648A

TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale Value

0001 = 1:2 Postscale Value

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 = 1:1 Prescaler Value

01 = 1:4 Prescaler Value

1x = 1:16 Prescaler Value

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Bh, 8Bh,

10Bh, 18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

92h PR2 Timer2 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

9.0 CAPTURE/COMPARE/PWM

(CCP) MODULE

The CCP (Capture/Compare/PWM) module contains a

16-bit register which can operate as a 16-bit Capture

master/slave Duty Cycle register. Table 9-1 shows the

timer resources of the CCP module modes.

CCP1 Module

Capture/Compare/PWM Register1 (CCPR1) is

comprised of two 8-bit registers: CCPR1L (low byte)

and CCPR1H (high byte). The CCP1CON register

controls the operation of CCP1. All are readable and

writable.

Additional information on the CCP module is available

in the “PIC® Mid-Range MCU Family Reference Man-

ual” (DS33023).

TABLE 9-1: CCP MODE – TIMER

RESOURCE

CCP Mode Timer Resource

Capture Timer1

Compare Timer1

PWM Timer2

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 CCP1X:CCP1Y: PWM Least Significant bits

Capture Mode

Unused

Compare Mode

Unused

PWM Mode

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0 CCP1M<3:0>: CCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP1 module)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCP1IF bit is set)

1001 = Compare mode, clear output on match (CCP1IF bit is set)

1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is

unaffected)

1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1

11xx = PWM mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

9.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin RB3/CCP1. An event is defined as:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

An event is selected by control bits CCP1M<3:0>

(CCP1CON<3:0>). When a capture is made, the

interrupt request flag bit CCP1IF (PIR1<2>) is set. It

must be cleared in software. If another capture occurs

before the value in register CCPR1 is read, the old

captured value will be lost.

9.1.1 CCP PIN CONFIGURATION

In Capture mode, the RB3/CCP1 pin should be config-

ured as an input by setting the TRISB<3> bit.

FIGURE 9-1: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

9.1.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode for the CCP module to use the

capture feature. In Asynchronous Counter mode, the

capture operation may not work.

9.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit CCP1IF following any such

change in Operating mode.

9.1.4 CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M<3:0>. Whenever the CCP module is turned

off, or the CCP module is not in Capture mode, the

prescaler counter is cleared. This means that any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will not

be cleared, therefore the first capture may be from a

non-zero prescaler. Example 9-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 9-1: CHANGING BETWEE N

CAPTURE PRESCALERS

9.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RB3/CCP1 pin is:

• Driven high

•Driven low

• Remains unchanged

The action on the pin is based on the value of control

bits CCP1M<3:0> (CCP1CON<3:0>). At the same

time, interrupt flag bit CCP1IF is set.

FIGURE 9-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

Note: If the RB3/CCP1 is configured as an

output, a write to the port can cause a

capture condition.

CCPR1H CCPR1L

TMR1H TMR1L

Set flag bit CCP1IF

(PIR1<2>)

Capture

Enable

Q’s

CCP1CON<3:0>

RB3/CCP1

Prescaler

³ 1, 4, 16

and

edge detect

CLRF CCP1CON ;Turn CCP module off

MOVLW NEW_CAPT_PS ;Load the W reg with

; the new prescaler

; mode value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

; value

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Output

Logic

Set flag bit CCP1IF

(PIR1<2>)

match

RB3/CCP1

TRISB<3>

CCP1CON<3:0>

Mode Select

Output Enable

Note: Special event trigger will reset Timer1, but not

set interrupt flag bit TMR1IF (PIR1<0>).

PIC16F627A/628A/648A

9.2.1 CCP PIN CONFIGURATION

The user must configure the RB3/CCP1 pin as an

output by clearing the TRISB<3> bit.

9.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

9.2.3 SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

9.2.4 SPECIAL EVENT TRIGGER

In this mode (CCP1M<3:0>=1011), an internal hard-

ware trigger is generated, which may be used to initiate

an action. See Register 9-1.

The special event trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and CCPR1H, CCPR1L register

pair. The TMR1H, TMR1L register pair is not reset until

the next rising edge of the TMR1 clock. This allows the

CCPR1 register pair to effectively be a 16-bit program-

mable period register for Timer1. The special event

trigger output also starts an A/D conversion provided

that the A/D module is enabled.

TABLE 9-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Note: Clearing the CCP1CON register will force

the RB3/CCP1 compare output latch to

the default low level. This is not the data

latch.

Note: Removing the match condition by chang-

ing the contents of the CCPR1H, CCPR1L

generates the special event trigger and

the clock edge that generates the TMR1

Reset will preclude the Reset from

occuring.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Bh, 8Bh,

10Bh, 18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.

PIC16F627A/628A/648A

9.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is multiplexed with the PORTB data latch,

the TRISB<3> bit must be cleared to make the CCP1

pin an output.

Figure 9-3 shows a simplified block diagram of the

CCP module in PWM mode.

For a step by step procedure on how to set up the CCP

module for PWM operation, see Section 9.3.3 “Set-

Up for PWM Operation”.

FIGURE 9-3: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 9-4) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(frequency = 1/period).

FIGURE 9-4: PWM OUTPUT

9.3.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTB I/O data

latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty cycle registers CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISB<3>

RB3/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q

clock or 2 bits of the prescaler to create 10-bit

time base.

Note: The Timer2 postscaler (see Section 8.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

PWM perio d PR2()1+[]4 ⋅⋅= Tosc TMR2 prescale⋅value

PIC16F627A/628A/648A

9.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available: the CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM

frequency:

For an example PWM period and duty cycle

calculation, see the PIC® Mid-Range Reference Man-

ual (DS33023).

9.3.3 SET-UP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRISB<3> bit.

4. Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

TABLE 9-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

TABLE 9-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2

(CCPR1L:CCP1CON<5:4> ) Tosc TMR2 prescale

⋅⋅

value

PWM duty cycle =

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be

cleared.

Resolution log Fosc

FPWM TMR2 Prescaler

-------------------------------------------------------------

⎝⎠

⎛⎞

log(2)

--------------------------------------------------------------------------- b its=

PWM

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.5

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR

Va lu e on

all other

Resets

0Bh, 8Bh,

10Bh, 18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000

92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 uuuu uuuu

15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

10.0 COMPARATOR MODULE

The comparator module contains two analog

comparators. The inputs to the comparators are

multiplexed with the RA0 through RA3 pins. The on-chip

Voltage Reference (Section 11.0 “Voltage Reference

Module”) can also be an input to the comparators.

The CMCON register, shown in Register 10-1, controls

the comparator input and output multiplexers. A block

diagram of the comparator is shown in Figure 10-1.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

bit 7 bit 0

bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:

1 = C2 VIN+ > C2 VIN-

0 = C2 VIN+ < C2 VIN-

When C2INV = 1:

1 = C2 VIN+ < C2 VIN-

0 = C2 VIN+ > C2 VIN-

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:

1 = C1 VIN+ > C1 VIN-

0 = C1 VIN+ < C1 VIN-

When C1INV = 1:

1 = C1 VIN+ < C1 VIN-

0 = C1 VIN+ > C1 VIN-

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 Output inverted

0 = C2 Output not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit

1 = C1 Output inverted

0 = C1 Output not inverted

bit 3 CIS: Comparator Input Switch bit

When CM<2:0>: = 001

Then:

1 = C1 VIN- connects to RA3

0 = C1 VIN- connects to RA0

When CM<2:0> = 010

Then:

1 = C1 VIN- connects to RA3

C2 VIN- connects to RA2

0 = C1 VIN- connects to RA0

C2 VIN- connects to RA1

bit 2-0 CM<2:0>: Comparator Mode bits

Figure 10-1 shows the comparator modes and CM<2:0> bit settings

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

10.1 Comparator Configuration

There are eight modes of operation for the

comparators. The CMCON register is used to select

the mode. Figure 10-1 shows the eight possible

modes. The TRISA register controls the data direction

of the comparator pins for each mode.

If the Comparator mode is changed, the comparator

output level may not be valid for the specified mode

change delay shown in Table 17-2.

FIGURE 10-1: COMPARATOR I/O OPERATING MODES

Note 1: Comparator interrupts should be disabled

during a Comparator mode change,

otherwise a false interrupt may occur.

2: Comparators can have an inverted

output. See Figure 10-1.

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Comparators Reset (POR Default Value)

CM<2:0> = 000

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Two Independent Comparators

CM<2:0> = 100

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Two Common Reference Comparators

CM<2:0> = 011

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1 Off (Read as ‘0’)

One Independent Comparator

CM<2:0> = 101

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

VIN-

VIN+Off (Read as ‘0’)

Comparators Off

CM<2:0> = 111

VIN-

VIN+Off (Read as ‘0’)

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Four Inputs Multiplexed to Two Comparators

CM<2:0> = 010

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

From VREF

CIS = 0

CIS = 1

CIS = 0

CIS = 1

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Two Common Reference Comparators with Outputs

CM<2:0> = 110

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

Open Drain

A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.

RA4/T0CKI/CMP2

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Three Inputs Multiplexed to Two Comparators

CM<2:0> = 001

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

CIS = 0

CIS = 1

VSS

RA0/AN0

RA3/AN3/CMP1

RA1/AN1

RA2/AN2/VREF

Module

C1VOUT

C2VOUT

C1VOUT

C2VOUT

Off (Read as ‘0’)

C2VOUT

C1VOUT

C2VOUT

C1VOUT

C2VOUT

C1VOUT

C2VOUT

PIC16F627A/628A/648A

The code example in Example 10-1 depicts the steps

required to configure the Comparator module. RA3 and

RA4 are configured as digital output. RA0 and RA1 are

configured as the V- inputs and RA2 as the V+ input to

both comparators.

EXAMPLE 10-1: INITIALIZING

COMPARATOR MODULE

10.2 Comparator Operation

A single comparator is shown in Figure 10-2 along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN-, the output of the comparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 10-2 represent

the uncertainty due to input offsets and response time.

See Table 17-2 for Common Mode voltage.

10.3 Comparator Reference

An external or internal reference signal may be used

depending on the comparator Operating mode. The

analog signal that is present at VIN- is compared to the

signal at VIN+, and the digital output of the comparator

is adjusted accordingly (Figure 10-2).

FIGURE 10-2: SINGLE COMPARATOR

10.3.1 EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

Comparator module can be configured to have the

comparators operate from the same or different

reference sources. However, threshold detector

applications may require the same reference. The

reference signal must be between VSS and VDD, and

can be applied to either pin of the comparator(s).

10.3.2 INTERNAL REFERENCE SIGNAL

The Comparator module also allows the selection of an

internally generated voltage reference for the

comparators. Section 11.0 “Voltage Reference

Module”, contains a detailed description of the Voltage

Reference module that provides this signal. The

internal reference signal is used when the comparators

are in mode CM<2:0> = 010 (Figure 10-1). In this

mode, the internal voltage reference is applied to the

VIN+ pin of both comparators.

10.4 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is to have a valid level. If the internal

reference is changed, the maximum delay of the internal

voltage reference must be considered when using the

comparator outputs. Otherwise, the maximum delay of

the comparators should be used (Table 17-2, page 142).

FLAG_REG EQU 0X20

CLRF FLAG_REG ;Init flag register

CLRF PORTA ;Init PORTA

MOVF CMCON, W ;Load comparator bits

ANDLW 0xC0 ;Mask comparator bits

IORWF FLAG_REG,F ;Store bits in flag register

MOVLW 0x03 ;Init comparator mode

MOVWF CMCON ;CM<2:0> = 011

BSF STATUS,RP0 ;Select Bank1

MOVLW 0x07 ;Initialize data direction

MOVWF TRISA ;Set RA<2:0> as inputs

;RA<4:3> as outputs

;TRISA<7:5> always read ‘0’

BCF STATUS,RP0 ;Select Bank 0

CALL DELAY10 ;10Μs delay

MOVF CMCON,F ;Read CMCON to end change

;condition

BCF PIR1,CMIF ;Clear pending interrupts

BSF STATUS,RP0 ;Select Bank 1

BSF PIE1,CMIE ;Enable comparator interrupts

BCF STATUS,RP0 ;Select Bank 0

BSF INTCON,PEIE ;Enable peripheral interrupts

BSF INTCON,GIE ;Global interrupt enable

–

VIN+

VIN-

Result

VIN-

VIN+

PIC16F627A/628A/648A

10.5 Comparator Outputs

The comparator outputs are read through the CMCON

outputs may also be directly output to the RA3 and RA4

I/O pins. When the CM<2:0> = 110 or 001, multiplexors

in the output path of the RA3 and RA4/T0CK1/CMP2

pins will switch and the output of each pin will be the

unsynchronized output of the comparator. The

uncertainty of each of the comparators is related to the

input offset voltage and the response time given in the

specifications. Figure 10-3 shows the comparator output

block diagram.

The TRISA bits will still function as an output enable/

disable for the RA3/AN3/CMP1 and RA4/T0CK1/

CMP2 pins while in this mode.

FIGURE 10-3: MODIFIE D COMPARATOR OUTPUT BLOCK DIAGRAM

Note 1: When reading the PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input, according to the

Schmitt Trigger input specification.

2: Analog levels on any pin that is defined as

a digital input may cause the input buffer

to consume more current than is

specified.

To RA3/AN3/CMP1 or

Set CMIF bit DQ

Reset

From other Comparator

To Data B u s

CnVOUT

CnINV

RD CMCON

CMCON<7:6>

RA4/T0CK1/CMP2 pin

PIC16F627A/628A/648A

10.6 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<6>, is the comparator interrupt flag.

The CMIF bit must be reset by clearing ‘0’. Since it is

also possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

The CMIE bit (PIE1<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit must also be set. If any of these

bits are clear, the interrupt is not enabled, though the

CMIF bit will still be set if an interrupt condition occurs.

The user, in the interrupt service routine, can clear the

interrupt in the following manner:

a) Any write or read of CMCON. This will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

10.7 Comparator Operation During

Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional if enabled. This interrupt will

wake-up the device from Sleep mode when enabled.

While the comparator is powered-up, higher Sleep

currents than shown in the power-down current

specification will occur. Each comparator that is

operational will consume additional current as shown in

the comparator specifications. To minimize power

consumption while in Sleep mode, turn off the

comparators, CM<2:0> = 111, before entering Sleep. If

the device wakes up from Sleep, the contents of the

CMCON register are not affected.

10.8 Effect s of a Reset

A device Reset forces the CMCON register to its Reset

state. This forces the Comparator module to be in the

comparator Reset mode, CM<2:0> = 000. This ensures

that all potential inputs are analog inputs. Device current

is minimized when analog inputs are present at Reset

time. The comparators will be powered-down during the

Reset interval.

10.9 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 10-4. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum source impedance of 10 kΩ is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR1<6>)

interrupt flag may not get set.

PIC16F627A/628A/648A

FIGURE 10-4: ANALOG INPUT MODE

TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

Resets

1Fh CMCON C2OUT C1OUT C2INV C1NV CIS CM2 CM1 CM0 0000 0000 0000 0000

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: x = Unknown, u = Unchanged, - = Unimplemented, read as ‘0’

RS < 10 K

AIN

CPIN

5pF

VDD

VT = 0.6V

RIC

ILEAKAGE

±500 nA

VSS

Legend: CPIN = Input Capacitance

VT= Threshold Voltage

ILEAKAGE = Leakage Current at the Pin

RIC = Interconnect Resistance

RS= Source Impedance

VA = Analog Voltage

PIC16F627A/628A/648A

11.0 VOLTAGE REFERENCE

MODULE

The Voltage Reference module consists of a 16-tap

resistor ladder network that provides a selectable volt-

age reference. The resistor ladder is segmented to pro-

vide two ranges of VREF values and has a power-down

function to conserve power when the reference is not

being used. The VRCON register controls the opera-

tion of the reference as shown in Figure 11-1. The

block diagram is given in Figure 11-1.

11.1 Voltage Reference Configuration

The Voltage Reference module can output 16 distinct

voltage levels for each range.

The equations used to calculate the output of the

Voltage Reference module are as follows:

if VRR = 1:

if VRR = 0:

The setting time of the Voltage Reference module must

be considered when changing the VREF output

(Table 17-3). Example 11-1 demonstrates how voltage

reference is configured for an output voltage of 1.25V

with VDD = 5.0V.

VREF VR<3:0>

-----------------------V

VREF VDD 1

---

⎝⎠

⎛⎞

VR<3:0>

-----------------------+V

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN VROE VRR — VR3 VR2 VR1 VR0

bit 7 bit 0

bit 7 VREN: VREF Enable bit

1 = VREF circuit powered on

0 = VREF circuit powered down, no IDD drain

bit 6 VROE: VREF Output Enable bit

1 = VREF is output on RA2 pin

0 = VREF is disconnected from RA2 pin

bit 5 VRR: VREF Range Selection bit

1 = Low range

0 = High range

bit 4 Unimplemented: Read as ‘0’

bit 3-0 VR<3:0>: VREF Value Selection bits 0 ≤ VR <3:0> ≤ 15

When VRR = 1: VREF = (VR<3:0>/ 24) * VDD

When VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM

EXAMPLE 11-1: VOLTAGE REFERENCE

CONFIGURATION

11.2 Voltage Reference Accuracy/Error

The full range of VSS to VDD cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 11-1) keep VREF from approaching VSS or VDD.

The Voltage Reference module is VDD derived and

therefore, the VREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Voltage Ref-

erence module can be found in Table 17-3.

11.3 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time out, the contents of

the VRCON register are not affected. To minimize

current consumption in Sleep mode, the Voltage

Reference module should be disabled.

11.4 Effects of a Reset

A device Reset disables the Voltage Reference module

by clearing bit VREN (VRCON<7>). This Reset also

disconnects the reference from the RA2 pin by clearing

bit VROE (VRCON<6>) and selects the high voltage

range by clearing bit VRR (VRCON<5>). The VREF

value select bits, VRCON<3:0>, are also cleared.

11.5 Connection Considerations

The Voltage Reference module operates independently

of the Comparator module. The output of the reference

generator may be connected to the RA2 pin if the

TRISA<2> bit is set and the VROE bit, VRCON<6>, is

set. Enabling the Voltage Reference module output onto

the RA2 pin with an input signal present will increase

current consumption. Connecting RA2 as a digital output

with VREF enabled will also increase current consump-

tion.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited drive

capability, a buffer must be used in conjunction with the

Voltage Reference module output for external connec-

tions to VREF. Figure 11-2 shows an example buffering

technique.

Note: R is defined in Table 17-3.

VRR

VR3

VR0

(From VRCON<3:0>)

16-1 Analog Mux

8R RRRR

VREN

VREF

16 Stages

VDD

VSS VSS

MOVLW 0x02 ;4 Inputs Muxed

MOVWF CMCON ;to 2 comps.

BSF STATUS,RP0 ;go to Bank 1

MOVLW 0x07 ;RA3-RA0 are

MOVWF TRISA ;outputs

MOVLW 0xA6 ;enable VREF

MOVWF VRCON ;low range set VR<3:0>=6

BCF STATUS,RP0 ;go to Bank 0

CALL DELAY10 ;10μs delay

PIC16F627A/628A/648A

FIGURE 11 -2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 11-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value On

POR

Value On

All Other

Resets

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000

1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: - = Unimplemented, read as ‘0’.

Note 1: R is dependent upon the voltage reference configuration VRCON<3:0> and VRCON<5>.

VREF

Module

R(1)

Voltage

Reference

Output

Impedance

RA2

VREF Output

Op Amp

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

12.0 UNIVERSAL SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

MODULE

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) is also known as a Serial

Communications Interface (SCI). The USART can be

configured as a full-duplex asynchronous system that

can communicate with peripheral devices such as CRT

terminals and personal computers, or it can be

configured as a half-duplex synchronous system that

can communicate with peripheral devices such as A/D

or D/A integrated circuits, Serial EEPROMs, etc.

The USART can be configured in the following modes:

• Asynchronous (full-duplex)

• Synchronous – Master (half-duplex)

• Synchronous – Slave (half-duplex)

Bit SPEN (RCSTA<7>) and bits TRISB<2:1> have to be

set in order to configure pins RB2/TX/CK and RB1/RX/DT

as the Universal Synchronous Asynchronous Receiver

Transmitter.

Receive Status and Control Register (RCSTA).

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN SYNC — BRGH TRMT TX9D

bit 7 bit 0

bit 7 CSRC: Clock Source Select bit

Asynchronous mode

Don’t care

Synchronous mode

1 = Master mode (Clock generated internally from BRG)

0 = Slave mode (Clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: USART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 Unimplemented: Read as ‘0’

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode

1 = High speed

0 = Low speed

Synchronous mode

Unused in this mode

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th bit of transmit data. Can be parity bit.

Note 1: SREN/CREN overrides TXEN in SYNC mode.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADEN FERR OERR RX9D

bit 7 bit 0

bit 7 SPEN: Serial Port Enable bit

(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set)

1 = Serial port enabled

0 = Serial port disabled

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode - master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode - slave:

Unused in this mode

bit 4 CREN: Continuous Receive Enable bit

Asynchronous mode:

1 = Enables continuous receive

0 = Disables continuous receive

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8>

is set

0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Unused in this mode

Synchronous mode

Unused in this mode

bit 2 FERR: Framing Error bit

1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (Can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: 9th bit of received data (Can be parity bit)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

12.1 USART Baud Rate Generator

(BRG)

The BRG supports both the Asynchronous and

Synchronous modes of the USART. It is a dedicated

8-bit baud rate generator. The SPBRG register

controls the period of a free running 8-bit timer. In

Asynchronous mode, bit BRGH (TXSTA<2>) also

controls the baud rate. In Synchronous mode, bit

BRGH is ignored. Table 12-1 shows the formula for

computation of the baud rate for different USART

modes, which only apply in Master mode (internal

clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRG register can be calculated

using the formula in Table 12-1. From this, the error in

baud rate can be determined.

Example 12-1 shows the calculation of the baud rate

error for the following conditions:

FOSC = 16 MHz

Desired Baud Rate = 9600

BRGH = 0

SYNC = 0

EQUATION 12-1: CALCULATING BAUD

RATE ERROR

It may be advantageous to use the high baud rate

(BRGH = 1) even for slower baud clocks. This is

because the FOSC/(16(X + 1)) equation can reduce the

baud rate error in some cases.

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared) and ensures the

BRG does not wait for a timer overflow before

outputting the new baud rate.

The data on the RB1/RX/DT pin is sampled three times

by a majority detect circuit to determine if a high or a

low level is present at the RX pin.

TABLE 12-1: BAUD RATE FORMULA

TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Desired Baud Rate Fosc

64 x 1+()

-----------------------=

9600 16000000

64 x 1+()

------------------------=

x25.042=

Calcula ted Baud Rat e 16000000

64 25 1+()

---------------------------9615==

Error (Calculated Baud Rate - Desired Baud Rate)

Desired Baud Rate

-----------------------------------------------------------------------------------------------------------=

= 9615 9600–

9600

------------------------------0.16%=

SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)

0(Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1))

1(Synchronous) Baud Rate = FOSC/(4(X+1)) NA

Legend: X = value in SPBRG (0 to 255)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Value on all

other Resets

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the BRG.

PIC16F627A/628A/648A

TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE

BAUD

RAT E (K)

FOSC = 20 MHz SPBRG

value

(decimal)

16 MHz SPBRG

value

(decimal)

10 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3NA— —NA— —NA— —

1.2NA— —NA— —NA— —

2.4NA— —NA— —NA— —

9.6 NA — — NA — — 9.766 +1.73% 255

19.2 19.53 +1.73% 255 19.23 +0.16% 207 19.23 +0.16% 129

76.8 76.92 +0.16% 64 76.92 +0.16% 51 75.76 -1.36% 32

96 96.15 +0.16% 51 95.24 -0.79% 41 96.15 +0.16% 25

300 294.1 -1.96 16 307.69 +2.56% 12 312.5 +4.17% 7

500 500 0 9 500 0 7 500 0 4

HIGH 5000 — 0 4000 — 0 2500 — 0

LOW 19.53 — 255 15.625 — 255 9.766 — 255

BAUD

RAT E (K)

FOSC = 7.15909 MHz SPBRG

value

(decimal)

5.0688 MHz SPBRG

value

(decimal)

4 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3NA— —NA— —NA— —

1.2NA— —NA— —NA— —

2.4NA— —NA— —NA— —

9.6 9.622 +0.23% 185 9.6 0 131 9.615 +0.16% 103

19.2 19.24 +0.23% 92 19.2 0 65 19.231 +0.16% 51

76.8 77.82 +1.32 22 79.2 +3.13% 15 75.923 +0.16% 12

96 94.20 -1.88 18 97.48 +1.54% 12 1000 +4.17% 9

300 298.3 -0.57 5 316.8 5.60% 3 NA ——

500 NA — — NA ——NA— —

HIGH 1789.8 — 0 1267 — 0 100 — 0

LOW 6.991 — 255 4.950 — 255 3.906 — 255

BAUD

RAT E (K)

FOSC = 3.579545 MHz SPBRG

value

(decimal)

1 MHz SPBRG

value

(decimal)

32.768 kHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3 NA — — NA — — 0.303 +1.14% 26

1.2 NA — — 1.202 +0.16% 207 1.170 -2.48% 6

2.4 NA — — 2.404 +0.16% 103 NA ——

9.6 9.622 +0.23% 92 9.615 +0.16% 25 NA — —

19.2 19.04 -0.83% 46 19.24 +0.16% 12 NA — —

76.8 74.57 -2.90% 11 83.34 +8.51% 2 NA — —

96 99.43 +3.57% 8 NA ——

NA ——

300 298.3 0.57% 2 NA — — NA — —

500 NA ——NA— —NA— —

HIGH 894.9 — 0 250 — 0 8.192 — 0

LOW 3.496 — 255 0.9766 — 255 0.032 — 255

PIC16F627A/628A/648A

TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

BAUD

RATE (K)

FOSC = 20 MHz SPBRG

value

(decimal)

16 MHz SPBRG

value

(decimal)

10 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3NA——NA ——NA ——

1.2 1.221 +1.73% 255 1.202 +0.16% 207 1.202 +0.16% 129

2.4 2.404 +0.16% 129 2.404 +0.16% 103 2.404 +0.16% 64

9.6 9.469 -1.36% 32 9.615 +0.16% 25 9.766 +1.73% 15

19.2 19.53 +1.73% 15 19.23 +0.16% 12 19.53 +1.73V 7

76.8 78.13 +1.73% 3 83.33 +8.51% 2 78.13 +1.73% 1

96 104.2 +8.51% 2 NA — — NA — —

300 312.5 +4.17% 0 NA — — NA — —

500 NA — — NA — — NA — —

HIGH 312.5 — 0 250 — 0 156.3 — 0

LOW 1.221 — 255 0.977 — 255 0.6104 — 255

BAUD

RATE (K)

FOSC = 7.15909 MHz S PBRG

value

(decimal)

5.0688 MHz SPBRG

value

(decimal)

4 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3 NA — — 0.31 +3.13% 255 0.3005 -0.17% 207

1.2 1.203 +0.23% 92 1.2 0 65 1.202 +1.67% 51

2.4 2.380 -0.83% 46 2.4 0 32 2.404 +1.67% 25

9.6 9.322 -2.90% 11 9.9 +3.13% 7 NA — —

19.2 18.64 -2.90% 5 19.8 +3.13% 3 NA — —

76.8 NA — — 79.2 +3.13% 0 NA — —

96 NA — — NA — — NA — —

300 NA — — NA — — NA — —

500 NA — — NA — — NA — —

HIGH 111.9 — 0 79.2 — 0 62.500 — 0

LOW 0.437 — 255 0.3094 — 255 3.906 — 255

BAUD

RATE (K)

FOSC = 3.579545 MHz SPBRG

value

(decimal)

1 MHz SPBRG

value

(decimal)

32.768 kHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3 0.301 +0.23% 185 0.300 +0.16% 51 0.256 -14.67% 1

1.2 1.190 -0.83% 46 1.202 +0.16% 12 NA — —

2.4 2.432 +1.32% 22 2.232 -6.99% 6 NA — —

9.6 9.322 -2.90% 5 NA — — NA — —

19.2 18.64 -2.90% 2 NA — — NA — —

76.8NA— —NA— —NA— —

96 NA — — NA — — NA — —

300 NA — — NA — — NA — —

500 NA — — NA — — NA — —

HIGH 55.93 — 0 15.63 — 0 0.512 — 0

LOW 0.2185 — 255 0.0610 — 255 0.0020 — 255

PIC16F627A/628A/648A

TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

BAUD

RAT E (K)

FOSC = 20 MHz SPBRG

value

(decimal)

16 MHz SPBRG

value

(decimal)

10 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

9600 9.615 +0.16% 129 9.615 +0.16% 103 9.615 +0.16% 64

19200 19.230 +0.16% 64 19.230 +0.16% 51 18.939 -1.36% 32

38400 37.878 -1.36% 32 38.461 +0.16% 25 39.062 +1.7% 15

57600 56.818 -1.36% 21 58.823 +2.12% 16 56.818 -1.36% 10

115200 113.636 -1.36% 10 111.111 -3.55% 8 125 +8.51% 4

250000 250 0 4 250 0 3 NA — —

625000 625 0 1 NA — — 625 0 0

1250000 1250 0 0 NA — — NA — —

BAUD

RAT E (K)

FOSC = 7.16 MHz SPBRG

value

(decimal)

5.068 MHz SPBRG

value

(decimal)

4 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

9600 9.520 -0.83% 46 9598.485 0.016% 32 9615.385 0.160% 25

19200 19.454 +1.32% 22 18632.35 -2.956% 16 19230.77 0.160% 12

38400 37.286 -2.90% 11 39593.75 3.109% 7 35714.29 -6.994% 6

57600 55.930 -2.90% 7 52791.67 -8.348% 5 62500 8.507% 3

115200 111.860 -2.90% 3 105583.3 -8.348% 2 125000 8.507% 1

250000 NA — — 316750 26.700% 0 250000 0.000% 0

625000 NA — — NA — — NA — —

1250000 NA — — NA — — NA — —

BAUD

RAT E (K)

FOSC = 3.579 MHz SPBRG

value

(decimal)

1 MHz SPBRG

value

(decimal)

32.768 kHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

9600 9725.543 1.308% 22 8.928 -6.994% 6 NA NA NA

19200 18640.63 -2.913% 11 20833.3 8.507% 2 NA NA NA

38400 37281.25 -2.913% 5 31250 -18.620% 1 NA NA NA

57600 55921.88 -2.913% 3 62500 +8.507 0 NA NA NA

115200 111243.8 -2.913% 1 NA — — NA NA NA

250000 223687.5 -10.525% 0 NA — — NA NA NA

625000 NA — — NA — — NA NA NA

1250000 NA — — NA — — NA NA NA

PIC16F627A/628A/648A

12.2 USART Asynchronous Mode

In this mode, the USART uses standard non-return-to-

zero (NRZ) format (one Start bit, eight or nine data bits

and one Stop bit). The most common data format is

8-bit. A dedicated 8-bit baud rate generator is used to

derive baud rate frequencies from the oscillator. The

USART transmits and receives the LSb first. The

USART’s transmitter and receiver are functionally

independent, but use the same data format and baud

rate. The baud rate generator produces a clock either

x16 or x64 of the bit shift rate, depending on bit BRGH

(TXSTA<2>). Parity is not supported by the hardware,

but can be implemented in software (and stored as the

ninth data bit). Asynchronous mode is stopped during

Sleep.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

The USART Asynchronous module consists of the

following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

12.2.1 USART ASYNCHRONOUS

TRANSMITTER

The USART transmitter block diagram is shown in

Figure 12-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the Stop bit has been

transmitted from the previous load. As soon as the Stop

bit is transmitted, the TSR is loaded with new data from

the TXREG register (if available). Once the TXREG

in one TCY), the TXREG register is empty and flag bit

TXIF (PIR1<4>) is set. This interrupt can be enabled/

disabled by setting/clearing enable bit TXIE

( PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register. While flag bit TXIF indicated the

status of the TXREG register, another bit TRMT

(TXSTA<1>) shows the status of the TSR register.

Status bit TRMT is a read-only bit which is set when the

TSR register is empty. No interrupt logic is tied to this

bit, so the user has to poll this bit in order to determine

if the TSR register is empty.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data

and the Baud Rate Generator (BRG) has produced a

shift clock (Figure 12-1). The transmission can also be

started by first loading the TXREG register and then

setting enable bit TXEN. Normally when transmission

is first started, the TSR register is empty, so a transfer

to the TXREG register will result in an immediate

transfer to TSR resulting in an empty TXREG. A back-

to-back transfer is thus possible (Figure 12-3). Clearing

enable bit TXEN during a transmission will cause the

transmission to be aborted and will reset the

transmitter. As a result the RB2/TX/CK pin will revert to

high-impedance.

In order to select 9-bit transmission, transmit bit TX9

(TXSTA<6>) should be set and the ninth bit should be

written to TX9D (TXSTA<0>). The ninth bit must be

written before writing the 8-bit data to the TXREG

to the TSR register (if the TSR is empty). In such a

case, an incorrect ninth data bit may be loaded in the

TSR register.

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

PIC16F627A/628A/648A

FIGURE 12-1: USART TRANSMIT BLOCK DIAGRAM

Follow these steps when setting up an Asynchronous

Transmission:

1. TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

2. Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH. (Section 12.1 “USART Baud

Rate Generator (BRG)”).

3. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

4. If interrupts are desired, then set enable bit

TXIE.

5. If 9-bit transmission is desired, then set transmit

bit TX9.

6. Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. Load data to the TXREG register (starts

transmission).

FIGURE 12-2: ASY NCHR ON OUS TRANSMISSION

TXIF

TXIE

Interrupt

TXEN Baud Rate CLK

SPBRG

Baud Rate Generator

TX9D

MSb LSb

Data Bus

TXREG register

TSR register

(8) 0

TX9

TRMT SPEN

RB2/TX/CK pin

Pin Buffer

and Control

² ² ²

Word 1

Stop bit

Word 1

Transmit Shift Reg.

Start bit bit 0 bit 1 bit 7/8

Write to TXREG

Word 1

BRG output

(shift clock)

RB2/TX/CK (pin)

TXIF bit

(Transmit buffer

reg. empty flag)

TRMT bit

(Transmit shift

reg. empty flag)

PIC16F627A/628A/648A

FIGURE 12-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USART Transmit Data Register 0000 0000 0000 0000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented locations read as ‘0’.

Shaded cells are not used for Asynchronous Transmission.

Transmit Shift Reg.

Write to TXREG

BRG output

(shift clock)

RB2/TX/CK (pin)

TXIF bit

(interrupt reg. flag)

TRMT bit

(Transmit shift

reg. empty flag)

Word 1 Word 2

Start bit Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

PIC16F627A/628A/648A

12.2.2 USART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 12-4.

The data is received on the RB1/RX/DT pin and drives

the data recovery block. The data recovery block is

actually a high-speed shifter operating at x16 times the

baud rate, whereas the main receive serial shifter

operates at the bit rate or at FOSC.

When Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

The heart of the receiver is the Receive (serial) Shift

received data in the RSR is transferred to the RCREG

bit RCIF (PIR1<5>) is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read-only bit, which is

cleared by the hardware. It is cleared when the RCREG

double buffered register (i.e., it is a two-deep FIFO). It

is possible for two bytes of data to be received and

transferred to the RCREG FIFO and a third byte begin

shifting to the RSR register. On the detection of the

Stop bit of the third byte, if the RCREG register is still

full, then overrun error bit OERR (RCSTA<1>) will be

set. The word in the RSR will be lost. The RCREG

the FIFO. Overrun bit OERR has to be cleared in soft-

ware. This is done by resetting the receive logic (CREN

is cleared and then set). If bit OERR is set, transfers

from the RSR register to the RCREG register are inhib-

ited, so it is essential to clear error bit OERR if it is set.

Framing error bit FERR (RCSTA<2>) is set if a Stop bit

is detected as clear. Bit FERR and the 9th receive bit

are buffered the same way as the receive data. Read-

ing the RCREG, will load bits RX9D and FERR with

new values, therefore it is essential for the user to read

the RCSTA register before reading RCREG register in

order not to lose the old FERR and RX9D information.

FIGURE 12-4: USA R T RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RB1/RX/DT

Pin Buffer

and Control

SPEN

Data

Recovery

CREN

OERR FERR

RSR register

MSb LSb

RX9D RCREG register FIFO

Interrupt RCIF

RCIE

Data Bus

÷ 64

÷ 16

Stop Start

(8) 710

RX9

• • •

RX9

ADEN

RX9

ADEN

RSR<8>

Enable

Load of

Receive

Buffer

RCREG register

RX9D

PIC16F627A/628A/648A

FIGURE 12-5: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT

FIGURE 12-6: ASY NCHR ON OUS RECEPT ION WITH ADDRESS BYTE FIRST

FIGURE 12-7: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY

VALID DATA BYTE

Start

bit bit 1bit 0 bit 8 bit 0Stop

bit

Start

bit bit 8 Stop

bit

RB1/RX/DT (Pin)

RCV Buffer Reg

RCV Shift Reg

Read RCV

Buffer Reg

RCREG

RCIF

(interrupt flag)

Word 1

RCREG

bit 8 = 0, Data Byte bit 8 = 1, Address Byte

ADEN = 1

(Address Match

Enable)

‘1’ ‘1’

Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG

(Receive Buffer) because ADEN = 1 and bit 8 = 0.

Start

bit bit 1bit 0 bit 8 bit 0Stop

bit

Start

bit bit 8 Stop

bit

RB1/RX/DT (pin)

RCV Buffer Reg

RCV Shift Reg

Read RCV

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

Word 1

RCREG

bit 8 = 1, Address Byte bit 8 = 0, Data Byte

ADEN = 1

(Address Match

Enable)

‘1’ ‘1’

Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG

(receive buffer) because ADEN was not updated (still = 1) and bit 8 = 0.

Start

bit bit 1bit 0 bit 8 bit 0Stop

bit

Start

bit bit 8 Stop

bit

RB1/RX/DT (pin)

Reg

RCV Buffer Reg

RCV Shift

Read RCV

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

Word 2

RCREG

bit 8 = 1, Address Byte bit 8 = 0, Data Byte

ADEN

(Address Match

Enable)

Word 1

RCREG

Note: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG

(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents

of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8.

PIC16F627A/628A/648A

Follow these steps when setting up an Asynchronous

Reception:

1. TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

2. Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH. (Section 12.1 “USART Baud

Rate Generator (BRG)”).

3. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

4. If interrupts are desired, then set enable bit

RCIE.

5. If 9-bit reception is desired, then set bit RX9.

6. Enable the reception by setting bit CREN.

7. Flag bit RCIF will be set when reception is

complete and an interrupt will be generated if

enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If an OERR error occurred, clear the error by

clearing enable bit CREN.

TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCREG USART Receive Data Register 0000 0000 0000 0000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

PIC16F627A/628A/648A

12.3 USART Address Detect Function

12.3.1 USART 9-BIT RECEIVER WITH

ADDRESS DETECT

When the RX9 bit is set in the RCSTA register, 9 bits

are received and the ninth bit is placed in the RX9D bit

of the RCSTA register. The USART module has a

special provision for multiprocessor communication.

Multiprocessor communication is enabled by setting

the ADEN bit (RCSTA<3>) along with the RX9 bit. The

port is now programmed such that when the last bit is

received, the contents of the Receive Shift Register

(RSR) are transferred to the receive buffer, the ninth bit

of the RSR (RSR<8>) is transferred to RX9D, and the

receive interrupt is set if and only if RSR<8> = 1. This

feature can be used in a multiprocessor system as

follows:

A master processor intends to transmit a block of data

to one of many slaves. It must first send out an address

byte that identifies the target slave. An address byte is

identified by setting the ninth bit (RSR<8>) to a ‘1’

(instead of a ‘0’ for a data byte). If the ADEN and RX9

bits are set in the slave’s RCSTA register, enabling

multiprocessor communication, all data bytes will be

ignored. However, if the ninth received bit is equal to a

‘1’, indicating that the received byte is an address, the

slave will be interrupted and the contents of the RSR

allows the slave to be interrupted only by addresses, so

that the slave can examine the received byte to see if it

is being addressed. The addressed slave will then clear

its ADEN bit and prepare to receive data bytes from the

master.

When ADEN is enabled (= 1), all data bytes are

ignored. Following the Stop bit, the data will not be

loaded into the receive buffer, and no interrupt will

occur. If another byte is shifted into the RSR register,

the previous data byte will be lost.

The ADEN bit will only take effect when the receiver is

configured in 9-bit mode (RX9 = 1). When ADEN is

disabled (= 0), all data bytes are received and the 9th

bit can be used as the parity bit.

The receive block diagram is shown in Figure 12-4.

Reception is enabled by setting bit CREN

(RCSTA<4>).

12.3.1.1 Setting up 9-bit mode with Address

Detect

Follow these steps when setting up Asynchronous

Reception with Address Detect Enabled:

1. TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

2. Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH.

3. Enable asynchronous communication by setting

or clearing bit SYNC and setting bit SPEN.

4. If interrupts are desired, then set enable bit

RCIE.

5. Set bit RX9 to enable 9-bit reception.

6. Set ADEN to enable address detect.

7. Enable the reception by setting enable bit CREN

or SREN.

8. Flag bit RCIF will be set when reception is

complete and an interrupt will be generated if

enable bit RCIE was set.

9. Read the 8-bit received data by reading the

RCREG register to determine if the device is

being addressed.

10. If an OERR error occurred, clear the error by

clearing enable bit CREN if it was already set.

11. If the device has been addressed (RSR<8> = 1

with address match enabled), clear the ADEN

and RCIF bits to allow data bytes and address

bytes to be read into the receive buffer and

interrupt the CPU.

TABLE 12-8: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Address N ame Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCREG USART Receive Data Register 0000 0000 0000 0000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous

reception.

PIC16F627A/628A/648A

12.4 USART Synchronous Master

Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner (i.e., transmission and reception

do not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition enable bit SPEN (RCSTA<7>) is set in order to

configure the RB2/TX/CK and RB1/RX/DT I/O pins to

CK (clock) and DT (data) lines, respectively. The

Master mode indicates that the processor transmits the

master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA<7>).

12.4.1 USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 12-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one Tcycle), the TXREG is empty and

interrupt bit, TXIF (PIR1<4>) is set. The interrupt can

be enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register. While flag bit TXIF indicates the

status of the TXREG register, another bit TRMT

(TXSTA<1>) shows the status of the TSR register.

TRMT is a read-only bit which is set when the TSR is

empty. No interrupt logic is tied to this bit, so the user

has to poll this bit in order to determine if the TSR

memory so it is not available to the user.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data.

The first data bit will be shifted out on the next available

rising edge of the clock on the CK line. Data out is

stable around the falling edge of the synchronous clock

(Figure 12-8). The transmission can also be started by

first loading the TXREG register and then setting bit

TXEN (Figure 12-9). This is advantageous when slow

baud rates are selected, since the BRG is kept in Reset

when bits TXEN, CREN and SREN are clear. Setting

enable bit TXEN will start the BRG, creating a shift

clock immediately. Normally, when transmission is first

started, the TSR register is empty, so a transfer to the

TXREG register will result in an immediate transfer to

TSR resulting in an empty TXREG. Back-to-back

transfers are possible.

Clearing enable bit TXEN during a transmission will

cause the transmission to be aborted and will reset the

transmitter. The DT and CK pins will revert to high-

impedance. If either bit CREN or bit SREN is set during

a transmission, the transmission is aborted and the DT

pin reverts to a high-impedance state (for a reception).

The CK pin will remain an output if bit CSRC is set

(internal clock). The transmitter logic however is not

reset although it is disconnected from the pins. In order

to reset the transmitter, the user has to clear bit TXEN.

If bit SREN is set (to interrupt an on-going transmission

and receive a single word), then after the single word is

received, bit SREN will be cleared and the serial port

will revert back to transmitting since bit TXEN is still set.

The DT line will immediately switch from high-imped-

ance Receive mode to transmit and start driving. To

avoid this, bit TXEN should be cleared.

In order to select 9-bit transmission, the TX9

(TXSTA<6>) bit should be set and the ninth bit should

be written to bit TX9D (TXSTA<0>). The ninth bit must

be written before writing the 8-bit data to the TXREG

result in an immediate transfer of the data to the TSR

the TXREG was written before writing the “new” TX9D,

the “present” value of bit TX9D is loaded.

Follow these steps when setting up a Synchronous

Master Transmission:

1. TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

2. Initialize the SPBRG register for the appropriate

baud rate (Section 12.1 “USART Baud Rate

Generator (BRG)”).

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

4. If interrupts are desired, then set enable bit

TXIE.

5. If 9-bit transmission is desired, then set bit TX9.

6. Enable the transmission by setting bit TXEN.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. Start each transmission by loading data to the

TXREG register.

PIC16F627A/628A/648A

TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

FIGURE 12-8: SY NCHRO NOUS TRANSMISSION

FIGURE 12-9: SY NCHRONOUS TRANSMISSION (THROUGH TXEN)

Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Value on all

other Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USART Transmit Data Register 0000 0000 0000 0000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

bit 0 bit 1 bit 7

Word 1

Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4

bit 2 bit 0 bit 1 bit 7

RB1/RX/DT pin

RB2/TX/CK pin

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TRMT

TXEN bit

‘1’‘1’

Word 2

TRMT bit

Write Word 1 Write Word 2

Note: Sync Master Mode; SPBRG = 0. Continuous transmission of two 8-bit words.

RB1/RX/DT pin

RB2/TX/CK pin

Write to

TXREG Reg

TXIF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bit

PIC16F627A/628A/648A

12.4.2 USART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either enable bit SREN

(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is

sampled on the RB1/RX/DT pin on the falling edge of

the clock. If enable bit SREN is set, then only a single

word is received. If enable bit CREN is set, the recep-

tion is continuous until CREN is cleared. If both bits are

set, then CREN takes precedence. After clocking the

last bit, the received data in the Receive Shift Register

(RSR) is transferred to the RCREG register (if it is

empty). When the transfer is complete, interrupt flag bit

RCIF (PIR1<5>) is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read-only bit which is

reset by the hardware. In this case, it is reset when the

RCREG register has been read and is empty. The

RCREG is a double buffered register (i.e., it is a two-

deep FIFO). It is possible for two bytes of data to be

received and transferred to the RCREG FIFO and a

third byte to begin shifting into the RSR register. On the

clocking of the last bit of the third byte, if the RCREG

(RCSTA<1>) is set. The word in the RSR will be lost.

The RCREG register can be read twice to retrieve the

two bytes in the FIFO. Bit OERR has to be cleared in

software (by clearing bit CREN). If bit OERR is set,

transfers from the RSR to the RCREG are inhibited, so

it is essential to clear bit OERR if it is set. The 9th

receive bit is buffered the same way as the receive

data. Reading the RCREG register, will load bit RX9D

with a new value, therefore it is essential for the user to

read the RCSTA register before reading RCREG in

order not to lose the old RX9D information.

Follow these steps when setting up a Synchronous

Master Reception:

1. TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

2. Initialize the SPBRG register for the appropriate

baud rate. (Section 12.1 “USART Baud Rate

Generator (BRG)”).

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

4. Ensure bits CREN and SREN are clear.

5. If interrupts are desired, then set enable bit

RCIE.

6. If 9-bit reception is desired, then set bit RX9.

7. If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.

8. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

enable bit RCIE was set.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an OERR error occurred, clear the error by

clearing bit CREN.

TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR Value on all

other Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCREG USART Receive Data Register 0000 0000 0000 0000

8Ch PIE1 EPIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE -000 0000 -000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.

PIC16F627A/628A/648A

FIGURE 12-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

12.5 USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RB2/TX/CK pin (instead of being supplied internally

in Master mode). This allows the device to transfer or

receive data while in Sleep mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

12.5.1 USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical except in the case of the Sleep

mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from Sleep and if the global interrupt is

enabled, the program will branch to the interrupt

vector (0004h).

Follow these steps when setting up a Synchronous

Slave Transmission:

1. TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

2. Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

3. Clear bits CREN and SREN.

4. If interrupts are desired, then set enable bit

TXIE.

5. If 9-bit transmission is desired, then set bit TX9.

6. Enable the transmission by setting enable bit

TXEN.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. Start transmission by loading data to the TXREG

CREN bit

RB1/RX/DT pin

RB2/TX/CK pin

WRITE to

Bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q2 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1 Q2Q3Q4

‘0’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘0’

Q1Q2Q3Q4

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.

PIC16F627A/628A/648A

12.5.2 USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical except in the case of the Sleep

mode. Also, bit SREN is a “don’t care” in Slave mode.

If receive is enabled by setting bit CREN prior to the

SLEEP instruction, then a word may be received during

Sleep. On completely receiving the word, the RSR

and if enable bit RCIE bit is set, the interrupt generated

will wake the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt vector

(0004h).

Follow these steps when setting up a Synchronous

Slave Reception:

1. TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

2. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

3. If interrupts are desired, then set enable bit

RCIE.

4. If 9-bit reception is desired, then set bit RX9.

5. To enable reception, set enable bit CREN.

6. Flag bit RCIF will be set when reception is

complete and an interrupt will be generated, if

enable bit RCIE was set.

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG register.

9. If an OERR error occurred, clear the error by

clearing bit CREN.

TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Value on all

other R esets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USART Transmit Data Register 0000 0000 0000 0000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Value on all

other Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCREG USART Receive Data Register 0000 0000 0000 0000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.

PIC16F627A/628A/648A

13.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full VDD range). This memory

is not directly mapped in the register file space. Instead

it is indirectly addressed through the Special Function

Registers (SFRs). There are four SFRs used to read

and write this memory. These registers are:

• EECON1

• EECON2 (Not a physically implemented register)

• EEDATA

• EEADR

EEDATA holds the 8-bit data for read/write and EEADR

holds the address of the EEPROM location being

accessed. PIC16F627A/628A devices have 128 bytes

of data EEPROM with an address range from 0h to

7Fh. The PIC16F648A device has 256 bytes of data

EEPROM with an address range from 0h to FFh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature, as well as

from chip-to-chip. Please refer to AC specifications for

exact limits.

When the device is code-protected, the CPU can

continue to read and write the data EEPROM memory. A

device programmer can no longer access this memory.

Additional information on the data EEPROM is

available in the PIC® Mid-Range Reference Manual

(DS33023).

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

bit 7-0 EEDATn: Byte value to Write to or Read from data EEPROM memory location.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EADR7 EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0

bit 7 bit 0

bit 7 PIC16F627A/628A

Unimplemented Address: Must be set to ‘0’

PIC16F648A

EEADR: Set to ‘1’ specifies top 128 locations (128-255) of EEPROM Read/Write Operation

bit 6-0 EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

13.1 EEADR

The PIC16F648A EEADR register addresses 256

bytes of data EEPROM. All eight bits in the register

(EEADR<7:0>) are required.

The PIC16F627A/628A EEADR register addresses

only the first 128 bytes of data EEPROM so only seven

of the eight bits in the register (EEADR<6:0>) are

required. The upper bit is address decoded. This

means that this bit should always be ‘0’ to ensure that

the address is in the 128 byte memory space.

13.2 EECON1 and EECON2 Registers

EECON1 is the control register with four low order bits

physically implemented. The upper-four bits are non-

existent and read as ‘0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time-out Reset during normal

operation. In these situations, following Reset, the user

can check the WRERR bit and rewrite the location. The

data and address will be unchanged in the EEDATA

and EEADR registers.

Interrupt flag bit EEIF in the PIR1 register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

— — — — WRERR WREN WR RD

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR Reset)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit

can only be set (not cleared) in software).

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

13.3 Reading the EEPROM Data

Memory

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD (EECON1<0>). The data is available, in the very

next cycle, in the EEDATA register; therefore it can be

read in the next instruction. EEDATA will hold this value

until another read or until it is written to by the user

(during a write operation).

EXAMPLE 13-1: DATA EEPROM READ

13.4 Writing to the EEPROM Data

Memory

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

specific sequence to initiate the write for each byte.

EXAMPLE 13-2: DATA EEPROM WRITE

The write will not initiate if the above sequence is not

followed exactly (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required sequence. Any number that is not equal to the

required cycles to execute the required sequence will

cause the data not to be written into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit in the

PIR1 registers must be cleared by software.

13.5 Wri te Veri fy

Depending on the application, good programming

practice may dictate that the value written to the Data

EEPROM should be verified (Example 13-3) to the

desired value to be written. This should be used in

applications where an EEPROM bit will be stressed

near the specification limit.

EXAMPL E 13-3: WRITE VERIFY

13.6 Protection Against Spurious W rite

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, WREN is cleared. Also

when enabled, the Power-up Timer (72 ms duration)

prevents EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch or software malfunction.

BSF STATUS, RP0 ;Bank 1

MOVLW CONFIG_ADDR ;

MOVWF EEADR ;Address to read

BSF EECON1, RD ;EE Read

MOVF EEDATA, W ;W = EEDATA

BCF STATUS, RP0 ;Bank 0

Required

Sequence

BSF STATUS, RP0 ;Bank 1

BSF EECON1, WREN ;Enable write

BCF INTCON, GIE ;Disable INTs.

BTFSC INTCON,GIE ;See AN576

GOTO $-2

MOVLW 55h ;

MOVWF EECON2 ;Write 55h

MOVLW AAh ;

MOVWF EECON2 ;Write AAh

BSF EECON1,WR ;Set WR bit

;begin write

BSF INTCON, GIE ;Enable INTs.

BSF STATUS, RP0 ;Bank 1

MOVF EEDATA, W

BSF EECON1, RD ;Read the

;value written

;

;Is the value written (in W reg) and

;read (in EEDATA) the same?

;

SUBWF EEDATA, W ;

BTFSS STATUS, Z ;Is difference 0?

GOTO WRITE_ERR ;NO, Write error

: ;YES, Good write

: ;Continue program

PIC16F627A/628A/648A

13.7 Using the Data EEPROM

The data EEPROM is a high endurance, byte

addressable array that has been optimized for the storage

of frequently changing information (e.g., program

variables or other data that are updated often). When

variables in one section change frequently, while

variables in another section do not change, it is possible

to exceed the total number of write cycles to the EEPROM

(specification D124) without exceeding the total number

of write cycles to a single byte (specifications D120 and

D120A). If this is the case, then an array refresh must be

performed. For this reason, variables that change

infrequently (such as constants, IDs, calibration, etc.)

should be stored in Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 13-4.

EXAMPLE 13-4: DATA EEPROM REFRESH ROUTINE

Note: If data EEPROM is only used to store

constants and/or data that changes rarely,

an array refresh is likely not required. See

specification D124.

BANKSEL 0X80 ;select Bank1

CLRF EEADR ;start at address 0

BCF INTCON, GIE ;disable interrupts

BTFSC INTCON, GIE ;see AN576

GOTO $ - 2

BSF EECON1, WREN ;enable EE writes

Loop

BSF EECON1, RD ;retrieve data into EEDATA

MOVLW 0x55 ;first step of ...

MOVWF EECON2 ;... required sequence

MOVLW 0xAA ;second step of ...

MOVWF EECON2 ;... required sequence

BSF EECON1, WR ;start write sequence

BTFSC EECON1, WR ;wait for write complete

GOTO $ - 1

#IFDEF __16F648A ;256 bytes in 16F648A

INCFSZ EEADR, f ;test for end of memory

#ELSE ;128 bytes in 16F627A/628A

INCF EEADR, f ;next address

BTFSS EEADR, 7 ;test for end of memory

#ENDIF ;end of conditional assembly

GOTO Loop ;repeat for all locations

BCF EECON1, WREN ;disable EE writes

BSF INTCON, GIE ;enable interrupts (optional)

PIC16F627A/628A/648A

13.8 Data EEPROM Operation During

Code-Protect

When the device is code-protected, the CPU is able to

read and write data to the data EEPROM.

TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

V alue on all

other

Resets

9Ah EEDATA EEPROM Data Register xxxx xxxx uuuu uuuu

9Bh EEADR EEPROM Address Register xxxx xxxx uuuu uuuu

9Ch EECON1 ———— WRERR WREN WR RD ---- x000 ---- q000

9Dh EECON2(1) EEPROM Control Register 2 ---- ---- ---- ----

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by data EEPROM.

Note 1: EECON2 is not a physical register.

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

14.0 SPECIAL FEATURES OF THE

CPU

Special circuits to deal with the needs of real-time

applications are what sets a microcontroller apart from

other processors. The PIC16F627A/628A/648A family

has a host of such features intended to maximize

system reliability, minimize cost through elimination of

external components, provide power-saving operating

modes and offer code protection.

These are:

1. OSC selection

2. Reset

3. Power-on Reset (POR)

4. Power-up Timer (PWRT)

5. Oscillator Start-Up Timer (OST)

6. Brown-out Reset (BOR)

7. Interrupts

8. Watchdog Timer (WDT)

9. Sleep

10. Code protection

11. ID Locations

12. In-Circuit Serial Programming™ (ICSP™)

The PIC16F627A/628A/648A has a Watchdog Timer

which is controlled by configuration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that offer necessary delays on power-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chip in Reset until the crystal oscillator is stable.

The other is the Power-up Timer (PWRT), which

provides a fixed delay of 72 ms (nominal) on power-up

only, designed to keep the part in Reset while the

power supply stabilizes. There is also circuitry to reset

the device if a brown-out occurs. With these three

functions on-chip, most applications need no external

Reset circuitry.

The Sleep mode is designed to offer a very low current

Power-down mode. The user can wake-up from Sleep

through external Reset, Watchdog Timer wake-up or

through an interrupt. Several oscillator options are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of configuration

bits are used to select various options.

14.1 Configuration Bits

The configuration bits can be programmed (read as ‘0’)

or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped in

program memory location 2007h.

The user will note that address 2007h is beyond the

user program memory space. In fact, it belongs to the

special configuration memory space (2000h-3FFFh),

which can be accessed only during programming. See

“PIC16F627A/628A/648A EEPROM Memory

Programming Specification” (DS41196) for additional

information.

PIC16F627A/628A/648A

CP ————CPDLVP BOREN MCLRE FOSC2 PWRTE WDTE F0SC1 F0SC0

bit 13 bit 0

bit 13: CP: Flash Program Memory Code Protection bit(2)

(PIC16F648A)

1 = Code protection off

0 = 0000h to 0FFFh code-protected

(PIC16F628A)

1 = Code protection off

0 = 0000h to 07FFh code-protected

(PIC16F627A)

1 = Code protection off

0 = 0000h to 03FFh code-protected

bit 12-9: Unimplemented: Read as ‘0’

bit 8: CPD: Data Code Protection bit(3)

1 = Data memory code protection off

0 = Data memory code-protected

bit 7: LVP: Low-Voltage Programming Enable bit

1 = RB4/PGM pin has PGM function, low-voltage programming enabled

0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming

bit 6: BOREN: Brown-out Reset Enable bit (1)

1 = BOR Reset enabled

0 = BOR Reset disabled

bit 5: MCLRE: RA5/MCLR/VPP Pin Function Select bit

1 = RA5/MCLR/VPP pin function is MCLR

0 = RA5/MCLR/VPP pin function is digital Input, MCLR internally tied to VDD

bit 3: PWRTE: Power-up Timer Enable bit (1)

1 = PWRT disabled

0 = PWRT enabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 4, 1-0: FOSC<2:0>: Oscillator Selection bits(4)

111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN

110 = RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN

101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

100 = INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN

010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT) the way it does on the

PIC16F627/628 devices.

2: The code protection scheme has changed from the code protection scheme used on the PIC16F627/628 devices. The

entire Flash program memory needs to be bulk erased to set the CP bit, turning the code protection off. See

“PIC16F627A/628A/6 48A EEPROM Memory Programming Specification” (DS41196) for details.

3: The entire data EEPROM needs to be bulk erased to set the CPD bit, turning the code protection off. See “PIC16F627A/

628A/648A EEPROM Memory Programming Specification” (DS41196) for details.

4: When MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown

PIC16F627A/628A/648A

14.2 Oscillator Configurations

14.2.1 OSCILLATOR TYPES

The PIC16F627A/628A/648A can be operated in eight

different oscillator options. The user can program three

configuration bits (FOSC2 through FOSC0) to select

one of these eight modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC External Resistor/Capacitor (2 modes)

• INTOSC Internal Precision Oscillator (2 modes)

• EC External Clock In

14.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (Figure 14-1). The PIC16F627A/628A/648A

oscillator design requires the use of a parallel cut

crystal. Use of a series cut crystal may give a frequency

out of the crystal manufacturers specifications. When in

XT, LP or HS modes, the device can have an external

clock source to drive the OSC1 pin (Figure 14-4).

FIGURE 14-1: CRYS TAL OPERATION

(OR CERAMIC RESONATOR)

(HS, XT OR LP OSC

CONFIGURATION)

T ABLE 14-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

T ABLE 14-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Note 1: A series resistor may be required for AT strip cut

crystals.

2: See Table 14-1 and Table 14-2 for recommended

values of C1 and C2.

C1(2)

C2(2)

XTAL

OSC2

RS(1)

OSC1

RF Sleep

PIC16F627A/628A/648A

FOSC

Mode Freq OSC1(C1) OSC2(C2)

XT 455 kHz

2.0 MHz

4.0 MHz

22-100 pF

15-68 pF

22-100 pF

15-68 pF

HS 8.0 MHz

16.0 MHz

10-68 pF

10-22 pF

10-68 pF

10-22 pF

Note: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time. These values are for design

guidance only. Since each resonator has

its own characteristics, the user should

consult the resonator manufacturer for

appropriate values of external compo-

nents.

Mode Freq OSC1(C1) OSC2(C2)

LP 32 kHz

200 kHz

15-30 pF

0-15 pF

15-30 pF

0-15 pF

XT 100 kHz

2 MHz

4 MHz

68-150 pF

15-30 pF

150-200 pF

15-30 pF

HS 8 MHz

10 MHz

20 MHz

15-30 pF

Note: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time. These values are for design

guidance only. A series resistor (RS) may

be required in HS mode, as well as XT

mode, to avoid overdriving crystals with

low drive level specification. Since each

crystal has its own characteristics, the

user should consult the crystal manufac-

turer for appropriate values of external

components.

PIC16F627A/628A/648A

14.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built.

Prepackaged oscillators provide a wide operating

range and better stability. A well-designed crystal

oscillator will provide good performance with TTL

gates. Two types of crystal oscillator circuits can be

used; one with series resonance, or one with parallel

resonance.

Figure 14-2 shows implementation of a parallel

resonant oscillator circuit. The circuit is designed to

use the fundamental frequency of the crystal. The

74AS04 inverter performs the 180° phase shift that a

parallel oscillator requires. The 4.7 kΩ resistor

provides the negative feedback for stability. The

10 kΩ potentiometers bias the 74AS04 in the linear

region. This could be used for external oscillator

designs.

FIGURE 14-2: EX TERN AL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 14-3 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a 180°

phase shift in a series resonant oscillator circuit. The

330 kΩ resistors provide the negative feedback to bias

the inverters in their linear region.

FIGURE 14-3: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

14.2.4 PRECISION INTERNAL 4 MHZ

OSCILLATOR

The internal precision oscillator provides a fixed 4 MHz

(nominal) system clock at VDD = 5V and 25°C. See

Section 17.0 “Electrical S pecifications”, for informa-

tion on variation over voltage and temperature.

14.2.5 EXTERNAL CLOCK IN

For applications where a clock is already available

elsewhere, users may directly drive the PIC16F627A/

628A/648A provided that this external clock source meets

the AC/DC timing requirements listed in Section 17.6

“Timing Diagrams and Specifications”. Figure 14-4

below shows how an external clock circuit should be

configured.

FIGURE 14-4: EXTERNAL CLOCK INPUT

OPERATION (EC, HS, XT

OR LP OSC

CONFIGURATION)

+5V

10K

4.7K

10K

74AS04

XTAL

10K

74AS04 PIC16F627A/628A/648A

CLKIN

To o t he r

Devices

C1 C2

330 KΩ

74AS04 74AS04

PIC16F627A/

CLKIN

To o t he r

Devices

XTAL

330 KΩ

74AS04

0.1 pF

628A/648A

Clock from

ext. system

PIC16F627A/628A/648A

RA6

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

PIC16F627A/628A/648A

14.2.6 RC OSCILLATOR

For applications where precise timing is not a

requirement, the RC oscillator option is available. The

operation and functionality of the RC oscillator is

dependent upon a number of variables. The RC oscillator

frequency is a function of:

• Supply voltage

• Resistor (REXT) and capacitor (CEXT) values

• Operating temperature

The oscillator frequency will vary from unit-to-unit due

to normal process parameter variation. The difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to account for the

tolerance of the external R and C components.

Figure 14-5 shows how the R/C combination is

connected.

FIGURE 14-5: RC OSCILLATOR MODE

The RC Oscillator mode has two options that control

the unused OSC2 pin. The first allows it to be used as

a general purpose I/O port. The other configures the

pin as an output providing the FOSC signal (internal

clock divided by 4) for test or external synchronization

purposes.

14.2.7 CLKOUT

The PIC16F627A/628A/648A can be configured to

provide a clock out signal by programming the

Configuration Word. The oscillator frequency, divided

by 4 can be used for test purposes or to synchronize

other logic.

14.2.8 SPECIAL FEATURE: DUAL-SPEED

OSCILLATOR MODES

A software programmable dual-speed oscillator mode

is provided when the PIC16F627A/628A/648A is

configured in the INTOSC oscillator mode. This feature

allows users to dynamically toggle the oscillator speed

between 4 MHz and 48 kHz nominal in the INTOSC

mode. Applications that require low-current power

savings, but cannot tolerate putting the part into Sleep,

may use this mode.

There is a time delay associated with the transition

between fast and slow oscillator speeds. This oscillator

speed transition delay consists of two existing clock

pulses and eight new speed clock pulses. During this

clock speed transition delay, the System Clock is halted

causing the processor to be frozen in time. During this

delay, the program counter and the CLKOUT stop.

The OSCF bit in the PCON register is used to control

Dual Speed mode. See Section 4.2.2.6 “PCON

14.3 Reset

The PIC16F627A/628A/648A differentiates between

various kinds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

d) WDT Reset (normal operation)

e) WDT wake-up (Sleep)

f) Brown-out Reset (BOR)

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on Power-on Reset, Brown-out Reset, MCLR

Reset, WDT Reset and MCLR Reset during Sleep.

They are not affected by a WDT wake-up, since this is

viewed as the resumption of normal operation. TO and

PD bits are set or cleared differently in different Reset

situations as indicated in Table 14-4. These bits are

used in software to determine the nature of the Reset.

See Table 14-7 for a full description of Reset states of

all registers.

A simplified block diagram of the on-chip Reset circuit

is shown in Figure 14-6.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Table 17-7 for pulse width

specification.

CEXT

VDD

REXT

VSS

PIC16F627A/628A/648A

FOSC/4

Internal

Clock

CLKIN

RA7/OSC1/

RA6/OSC2/CLKOUT

Recommended Values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)

10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3.0V)

CEXT > 20 pF

PIC16F627A/628A/648A

FIGURE 14-6: SI MPLIFI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD Rise

Detect

OST/PWRT

WDT

Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Reset

Enable OST

Enable PWRT

Sleep

See Table 14-3 for time out situations.

Note 1: This is a separate oscillator from the INTOSC/RC oscillator.

Brown-out

Reset

BOREN

CLKIN

VPP Pin

10-bit Ripple-counter

Schmitt Trigger Input

On-chip(1)

OSC

PIC16F627A/628A/648A

14.4 Power-on Reset (POR), Power-up

Timer (PWRT), Oscillator St art-up

Timer (OST) and Brown-out Reset

(BOR)

14.4.1 POWER-ON RESET (POR)

The on-chip POR holds the part in Reset until a VDD

rise is detected (in the range of 1.2-1.7V). A maxi-

mum rise time for VDD is required. See Section 17.0

“Electrical Specifications” for details.

The POR circuit does not produce an internal Reset

when VDD declines.

When the device starts normal operation (exits the

Reset condition), device operating parameters

(voltage, frequency, temperature, etc.) must be met to

ensure proper operation. If these conditions are not

met, the device must be held in Reset via MCLR, BOR

or PWRT until the operating conditions are met.

For additional information, refer to Application Note

AN607 “P ower-up Trouble Shoot ing ” (DS00607).

14.4.2 POWER-UP TIMER (PWRT)

The PWRT provides a fixed 72 ms (nominal) time out

on power-up (POR) or if enabled from a Brown-out

Reset. The PWRT operates on an internal RC oscilla-

tor. The chip is kept in Reset as long as PWRT is active.

The PWRT delay allows the VDD to rise to an accept-

able level. A configuration bit, PWRTE can disable (if

set) or enable (if cleared or programmed) the PWRT. It

is recommended that the PWRT be enabled when

Brown-out Reset is enabled.

The power-up time delay will vary from chip-to-chip and

due to VDD, temperature and process variation. See

DC parameters Table 17-7 for details.

14.4.3 OSCILLATOR START-UP TIMER

(OST)

The OST provides a 1024 oscillator cycle (from OSC1

input) delay after the PWRT delay is over. Program

execution will not start until the OST time out is

complete. This ensures that the crystal oscillator or

resonator has started and stabilized.

The OST time out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

Sleep. See Table 17-7.

14.4.4 BROWN-OUT RESET (BOR)

The PIC16F627A/628A/648A have on-chip BOR

circuitry. A configuration bit, BOREN, can disable (if

clear/programmed) or enable (if set) the BOR circuitry.

If VDD falls below VBOR for longer than TBOR, the

brown-out situation will reset the chip. A Reset is not

assured if VDD falls below VBOR for shorter than TBOR.

VBOR and TBOR are defined in Table 17-2 and

Table 17-7, respectively.

On any Reset (Power-on, Brown-out, Watchdog, etc.),

the chip will remain in Reset until VDD rises above

VBOR (see Figure 14-7). The Power-up Timer will now

be invoked, if enabled, and will keep the chip in Reset

an additional 72 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-Up Timer will execute a

72 ms Reset. Figure 14-7 shows typical brown-out

situations.

FIGURE 14-7: BROW N-OUT SITUATIONS WITH PWRT ENABLED

72 ms

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset 72 ms

<72 ms

72 ms

VBOR

VDD

Internal

Reset

≥ TBOR

Note: 72 ms delay only if PWRTE bit is programmed to ‘0’.

PIC16F627A/628A/648A

14.4.5 TIME OUT SEQUENCE

On power-up, the time out sequence is as follows: First

PWRT time-out is invoked after POR has expired. Then

OST is activated. The total time out will vary based on

oscillator configuration and PWRTE bit Status. For

example, in RC mode with PWRTE bit set (PWRT

disabled), there will be no time out at all. Figure 14-8,

Figure 14-11 and Figure 14-12 depict time out

sequences.

Since the time outs occur from the POR pulse, if MCLR

is kept low long enough, the time outs will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 14-11). This is useful for testing purposes

or to synchronize more than one PIC16F627A/628A/

648A device operating in parallel.

Table 14-6 shows the Reset conditions for some

special registers, while Table 14-7 shows the Reset

conditions for all the registers.

14.4.6 POWER CONTROL (PCON) STATUS

The PCON/Status register, PCON (address 8Eh), has

two bits.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0

indicating that a brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled (by

setting BOREN bit = 0 in the Configuration Word).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset if POR is ‘0’, it will indicate that a

Power-on Reset must have occurred (VDD may have

gone too low).

TABLE 14-3: TIME OUT IN VARIOUS SITUATIONS

TABLE 14-4: ST ATUS/PCON BITS AND THEIR SIGNIFICANCE

Oscillator Configuration Power-up T im er Brown-out Reset W ake-up from

Sleep

PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1

XT, HS, LP 72 ms +

1024•T

OSC

1024•TOSC 72 ms +

1024•T

OSC

1024•TOSC 1024•TOSC

RC, EC 72 ms — 72 ms — —

INTOSC 72 ms — 72 ms — 6 μs

POR BOR TO PD Condition

0X11Power-on Reset

0X0XIllegal, TO is set on POR

0XX0Illegal, PD is set on POR

10XXBrown-out Reset

110uWDT Reset

1100WDT Wake-up

11uuMCLR Reset during normal operation

1110MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

PIC16F627A/628A/648A

TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

TABLE 14-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Reset

V alue on all

other

Resets(1)

03h, 83h,

103h, 183h

STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu

8Eh PCON ——— — OSCF —PORBOR ---- 1-0x ---- u-uq

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by Brown-out Reset.

Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation.

Condition Program

Counter Status

Power-on Reset 000h 0001 1xxx ---- 1-0x

MCLR Reset during normal operation 000h 000u uuuu ---- 1-uu

MCLR Reset during Sleep 000h 0001 0uuu ---- 1-uu

WDT Reset 000h 0000 uuuu ---- 1-uu

WDT Wake-up PC + 1 uuu0 0uuu ---- u-uu

Brown-out Reset 000h 000x xuuu ---- 1-u0

Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- u-uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector

(0004h) after execution of PC + 1.

PIC16F627A/628A/648A

TABLE 14-7: INITIALIZATION CONDITION FOR REGISTERS

•MCLR

Reset during normal

operation

•MCLR

Reset during Sleep

• WDT Reset

• Brown-out Reset (1)

• Wake-up from Sleep(7) through

interrupt

• Wake-up from Sleep(7) through

WDT time out

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h, 80h,

100h, 180h

—— —

TMR0 01h, 101h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h, 82h,

102h, 182h

0000 0000 0000 0000 PC + 1(3)

STATUS 03h, 83h,

103h, 183h

0001 1xxx 000q quuu(4) uuuq 0uuu(4)

FSR 04h, 84h,

104h, 184h

xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h xxxx 0000 xxxx 0000 uuuu uuuu

PORTB 06h, 106h xxxx xxxx uuuu uuuu uuuu uuuu

PCLATH 0Ah, 8Ah,

10Ah, 18Ah

---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh, 8Bh,

10Bh,18Bh

0000 000x 0000 000u uuuu uqqq(2)

PIR1 0Ch 0000 -000 0000 -000 qqqq -qqq(2)

TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 10h --00 0000 --uu uuuu(6) --uu uuuu

TMR2 11h 0000 0000 0000 0000 uuuu uuuu

T2CON 12h -000 0000 -000 0000 -uuu uuuu

CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 17h --00 0000 --00 0000 --uu uuuu

RCSTA 18h 0000 000x 0000 000x uuuu uuuu

TXREG 19h 0000 0000 0000 0000 uuuu uuuu

RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu

CMCON 1Fh 0000 0000 0000 0000 uu-- uuuu

OPTION 81h,181h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h 1111 1111 1111 1111 uuuu uuuu

TRISB 86h, 186h 1111 1111 1111 1111 uuuu uuuu

PIE1 8Ch 0000 -000 0000 -000 uuuu -uuu

PCON 8Eh ---- 1-0x ---- 1-uq(1,5) ---- u-uu

PR2 92h 1111 1111 1111 1111 uuuu uuuu

TXSTA 98h 0000 -010 0000 -010 uuuu -uuu

SPBRG 99h 0000 0000 0000 0000 uuuu uuuu

EEDATA 9Ah xxxx xxxx uuuu uuuu uuuu uuuu

EEADR 9Bh xxxx xxxx uuuu uuuu uuuu uuuu

EECON1 9Ch ---- x000 ---- q000 ---- uuuu

EECON2 9Dh — — —

VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 14-6 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: Reset to ‘--00 0000’ on a Brown-out Reset (BOR).

7: Peripherals generating interrupts for wake-up from Sleep will change the resulting bits in the associated registers.

PIC16F627A/628A/648A

FIGURE 14-8: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE

FIGURE 14-9: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time Out

OST Time Out

Internal Reset

VDD

MCLR

Internal POR

PWRT Time Out

OST Time Out

Internal Reset

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time Out

OST Time Out

Internal Reset

PIC16F627A/628A/648A

FIGURE 14-11: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

FIGURE 14-12: EXT ERN AL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 14-13: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

Note 1: External Power-on Reset circuit is required

only if VDD power-up slope is too slow. The

diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 100Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge (ESD)

or Electrical Overstress (EOS).

VDD

MCLR

PIC16F627A/628A/648A

VDD

Note 1: This circuit will activate Reset when VDD

goes below (Vz + 0.7V) where Vz = Zener

voltage.

2: Internal Brown-out Reset circuitry should

be disabled when using this circuit.

VDD

33k

10k

40k

VDD

MCLR

PIC16F627A/628A/648A

R1 + R2

= 0.7 V

VDD

R2 40k

VDD

MCLR

PIC16F627A/628A/648A

Note 1: This brown-out circuit is less expensive,

albeit less accurate. Transistor Q1 turns off

when VDD is below a certain level such that:

2: Internal Brown-out Reset should be

disabled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

VDD x R1

R1 + R2 = 0.7 V

PIC16F627A/628A/648A

14.5 Interrupts

The PIC16F627A/628A/648A has 10 sources of

interrupt:

• External Interrupt RB0/INT

• TMR0 Overflow Interrupt

• PORTB Change Interrupts (pins RB<7:4>)

• Comparator Interrupt

• USART Interrupt TX

• USART Interrupt RX

• CCP Interrupt

• TMR1 Overflow Interrupt

• TMR2 Match Interrupt

• Data EEPROM Interrupt

The Interrupt Control register (INTCON) records

individual interrupt requests in flag bits. It also has

individual and global interrupt enable bits.

A Global Interrupt Enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on Reset.

The “return-from-interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which re-

enables RB0/INT interrupts.

The INT pin interrupt, the RB port change interrupt and

the TMR0 overflow interrupt flags are contained in the

INTCON register.

The peripheral interrupt flag is contained in the special

contained in special registers PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine, the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in

software before re-enabling interrupts to avoid RB0/

INT recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 14-15).

The latency is the same for one or two-cycle instructions.

Once in the interrupt service routine, the source(s) of the

interrupt can be determined by polling the interrupt flag

bits. The interrupt flag bit(s) must be cleared in software

before re-enabling interrupts to avoid multiple interrupt

requests.

FIGURE 14-14: INTE RRUPT LOGIC

Note 1: Individual interrupt flag bits are set

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The CPU will execute a NOP

in the cycle immediately following the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit

is set again.

TMR2IF

TMR2IE

CCP1IF

CCP1IE

CMIF

CMIE

TXIF

TXIE

RCIF

RCIE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (if in Sleep mode)(1)

Interrupt to CPU

EEIE

EEIF

TMR1IF

TMR1IE

Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is

suspended during Sleep, only those peripherals which do not depend upon the system

clock will wake the part from Sleep. See Secti on 14.8.1 “Wake-up from Sleep”.

PIC16F627A/628A/648A

14.5.1 RB0/INT INTERRUPT

External interrupt on the RB0/INT pin is edge triggered;

either rising if INTEDG bit (OPTION<6>) is set, or

falling, if INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, the INTF bit

(INTCON<1>) is set. This interrupt can be disabled by

clearing the INTE control bit (INTCON<4>). The INTF

bit must be cleared in software in the interrupt service

routine before re-enabling this interrupt. The RB0/INT

interrupt can wake-up the processor from Sleep, if the

INTE bit was set prior to going into Sleep. The status of

the GIE bit decides whether or not the processor

branches to the interrupt vector following wake-up. See

Section 14.8 “Power-Down Mode (Sleep)” for details

on Sleep, and Figure 14-17 for timing of wake-up from

Sleep through RB0/INT interrupt.

14.5.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set the

T0IF (INTCON<2>) bit. The interrupt can be enabled/

disabled by setting/clearing T0IE (INTCON<5>) bit. For

operation of the Timer0 module, see Section 6.0

“Timer0 Module”.

14.5.3 PORTB INTERRUPT

An input change on PORTB <7:4> sets the RBIF

(INTCON<0>) bit. The interrupt can be enabled/disabled

by setting/clearing the RBIE (INTCON<3>) bit. For

operation of PORTB (Section 5.2 “PORTB and TRISB

Registers”).

14.5.4 COMPARATOR INTERRUPT

See Section 10.6 “Comparator Interrupts” for

complete description of comparator interrupts.

FIGURE 14-15: INT PIN INTERRUPT TIMING

Note: If a change on the I/O pin should occur

when the read operation is being executed

(starts during the Q2 cycle and ends before

the start of the Q3 cycle), then the RBIF

interrupt flag may not get set.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instr uction Flow

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC + 1 PC + 1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycle

Inst (PC) Inst (PC + 1)

Inst (PC - 1) Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.

3: CLKOUT is available in RC and INTOSC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

(1)

(4)

(5) (2)

(3)

PIC16F627A/628A/648A

TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS

14.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W register and

Status register). This must be implemented in software.

Example 14-1 stores and restores the Status and W

registers. The user register, W_TEMP, must be defined

in a common memory location (i.e., W_TEMP is

defined at 0x70 in Bank 0 and is therefore, accessible

at 0xF0, 0x170 and 0x1F0). The Example 14-1:

• Stores the W register

• Stores the Status register

• Executes the ISR code

• Restores the Status (and bank select bit register)

• Restores the W register

EXAMPLE 14-1: SAVING THE STATUS

AND W REGISTERS IN

RAM

14.7 W atchdog Timer (WDT)

The Watchdog Timer is a free running on-chip RC

oscillator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the CLKIN pin. That means that the

WDT will run, even if the clock on the OSC1 and OSC2

pins of the device has been stopped, for example, by

execution of a SLEEP instruction. During normal

operation, a WDT time out generates a device Reset. If

the device is in Sleep mode, a WDT time out causes

the device to wake-up and continue with normal

operation. The WDT can be permanently disabled by

programming the configuration bit WDTE as clear

(Section 14.1 “Configuration Bits”).

14.7.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms (with

no prescaler). The time-out periods vary with

temperature, VDD and process variations from part to

part (see DC Specifications, Table 17-7). If longer time-

out periods are desired, a postscaler with a division ratio

of up to 1:128 can be assigned to the WDT under

software control by writing to the OPTION register. Thus,

time-out periods up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the postscaler, if assigned to the WDT, and prevent

it from timing out and generating a device Reset.

The TO bit in the Status register will be cleared upon a

Watchdog Timer time out.

14.7.2 WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst case

conditions (VDD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT time out occurs.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Reset

Value on all

other

Resets(1)

0Bh, 8Bh,

10Bh, 18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal

operation.

MOVWF W_TEMP ;copy W to temp register,

;could be in any bank

SWAPF STATUS,W ;swap status to be saved

;into W

BCF STATUS,RP0 ;change to bank 0

;regardless of current

;bank

MOVWF STATUS_TEMP ;save status to bank 0

;register

:(ISR)

SWAPF STATUS_TEMP,W;swap STATUS_TEMP

;into W, sets bank to

original

;state

MOVWF STATUS ;move W into STATUS

;register

SWAPF W_TEMP,F ;swap W_TEMP

SWAPF W_TEMP,W ;swap W_TEMP into W

PIC16F627A/628A/648A

FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS

14.8 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the Status register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before SLEEP was executed (driving high, low or high-

impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD or VSS with no external

circuitry drawing current from the I/O pin and the

comparators, and VREF should be disabled. I/O pins

that are high-impedance inputs should be pulled high

or low externally to avoid switching currents caused by

floating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The

contribution from on chip pull-ups on PORTB should be

considered.

The MCLR pin must be at a logic high level (VIHMC).

Add r e s s Name Bit 7 Bit 6 B it 5 B i t 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Reset

Value on

all other

Resets

2007h CONFIG LVP BOREN MCLRE FOSC2 PWRTE WDTE FOSC1 FOSC0 uuuu uuuu uuuu uuuu

81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.

Note: Shaded cells are not used by the Watchdog Timer.

(Figure 6-1)

Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

From TMR0 Clock Source

Watchdog

Timer

WDT

Enable Bit

8 to 1 MUX PS<2:0>

To TMR0

(Figure 6-1)

01 PSA

WDT

Time-out

PSA

MUX

WDT Postscaler/

TMR0 Prescaler

Note: It should be noted that a Reset generated

by a WDT time-out does not drive MCLR

pin low.

PIC16F627A/628A/648A

14.8.1 WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin

2. Watchdog Timer wake-up (if WDT was enabled)

3. Interrupt from RB0/INT pin, RB port change, or

any peripheral interrupt, which is active in Sleep.

The first event will cause a device Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the Status register

can be used to determine the cause of device Reset.

PD bit, which is set on power-up, is cleared when Sleep

is invoked. TO bit is cleared if WDT wake-up occurred.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the

interrupt address (0004h). In cases where the

execution of the instruction following SLEEP is not

desirable, the user should have an NOP after the SLEEP

instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

FIGURE 14-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT

14.9 Code Protection

With the Code-Protect bit is cleared (Code-Protect

enabled), the contents of the program memory

locations are read out as ‘0’. See “PIC16F627A/628A/

648A EEPROM Memory Programming Specification”

(DS41196) for details.

14.10 User ID Locations

Four memory locations (2000h-2003h) are designated

as user ID locations where the user can store

checksum or other code-identification numbers. These

locations are not accessible during normal execution

but are readable and writable during Program/Verify.

Only the Least Significant 4 bits of the user ID locations

are used for checksum calculations although each

location has 14 bits.

Note: If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the corresponding

interrupt flag bits set, the device will not enter

Sleep. The SLEEP instruction is executed as

a NOP instruction.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h(3) 0005h

Dummy cycle

TOST(1,2)

PC + 2

Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024 TOSC (drawing not to scale). Approximately 1 μs delay will be there for RC Oscillator mode.

3: GIE = 1 assumed. In this case, after wake-up the processor jumps to the interrupt routine. If GIE = 0, execution will continue

in-line.

4: CLKOUT is not available in these Oscillator modes, but shown here for timing reference.

Note: Only a Bulk Erase function can set the CP

and CPD bits by turning off the code

protection. The entire data EEPROM and

Flash program memory will be erased to

turn the code protection off.

PIC16F627A/628A/648A

14.11 In-Circuit Serial Programming™

(ICSP™)

The PIC16F627A/628A/648A microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock and data,

and three other lines for power, ground and the

programming voltage. This allows customers to

manufacture boards with unprogrammed devices and

then program the microcontroller just before shipping

the product. This also allows the most recent firmware

or custom firmware to be programmed.

The device is placed into a Program/Verify mode by

holding the RB6 and RB7 pins low while raising the

MCLR (VPP) pin from VIL to VIHH. See “PIC16F627A/

628A/648A EEPROM Memory Programming

Specification” (DS41196) for details. RB6 becomes the

programming clock and RB7 becomes the programming

data. Both RB6 and RB7 are Schmitt Trigger inputs in

this mode.

After Reset, to place the device into Programming/Verify

mode, the Program Counter (PC) is at location 00h. A

6-bit command is then supplied to the device. Depending

on the command, 14 bits of program data are then

supplied to or from the device, depending if the command

was a load or a read. For complete details of serial

programming, please refer to “PIC16F627A/628A/648A

EEPROM Memory Programming Specification”

(DS41196).

A typical In-Circuit Serial Programming connection is

shown in Figure 14-18.

FIGURE 14-18: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

14.12 Low-Voltage Programming

The LVP bit of the Configuration Word, enables the low-

voltage programming. This mode allows the

microcontroller to be programmed via ICSP using only

a 5V source. This mode removes the requirement of

VIHH to be placed on the MCLR pin. The LVP bit is

normally erased to ‘1’ which enables the low-voltage

programming. In this mode, the RB4/PGM pin is

dedicated to the programming function and ceases to

be a general purpose I/O pin. The device will enter

Programming mode when a ‘1’ is placed on the RB4/

PGM pin. The High-Voltage Programming mode is still

available by placing VIHH on the MCLR pin.

If Low-Voltage Programming mode is not used, the

LVP bit should be programmed to a ‘0’ so that RB4/

PGM becomes a digital I/O pin. To program the device,

VIHH must be placed onto MCLR during programming.

The LVP bit may only be programmed when program-

ming is entered with VIHH on MCLR. The LVP bit

cannot be programmed when programming is entered

with RB4/PGM.

It should be noted, that once the LVP bit is programmed

to ‘0’, only High-Voltage Programming mode can be

used to program the device.

External

Connector

Signals

To N o rm a l

Connections

To N o rm a l

Connections

PIC16F627A/628A/648A

VDD

VSS

RA5/MCLR/VPP

RB6/PGC

RB7/PGD

+5V

VPP

CLK

Data I/O

VDD

Note 1: While in this mode, the RB4 pin can no

longer be used as a general purpose I/O

pin.

2: VDD must be 5.0V +10% during erase

operations.

PIC16F627A/628A/648A

14.13 In-Circuit Debugger

Since in-circuit debugging requires the loss of clock,

data and MCLR pins, MPLAB® ICD 2 development with

an 18-pin device is not practical. A special 28-pin

PIC16F648A-ICD device is used with MPLAB ICD 2 to

provide separate clock, data and MCLR pins and frees

all normally available pins to the user. Debugging of all

three versions of the PIC16F627A/628A/648A is

supported by the PIC16F648A-ICD.

This special ICD device is mounted on the top of a

header and its signals are routed to the MPLAB ICD 2

connector. On the bottom of the header is an 18-pin

socket that plugs into the user’s target via an 18-pin

stand-off connector.

When the ICD pin on the PIC16F648A-ICD device is

held low, the In-Circuit Debugger functionality is

enabled. This function allows simple debugging

functions when used with MPLAB ICD 2. When the

microcontroller has this feature enabled, some of the

resources are not available for general use. Table 14-19

shows which features are consumed by the background

debugger.

TABLE 14-19: DEBUGGER RESOURCES

The PIC16F648A-ICD device with header is supplied

as an assembly. See Microchip Part Number

AC162053.

I/O pins ICDCLK, ICDDATA

Stack 1 level

Program Memory Address 0h must be NOP

300h-3FEh

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

15.0 INSTRUCTION SET SUMMARY

Each PIC16F627A/628A/648A instruction is a 14-bit

word divided into an OPCODE which specifies the

instruction type and one or more operands which

further specify the operation of the instruction. The

PIC16F627A/628A/648A instruction set summary in

Table 15-2 lists byte-oriented, bit-oriented, and

literal and control operations. Table 15-1 shows the

opcode field descriptions.

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

designator which selects the number of the bit affected

by the operation, while ‘f’ represents the number of the

file in which the bit is located.

For literal and control operations, ‘k’ represents an

eight or eleven bit constant or literal value.

15.1 Read-Modify-Write Operat ions

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

For example, a “clrf PORTB” instruction will read

PORTB, clear all the data bits, then write the result

back to PORTB. This example would have the unin-

tended result that the condition that sets the RBIF flag

would be cleared for pins configured as inputs and

using the PORTB interrupt-on-change feature.

TABLE 15-1: OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped

into three basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal and control operations

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles with the second cycle executed as a

NOP. One instruction cycle consists of four oscillator

periods. Thus, for an oscillator frequency of 4 MHz, the

normal instruction execution time is 1 μs. If a

conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2 μs.

Table 15-2 lists the instructions recognized by the

MPASM™ assembler.

Figure 15-1 shows the three general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where ‘h’ signifies a hexadecimal digit.

FIGURE 15-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

f Register file address (0x00 to 0x7F)

W Working register (accumulator)

b Bit address within an 8-bit file register

k Literal field, constant data or label

x Don’t care location (= 0 or 1)

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

d Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1

TO Time-out bit

PD Power-down bit

Note 1: Any unused opcode is reserved. Use of

any reserved opcode may cause unex-

pected operation.

2: To maintain upward compatibility with

future PIC MCU products, do not use the

OPTION and TRIS instructions.

Byte-oriented file register operations

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

OPCODE k (literal)

k = 8-bit immediate value

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

13 8 7 6 0

13 10 9 7 06

13 8 7 0

13 11 10 0

PIC16F627A/628A/648A

TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

—

f, d

—

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C,DC,Z

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1(2)

00bb

01bb

10bb

11bb

bfff

ffff

1, 2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

—

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the

pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data

will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the

Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed

as a NOP.

PIC16F627A/628A/648A

15.2 Instruction Descri ptions

ADDLW Add Literal and W

Syntax: [ label ] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Encoding: 11 111x kkkk kkkk

Description: The contents of the W register

are added to the eight bit literal

‘k’ and the result is placed in the

W register.

Words: 1

Cycles: 1

Example ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Encoding: 00 0111 dfff ffff

Description: Add the contents of the W

‘0’, the result is stored in the W

stored back in register ‘f’.

Words: 1

Cycles: 1

Example ADDWF REG1, 0

Before Instruction

W=0x17

REG1 = 0xC2

After Instruction

W=0xD9

REG1 = 0xC2

Z=0

C=0

DC = 0

ANDLW AND Literal with W

Syntax: [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Encoding: 11 1001 kkkk kkkk

Description: The contents of W register are

AND’ed with the eight bit literal

‘k’. The result is placed in the W

Words: 1

Cycles: 1

Example ANDLW 0x5F

Before Instruction

W=0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Status Affected: Z

Encoding: 00 0101 dfff ffff

Description: AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored

in the W register. If ‘d’ is ‘1’, the

result is stored back in register

‘f’.

Words: 1

Cycles: 1

Example ANDWF REG1, 1

Before Instruction

W=0x17

REG1 = 0xC2

After Instruction

W=0x17

REG1 = 0x02

PIC16F627A/628A/648A

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Encoding: 01 00bb bfff ffff

Description: Bit ‘b’ in register ‘f’ is cleared.

Words: 1

Cycles: 1

Example BCF REG1, 7

Before Instruction

REG1 = 0xC7

After Instruction

REG1 = 0x47

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Encoding: 01 01bb bfff ffff

Description: Bit ‘b’ in register ‘f’ is set.

Words: 1

Cycles: 1

Example BSF REG1, 7

Before Instruction

REG1 = 0x0A

After Instruction

REG1 = 0x8A

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Encoding: 01 10bb bfff ffff

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the

next instruction is skipped.

If bit ‘b’ is ‘0’, then the next

instruction fetched during the

current instruction execution is

discarded, and a NOP is executed

instead, making this a two-cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSC

GOTO

•

REG1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if REG<1> = 0,

PC = address TRUE

if REG<1> =1,

PC = address FALSE

PIC16F627A/628A/648A

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Encoding: 01 11bb bfff ffff

Description: If bit ‘b’ in register ‘f’ is ‘1’, then

the next instruction is skipped.

If bit ‘b’ is ‘1’, then the next

instruction fetched during the

current instruction execution, is

discarded and a NOP is executed

instead, making this a two-cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSS

GOTO

•

REG1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address FALSE

if FLAG<1> = 1,

PC = address TRUE

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Encoding: 10 0kkk kkkk kkkk

Description: Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven bit imme-

diate address is loaded into PC

bits <10:0>. The upper bits of

the PC are loaded from

PCLATH. CALL is a two-cycle

instruction.

Words: 1

Cycles: 2

Example HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE

TOS = Address HERE+1

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Status Affected: Z

Encoding: 00 0001 1fff ffff

Description: The contents of register ‘f’ are

cleared and the Z bit is set.

Words: 1

Cycles: 1

Example CLRF REG1

Before Instruction

REG1 = 0x5A

After Instruction

REG1 = 0x00

Z=1

PIC16F627A/628A/648A

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Encoding: 00 0001 0000 0011

Description: W register is cleared. Zero bit

(Z) is set.

Words: 1

Cycles: 1

Example CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00

Z=1

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0100

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets

the prescaler of the WDT. Status

bits TO and PD are set.

Words: 1

Cycles: 1

Example CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00

WDT prescaler = 0

TO =1

PD =1

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1001 dfff ffff

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

Words: 1

Cycles: 1

Example COMF REG1, 0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W=0xEC

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest)

Status Affected: Z

Encoding: 00 0011 dfff ffff

Description: Decrement register ‘f’. If ‘d’ is

‘0’. the result is stored in the W

stored back in register ‘f’.

Words: 1

Cycles: 1

Example DECF CNT, 1

Before Instruction

CNT = 0x01

Z=0

After Instruction

CNT = 0x00

Z=1

PIC16F627A/628A/648A

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest); skip if result =

Status Affected: None

Encoding: 00 1011 dfff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

If the result is ‘0’, the next

instruction, which is already

fetched, is discarded. A NOP is

executed instead making it a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE DECFSZ REG1, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

REG1 = REG1 - 1

if REG1 = 0,

PC = address CONTINUE

if REG1 ≠0,

PC = address HERE+1

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affected: None

Encoding: 10 1kkk kkkk kkkk

Description: GOTO is an unconditional

branch. The eleven-bit immedi-

ate value is loaded into PC bits

<10:0>. The upper bits of PC

are loaded from PCLATH<4:3>.

GOTO is a two-cycle instruction.

Words: 1

Cycles: 2

Example GOTO THERE

After Instruction

PC = Address THERE

PIC16F627A/628A/648A

INCF Increm ent f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest)

Status Affected: Z

Encoding: 00 1010 dfff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

Words: 1

Cycles: 1

Example INCF REG1, 1

Before Instruction

REG1 = 0xFF

Z=0

After Instruction

REG1 = 0x00

Z=1

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest), skip if result = 0

Status Affected: None

Encoding: 00 1111 dfff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

If the result is ‘0’, the next

instruction, which is already

fetched, is discarded. A NOP is

executed instead making it a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE INCFSZ REG1, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

REG1 = REG1 + 1

if CNT = 0,

PC = address CONTINUE

if REG1≠0,

PC = address HERE +1

PIC16F627A/628A/648A

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

Status Affected: Z

Encoding: 11 1000 kkkk kkkk

Description: The contents of the W register is

OR’ed with the eight-bit literal

‘k’. The result is placed in the W

Words: 1

Cycles: 1

Example IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W=0xBF

Z=0

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (dest)

Status Affected: Z

Encoding: 00 0100 dfff ffff

Description: Inclusive OR the W register with

is placed in the W register. If ‘d’

is ‘1’, the result is placed back in

Words: 1

Cycles: 1

Example IORWF REG1, 0

Before Instruction

REG1 = 0x13

W=0x91

After Instruction

REG1 = 0x13

W=0x93

Z=1

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Encoding: 11 00xx kkkk kkkk

Description: The eight bit literal ‘k’ is loaded

into W register. The “don’t

cares” will assemble as ‘0’s.

Words: 1

Cycles: 1

Example MOVLW 0x5A

After Instruction

W = 0x5A

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1000 dfff ffff

Description: The contents of register ‘f’ is

moved to a destination

dependent upon the status of

‘d’. If d = 0, destination is W

is file register f itself. d = 1 is

useful to test a file register since

status flag Z is affected.

Words: 1

Cycles: 1

Example MOVF REG1, 0

After Instruction

W= value in REG1 register

Z= 1

PIC16F627A/628A/648A

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

Status Affected: None

Encoding: 00 0000 1fff ffff

Description: Move data from W register to

Words: 1

Cycles: 1

Example MOVWF REG1

Before Instruction

REG1 = 0xFF

W = 0x4F

After Instruction

REG1 = 0x4F

W = 0x4F

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 00 0000 0xx0 0000

Description: No operation.

Words: 1

Cycles: 1

Example NOP

OPTION Load Option Register

Syntax: [ label ] OPTION

Operands: None

Operation: (W) → OPTION

Status Affected: None

Encoding: 00 0000 0110 0010

Description: The contents of the W register are

loaded in the OPTION register.

This instruction is supported for

code compatibility with PIC16C5X

products. Since OPTION is a

readable/writable register, the

user can directly address it. Using

only register instruction such as

MOVWF.

Words: 1

Cycles: 1

Example

To maint ain upward compatibil-

ity with future PIC® MCU

products, do not use this

instruction.

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affected: None

Encoding: 00 0000 0000 1001

Description: Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS)

is loaded in the PC. Interrupts

are enabled by setting Global

Interrupt Enable bit, GIE

(INTCON<7>). This is a two-

cycle instruction.

Words: 1

Cycles: 2

Example RETFIE

After Interrupt

PC = TOS

GIE = 1

PIC16F627A/628A/648A

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 11 01xx kkkk kkkk

Description: The W register is loaded with

the eight-bit literal ‘k’. The

program counter is loaded from

the top of the stack (the return

address). This is a two-cycle

instruction.

Words: 1

Cycles: 2

Example

TABLE

CALL TABLE;W contains table

;offset value

• ;W now has table value

•

ADDWF PC;W = offset

RETLW k1;Begin table

RETLW k2;

•

RETLW kn; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Encoding: 00 0000 0000 1000

Description: Return from subroutine. The

stack is POPed and the top of

the stack (TOS) is loaded into

the program counter. This is a

two-cycle instruction.

Words: 1

Cycles: 2

Example RETURN

After Interrupt

PC = TOS

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1101 dfff ffff

Description: The contents of register ‘f’ are

rotated one bit to the left through

the Carry Flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Words: 1

Cycles: 1

Example RLF REG1, 0

Before Instruction

REG1=1110 0110

C=0

After Instruction

REG1=1110 0110

W= 1100 1100

C=1

PIC16F627A/628A/648A

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1100 dfff ffff

Description: The contents of register ‘f’ are

rotated one bit to the right

through the Carry Flag. If ‘d’ is

‘0’, the result is placed in the W

placed back in register ‘f’.

Words: 1

Cycles: 1

Example RRF REG1, 0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W= 0111 0011

C=0

SLEEP

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0011

Description: The power-down Status bit, PD

is cleared. Time out Status bit,

TO is set. Watchdog Timer and

its prescaler are cleared.

The processor is put into Sleep

mode with the oscillator

stopped. See Section 14.8

“Power-Down M ode (Sleep)”

for more details.

Words: 1

Cycles: 1

Example:SLEEP

SUBLW Subtract W from Literal

Syntax: [ label ]SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status

Affected:

C, DC, Z

Encoding: 11 110x kkkk kkkk

Description: The W register is subtracted (2’s

complement method) from the eight-

bit literal ‘k’. The result is placed in

the W register.

Words: 1

Cycles: 1

Example 1:SUBLW 0x02

Before Instruction

W=1

C=?

After Instruction

W= 1

C=1; result is positive

Example 2: Before Instruction

W= 2

C=?

After Instruction

W= 0

C=1; result is zero

Example 3: Before Instruction

W= 3

C= ?

After Instruction

W= 0xFF

C = 0; result is negative

PIC16F627A/628A/648A

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (dest)

Status

Affected:

C, DC, Z

Encoding: 00 0010 dfff ffff

Description: Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stored back in register ‘f’.

Words: 1

Cycles: 1

Example 1:SUBWF REG1, 1

Before Instruction

REG1 = 3

W=2

C=?

After Instruction

REG1 = 1

W=2

C=1; result is positive

DC = 1

Z=0

Example 2: Before Instruction

REG1 = 2

W=2

C=?

After Instruction

REG1 = 0

W=2

C=1; result is zero

Z = DC = 1

Example 3: Before Instruction

REG1 = 1

W=2

C=?

After Instruction

REG1 = 0xFF

W=2

C=0; result is negative

Z = DC = 0

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Status Affected: None

Encoding: 00 1110 dfff ffff

Description: The upper and lower nibbles of

‘0’, the result is placed in W

placed in register ‘f’.

Words: 1

Cycles: 1

Example SWAPF REG1, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W=0x5A

TRIS Load TRIS Register

Syntax: [ label ] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f;

Status Affected: None

Encoding: 00 0000 0110 0fff

Description: The instruction is supported for

code compatibility with the

PIC16C5X products. Since TRIS

registers are readable and

writable, the user can directly

address them.

Words: 1

Cycles: 1

Example

To maint ain upward compatibil-

ity with future PIC® MCU

products, do not use this

instruction.

PIC16F627A/628A/648A

XORLW Exclusive OR Literal with W

Syntax: [ label ]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Encoding: 11 1010 kkkk kkkk

Description: The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

Words: 1

Cycles: 1

Example:XORLW 0xAF

Before Instruction

W=0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status Affected: Z

Encoding: 00 0110 dfff ffff

Description: Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stored back in register ‘f’.

Words: 1

Cycles: 1

Example XORWF REG1, 1

Before Instruction

REG1 = 0xAF

W=0xB5

After Instruction

REG1 = 0x1A

W=0xB5

PIC16F627A/628A/648A

16.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal

controllers are supported with a full range of software

and hardware development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- HI-TECH C for Various Device Families

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

16.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC16F627A/628A/648A

16.2 MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

16.3 HI-TECH C for Various Device

Families

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

16.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel® standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

16.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

16.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

PIC16F627A/628A/648A

16.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

16.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers signifi-

cant advantages over competitive emulators including

low-cost, full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, a rugge-

dized probe interface and long (up to three meters) inter-

connection cables.

16.9 MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC® Flash microcon-

trollers and dsPIC® DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

16.10 PICkit 3 In-Circuit Debugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC® and dsPIC® Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

PIC16F627A/628A/648A

16.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows® programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

Development Environment (IDE) the PICkit™ 2

enables in-circuit debugging on most PIC® microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

16.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

16.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

PIC16F627A/628A/648A

17.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings(†)

Ambient temperature under bias.................................................................................................................-40 to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V

Voltage on MCLR and RA4 with respect to VSS ............................................................................................-0.3 to +14V

Voltage on all other pins with respect to VSS ....................................................................................-0.3V to VDD + 0.3V

Total power dissipation(1) .....................................................................................................................................800 mW

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD)...............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by PORTA and PORTB (Combined)................................................................................200 mA

Maximum current sourced by PORTA and PORTB (Combined)...........................................................................200 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin rather than

pulling this pin directly to VSS.

PIC16F627A/628A/648A

FIGURE 17-1: PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +1 25°C

FIGURE 17-2: PI C16LF 62 7A/6 28A/6 48A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

FREQUENCY (MHz)

VDD

(VOLTS)

Note: The shaded region indicates the permissible combinations of voltage and frequency.

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

FREQUENCY (MHz)

VDD

(VOLTS)

2.0

Note: The shaded region indicates the permissible combinations of voltage and frequency.

PIC16F627A/628A/648A

17.1 DC Characteristics:PI C16F627A/628A/648A (Industrial, Extended)

PIC16LF627A/6 28A/648A (Industrial)

PIC16LF627A/628A/648A

(Industrial)

S tandard Operating Conditi ons (unle ss othe rwis e stated)

Operating temperature -40°C ≤ Ta ≤ +85°C for industrial

PIC16F627A/628A/648A

(Industrial, Extended)

S tandard Operating Conditi ons (unle ss othe rwis e stated)

Operating temperature -40°C ≤ Ta ≤ +85°C for industrial and

-40°C ≤ Ta ≤ +125°C for extended

Param

No. Sym Characteristic/Device Min Typ† Max Units Conditions

VDD Supply Vo ltage

D001 PIC16LF627A/628A/648A 2.0 — 5.5 V

PIC16F627A/628A/648A 3.0 —5.5 V

D002 VDR RAM Data Retention

Voltage(1) — 1.5* — V Device in Sleep mode

D003 VPOR VDD Start Voltage

to ensure Power-on Reset

—VSS — V See Section 14.4 “Power-

on Reset (POR), Power-up

Timer (PWRT), Oscillator

Start-up Timer (OST) and

Brown-out Reset

(BOR)”on Power-on Reset

for details

D004 SVDD VDD Rise Rate

to ensure Power-on Reset

0.05* — — V/ms See Section 14.4 “Power-

on Reset (POR), Power-up

Timer (PWRT), Oscillator

Start-up Timer (OST) and

Brown-out Reset (BOR)”

on Power-on Reset for

details

D005 VBOR Brown-out Reset Voltage 3.65

3.65

4.0

4.35

4.4

BOREN configuration bit is

set

BOREN configuration bit is

set, Extended

Legend: Rows with standard voltage device data only are shaded for improved readability.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

PIC16F627A/628A/648A

17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial)

PIC16LF627A/628A/648A (Industrial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ Ta ≤ +85°C for industrial

Param

No. LF and F Device

Characteristics Min† Typ Max Units Conditions

VDD Note

Supply Voltage (VDD)

D001 LF 2.0 — 5.5 V —

LF/F 3.0 — 5.5 V —

Power-down Base Current (IPD)

D020

LF — 0.01 0.80 μA 2.0 WDT, BOR, Comparators, VREF and

T1OSC: disabled

LF/F — 0.01 0.85 μA3.0

—0.022.7 μA5.0

Peripheral Module Current (ΔIMOD)(1)

D021

LF — 1 2.0 μA 2.0 WDT Current

LF/F — 2 3.4 μA3.0

—917.0μA5.0

D022 LF/F — 29 52 μA 4.5 BOR Current

—3055 μA5.0

D023

LF — 15 22 μA 2.0 Comparator Current

(Both comparators enabled)

LF/F — 22 37 μA3.0

—4468 μA5.0

D024

LF — 34 55 μA2.0V

REF Current

LF/F — 50 75 μA3.0

—80110μA5.0

D025

LF — 1.2 2.0 μA2.0T1O

SC Current

LF/F — 1.3 2.2 μA3.0

—1.82.9 μA5.0

Supply Current (IDD)

D010

LF — 10 15 μA2.0FOSC = 32 kHz

LP Oscillator Mode

LF/F — 15 25 μA3.0

—2848 μA5.0

D011

LF — 125 190 μA2.0F

OSC = 1 MHz

XT Oscillator Mode

LF/F — 175 340 μA3.0

— 320 520 μA5.0

D012

LF — 250 350 μA2.0F

OSC = 4 MHz

XT Oscillator Mode

LF/F — 450 600 μA3.0

— 710 995 μA5.0

D012A

LF — 395 465 μA2.0F

OSC = 4 MHz

INTOSC

LF/F — 565 785 μA3.0

— 0.895 1.3 mA 5.0

D013 LF/F — 2.5 2.9 mA 4.5 FOSC = 20 MHz

HS Oscillator Mode

—2.753.3 mA 5.0

Note 1: The “Δ” current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement. Max values should be used when calculating total current

consumption.

PIC16F627A/628A/648A

17.3 DC Characteristics: PIC16F627A/628A/648A (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ Ta ≤ +125°C for extended

Param

No. Device Characteristics Min† Typ Max Units Conditions

VDD Note

Supply Voltage (VDD)

D001 — 3.0 — 5.5 V —

Power-down Base Current (IPD)

D020E ——0.014μA 3.0 WDT, BOR, Comparators, VREF and

T1OSC: disabled

—0.02 8 μA5.0

Peripheral Module Current (ΔIMOD)(1)

D021E ——29μA3.0WDT Current

—920μA5.0

D022E — — 29 52 μA 4.5 BOR Current

—3055 μA5.0

D023E — — 22 37 μA 3.0 Comparator Current

(Both comparators enabled)

—4468 μA5.0

D024E — — 50 75 μA3.0V

REF Current

—83110μA5.0

D025E ——1.34μA 3.0 T1OSC Current

—1.8 6 μA5.0

Supply Current (IDD)

D010E — — 15 28 μA3.0F

OSC = 32 kHz

LP Oscillator Mode

—2854 μA5.0

D011E ——175340μA3.0FOSC = 1 MHz

XT Oscillator Mode

—320520 μA5.0

D012E ——450650μA3.0F

OSC = 4 MHz

XT Oscillator Mode

— 0.710 1.1 mA 5.0

D012AE ——565785μA3.0F

OSC = 4 MHz

INTOSC

— 0.895 1.3 mA 5.0

D013E — — 2.5 2.9 mA 4.5 FOSC = 20 MHz

HS Oscillator Mode

— 2.75 3.5 mA 5.0

Note 1: The “Δ” current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement. Max values should be used when calculating total current

consumption.

PIC16F627A/628A/648A

17.4 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)

PIC16LF627A/628A/648A (Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

-40°C ≤ TA ≤ +125°C for extended

Operating voltage VDD range as described in DC specification Table 17-2 and

Table 17-3

Param.

No. Sym Characteristic/Device Min Typ† Max Unit Conditions

VIL Input Low Voltage

D030

D031

D032

D033

I/O ports

with TTL buffer

with Schmitt Trigger input(4)

MCLR, RA4/T0CKI,OSC1

(in RC mode)

OSC1 (in HS)

OSC1 (in LP and XT)

VSS

—

0.8

0.15 VDD

0.2 VDD

0.3 VDD

0.6

VDD = 4.5V to 5.5V

otherwise

(Note1)

VIH Input High Voltage

D040

D041

D042

D043

D043A

D043B

I/O ports

with TTL buffer

with Schmitt Trigger input(4)

MCLR RA4/T0CKI

OSC1 (XT and LP)

OSC1 (in RC mode)

OSC1 (in HS mode)

2.0V

.25 VDD + 0.8V

0.8 VDD

1.3

0.9 VDD

0.7 VDD

—

VDD

VDD = 4.5V to 5.5V

otherwise

(Note1)

D070 IPURB PORTB weak pu ll-up

current 50 200 400 μAVDD = 5.0V, VPIN = VSS

IIL Input Leakage Current(2), (3)

D060

D061

D063

I/O ports (Except PORTA)

PORTA(4)

RA4/T0CKI

OSC1, MCLR

—

±1.0

±0.5

±1.0

±5.0

μA

VSS ≤ VPIN ≤ VDD, pin at high-impedance

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD, XT, HS and LP

oscillator configuration

VOL Output Low Voltage

D080

I/O ports(4) —

—

0.6

IOL = 8.5 mA, VDD = 4.5 V, -40° to +85°C

IOL = 7.0 mA, VDD = 4.5 V, +85° to

+125°C

VOH Output High Voltage(3)

D090 I/O ports (Except RA4(4) )VDD – 0.7

VDD – 0.7

—

IOH = -3.0 mA, VDD = 4.5 V, -40° to +85°C

IOH = -2.5 mA, VDD = 4.5 V, +85° to

+125°C

D150 VOD Open-Drain High Voltage — — 8.5* V RA4 pin PIC16F627A/628A/648A,

PIC16LF627A/628A/648A

Capacitive Loading Specs on Ou tp ut Pins

D100*

D101*

COSC2

CIO

OSC2 pin

All I/O pins/OSC2 (in RC mode)

—

In XT, HS and LP modes when external

clock used to drive OSC1.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16F627A/628A/648A

be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal

operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

4: Includes OSC1 and OSC2 when configured as I/O pins, CLKIN or CLKOUT.

PIC16F627A/628A/648A

TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)

PIC16LF627A/628A/648A (Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

-40°C ≤ TA ≤ +125°C for extended

Operating voltage VDD range as described in DC specification

Table 17-2 and Table 17-3

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

Data EEPROM Memory

D120

D120A

D121

D122

D123

D124

VDRW

TDEW

TRETD

TREF

Endurance

VDD for read/write

Erase/Write cycle time

Characteristic Retention

Number of Total Erase/Write

Cycles before Refresh(1)

100K

10K

VMIN

—

100K

—

10M

—

5.5

—

E/W

Year

E/W

-40°C ≤ TA ≤ 85°C

85°C ≤ TA ≤ 125°C

VMIN = Minimum operating

voltage

Provided no other

specifications are violated

-40°C to +85°C

Program Flash Memory

D130

D130A

D131

D132

D132A

D133

D133A

D134

VPR

VIE

VPEW

TIE

TPEW

TRETP

Endurance

VDD for read

VDD for Block erase

VDD for write

Block Erase cycle time

Write cycle time

Characteristic Retention

10K

1000

VMIN

4.5

VMIN

—

100K

10K

—

5.5

—

E/W

year

-40°C ≤ TA ≤ 85°C

85°C ≤ TA ≤ 125°C

VMIN = Minimum operating

voltage

VMIN = Minimum operating

voltage

VDD > 4.5V

Provided no other

specifications are violated

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Refer to Section 13.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM

endurance.

PIC16F627A/628A/648A

TABLE 17-2: COMPARATOR SPECIFICATIONS

TABLE 17-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditi ons: 2.0 V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated.

Param

No. Characteristics Sym Min Typ Max Units Comments

D300 Input Offset Voltage VIOFF —±5.0 ±10 mV

D301 Input Common Mode Voltage VICM 0—VDD – 1.5* V

D302 Common Mode Rejection Ratio CMRR 55* — — db

D303 Response Time(1) TRESP —

—

300

400

400*

600*

VDD = 3.0V to 5.5V

-40° to +85°C

VDD = 3.0V to 5.5V

-85° to +125°C

VDD = 2.0V to 3.0V

-40° to +85°C

D304 Comparator Mode Change to

Output Valid

TMC2OV —300 10* μs

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from

VSS to VDD.

Operating Conditions: 2.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.

Spec

No. Characteristics Sym Min Typ Max Units Comments

D310 Resolution VRES ——VDD/24

VDD/32

LSb

Low Range (VRR = 1)

High Range (VRR = 0)

D311 Absolute Accuracy VRAA —

—

1/4(2)*

1/2(2)*

LSb

Low Range (VRR = 1)

High Range (VRR = 0)

D312 Unit Resistor Value (R) VRUR —2k*— Ω

D313 Settling Time(1) TSET ——10*μs

* These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.

2: When VDD is between 2.0V and 3.0V, the VREF output voltage levels on RA2 described by the

equation:[VDD/2 ± (3 – VDD)/2] may cause the Absolute Accuracy (VRAA) of the VREF output signal on RA2

to be greater than the stated max.

PIC16F627A/628A/648A

17.5 Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats:

FIGURE 17-3: LOA D CONDITIONS

1. TppS2ppS

2. TppS

F Frequency T Time

Lowercase subscripts (pp) and their meanings:

ck CLKOUT osc OSC1

io I/O port t0 T0CKI

mc MCLR

Uppercase letters and their meanings:

FFall P Period

HHigh R Rise

I Invalid (High-impedance) V Valid

L Low Z High-Impedance

VDD/2

Pin Pin

VSS VSS

RL=464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load Condition 1 Load Condition 2

PIC16F627A/628A/648A

17.6 Timing Diagrams and Specifications

FIGURE 17-4: EX TERN AL CLOCK TIMING

TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENT S

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Frequency(1) DC — 4 MHz XT and RC Osc mode,

VDD = 5.0 V

DC — 20 MHz HS, EC Osc mode

DC — 200 kHz LP Osc mode

Oscillator Frequency(1) — — 4 MHz RC Osc mode, VDD = 5.0V

0.1 — 4 MHz XT Osc mode

—

200

MHz

kHz

HS Osc mode

LP Osc mode

— 4 — MHz INTOSC mode (fast)

— 48 — kHz INTOSC mode (slow)

OSC External CLKIN Period(1) 250 — — ns XT and RC Osc mode

50 — — ns HS, EC Osc mode

5——μsLP Osc mode

Oscillator Period(1) 250 — — ns RC Osc mode

250 — 10,000 ns XT Osc mode

50 — 1,000 ns HS Osc mode

5——μsLP Osc mode

— 250 — ns INTOSC mode (fast)

—21—μs INTOSC mode (slow)

CY Instruction Cycle Time 200 TCY DC ns TCY = 4/FOSC

3TosL,

TosH

External CLKIN (OSC1) High

External CLKIN Low

100* — — ns XT oscillator, T

OSC L/H duty

cycle

4 RC External Biased RC

Frequency

10 kHz* — 4 MHz — VDD = 5.0V

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-based period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-

ation and/or higher than expected current consumption. All devices are tested to operate at “Min” values

with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max” cycle time

limit is “DC” (no clock) for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

PIC16F627A/628A/648A

TABLE 17-5: PRECISION INTERNAL OSCILLATOR PARAMETERS

Legend: TBD = To Be Determined.

* Characterized but not tested.

FIGURE 17-5: CLKO UT AND I/O TIMING

Parameter

No. Sym Characteristic Min Typ Max Units Conditions

F10 FIOSC Oscillator Center frequency —4—MHz

F13 ΔIOSC Oscillator Accuracy 3.9644.04MHzV

DD = 3.5 V, 25°C

3.92 4 4.08 MHz 2.0V ≤ VDD ≤ 5.5V

0°C ≤ T

A ≤ +85°C

3.80 4 4.20 MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ T

A ≤ +85°C (IND)

-40°C ≤ T

A ≤ +125°C (EXT)

F14*TIOSCST Oscillator Wake-up from Sleep

start-up time

—6 8μsV

DD = 2.0V, -40°C to +85°C

—4 6μsVDD = 3.0V, -40°C to +85°C

—3 5μsV

DD = 5.0V, -40°C to +85°C

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

20, 21

19 18

Old Value New Value

PIC16F627A/628A/648A

TABLE 17-6: CLKOUT AND I/O TIMING REQUIREMENTS

FIGURE 17-6: RES E T, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMI NG

Parameter

No. Sym Characteristic Min Typ† Max Units

10 TOSH2CKLOSC1↑ to CLKOUT↓ PIC16F62XA —75200*ns

10A PIC16LF62XA — — 400* ns

11 TOSH2CKHOSC1↑ to CLKOUT↑ PIC16F62XA — 75 200* ns

11A PIC16LF62XA — — 400* ns

12 TCKR CLKOUT rise time PIC16F62XA — 35 100* ns

12A PIC16LF62XA — — 200* ns

13 TCKF CLKOUT fall time PIC16F62XA — 35 100* ns

13A PIC16LF62XA — — 200* ns

14 TCKL2IOVCLKOUT ↓ to Port out valid — — 20* ns

15 TIOV2CKH Port in valid before CLKOUT ↑PIC16F62XA TOSC+200 ns* — — ns

PIC16LF62XA TOSC+400 ns* — — ns

16 TCKH2IOI Port in hold after CLKOUT ↑ 0 — — ns

17 TOSH2IOVOSC1↑ (Q1 cycle) to PIC16F62XA — 50 150* ns

Port out valid PIC16LF62XA — — 300* ns

18 TOSH2IOIOSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time)

100*

200*

——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

VDD

MCLR

Internal

POR

PWRT

Time out

OST

Time out

Internal

Reset

Watchdog

Timer

Reset

I/O Pins

PIC16F627A/628A/648A

FIGURE 17-7: BROW N-OUT RES ET TIMING

TABLE 17-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER REQUIREMENTS

FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

30 TMCLMCLR Pulse Width (low) 2000 — — ns VDD = 5V, -40°C to +85°C

31 TWDT Watchdog Timer Time out Period

(No Prescaler)

7* 18 33* ms VDD = 5V, -40°C to +85°C

32 TOST Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period

33 TPWRT Power-up Timer Period 28* 72 132* ms VDD = 5V, -40°C to +85°C

34 TIOZ I/O High-impedance from MCLR

Low or Watchdog Timer Reset

— — 2.0* μs

35 TBOR Brown-out Reset pulse width 100* — — μsVDD ≤ VBOR (D005)

Legend: TBD = To Be Determined.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

VDD VBOR

RA4/T0CKI/CMP2

RB6/T1OSO/T1CKI/PGC

TMR0 OR

TMR1

PIC16F627A/628A/648A

TABLE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40 TT0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns

With Prescaler 10* — — ns

41 TT0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns

With Prescaler 10* — — ns

42 TT0P T0CKI Period

20 or

Greater of:

CY + 40*

— — ns N = prescale

value (2, 4,

..., 256)

45 TT1H T1CKI High

Time

Synchronous, No Prescaler 0.5TCY + 20* — — ns

Synchronous,

with Prescaler

PIC16F62XA 15* — — ns

PIC16LF62XA 25* — — ns

Asynchronous PIC16F62XA 30* — — ns

PIC16LF62XA 50* — — ns

46 TT1L T1CKI Low

Time

Synchronous, No Prescaler 0.5TCY + 20* — — ns

Synchronous,

with Prescaler

PIC16F62XA 15* — — ns

PIC16LF62XA 25* — — ns

Asynchronous PIC16F62XA 30* — — ns

PIC16LF62XA 50* — — ns

47 TT1P T1CKI input

period

Synchronous PIC16F62XA

20 or

Greater of:

TCY + 40*

— — ns N = prescale

value (1, 2,

4, 8)

PIC16LF62XA

20 or

Greater of:

CY + 40*

———

Asynchronous PIC16F62XA 60* — — ns

PIC16LF62XA 100* — — ns

FT1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit

T1OSCEN)

—32.7

(1) —kHz

48 TCKEZTMR1 Delay from external clock edge to timer

increment

2TOSC —7TOSC —

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This oscillator is intended to work only with 32.768 kHz watch crystals and their manufactured tolerances.

Higher value crystal frequencies may not be compatible with this crystal driver.

PIC16F627A/628A/648A

FIGURE 17-9: CAP TURE/ COMPARE/PWM TIMINGS

TABLE 17-9: CAPTURE/COMPARE/PWM REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

50 T

CCL CCP

input low time

No Prescaler 0.5TCY +

20*

—— ns

With Prescaler

PIC16F62XA 10* — — ns

PIC16LF62XA 20* — — ns

51 TCCH CCP

input high time

No Prescaler 0.5TCY +

20*

—— ns

With Prescaler

PIC16F62XA 10* — — ns

PIC16LF62XA 20* — — ns

52 TCCP CCP input period 3TCY + 40*

— — ns N = prescale

value (1,4 or 16)

53 TCCR CCP output rise time PIC16F62XA 10 25* ns

PIC16LF62XA 25 45* ns

54 T

CCF CCP output fall time PIC16F62XA 10 25* ns

PIC16LF62XA 25 45* ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

(CAPTURE MODE)

50 51

53 54

RB3/CCP1

(COMPARE OR PWM MODE)

RB3/CCP1

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period

of time and matrix samples. ‘Typical’ represents the mean of the distribution at 25°C. ‘Max’ or ‘Min’ represents

(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.

FIGURE 18-1: TYPICAL BASELINE IPD vs. VDD (-40°C TO 25°C)

100

120

140

160

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(Volts)

(nA)

-40°C

0°C

+25°C

PIC16F627A/628A/648A

FIGURE 18-2: TYPICAL BASELINE IPD vs. VDD (85°C)

FIGURE 18-3: TYPICAL BASELINE CURRENT IPD vs. VDD (125°C)

100

120

140

160

180

200

220

240

260

280

300

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(Volts)

IPD (nA)

+85°C

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(Volts)

+125°C

IPD (μA)

PIC16F627A/628A/648A

FIGURE 18-4: TYPICAL BOR IPD vs. VDD

FIGURE 18-5: TYPICAL SINGLE COMPARATOR IPD vs. VDD

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

(Volts)

125°C

85°C

25°C

0°C

-40°C

IPD (μA)

2 2.5 3 3.5 4 4.5 5 5.5

(Volts)

125°C

85°C

25°C

0°C

-40°C

IPD (μA)

PIC16F627A/628A/648A

FIGURE 18-6: TYPICAL VREF IPD vs. VDD

FIGURE 18-7: TYPICAL WDT IPD vs. VDD

100

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(Volts)

125°C

85°C

25°C

0°C

-40°C

IPD (μA)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(Volts)

125°C

85°C

25°C

0°C

-40°C

IPD (μA)

PIC16F627A/628A/648A

FIGURE 18-8: AVERAGE IPD_TIMER1

FIGURE 18-9: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE

VDD = 5 VOLTS

2 2.5 3 3.5 4 4.5 5 5.5

(V)

IPD (uA)

-40C

25C

85C

125

-5.0%

-4.0%

-3.0%

-2.0%

-1.0%

0.0%

1.0%

2.0%

3.0%

4.0%

5.0%

-40 25 85 125

Temperature (ºC)

Change from Calibration Target (%)

PIC16F627A/628A/648A

FIGURE 18-10: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE

VDD = 3 VOLTS

FIGURE 18-11: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE

VDD = 2 VOLTS

-5.0%

-4.0%

-3.0%

-2.0%

-1.0%

0.0%

1.0%

2.0%

3.0%

4.0%

5.0%

-40 25 85 125

Temperature (ºC)

Change from Calibration Target (%)

-5.0%

-4.0%

-3.0%

-2.0%

-1.0%

0.0%

1.0%

2.0%

3.0%

4.0%

5.0%

-40 25 85 125

Temperature (ºC)

Change from Calibration Target (%)

PIC16F627A/628A/648A

FIGURE 18-12: TYPICAL INTERNAL OSCILLATOR DEVIATION vs. VDD AT 25°C – 4 MHz MODE

FIGURE 18-13: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. VDD TEMPERATURE =

-40°C TO 85°C

-5.0%

-4.0%

-3.0%

-2.0%

-1.0%

0.0%

1.0%

2.0%

3.0%

4.0%

5.0%

2 2.5 3 3.5 4 4.5 5 5.5

(V)

Change from Calibration Target (%)

-5.0%

-4.0%

-3.0%

-2.0%

-1.0%

0.0%

1.0%

2.0%

3.0%

4.0%

5.0%

2 2.5 3 3.5 4 4.5 5 5.5

(V)

Change from Calibration Target (%)

PIC16F627A/628A/648A

FIGURE 18-14: INTE RNAL OSCILLATOR IDD vs. VDD – 4 MHz MODE

FIGURE 18-15: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. VDD AT 25°C – SLOW

MODE

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

2 2.5 3 3.5 4 4.5 5 5.5

VDD (V)

IDD (mA)

85 C 25 C Avg -40 C

2 2.5 3 3.5 4 4.5 5 5.5

(V)

Oscillator Frequency (kHz)

PIC16F627A/628A/648A

FIGURE 18-16: INTE RNAL OSCILLATOR IDD vs. VDD – SLOW MODE

FIGURE 18-17: SUPPLY CURRENT (IDD vs. VDD, FOSC = 1 MHz (XT OSCILLATOR MODE)

100

120

140

160

180

2 2.5 3 3.5 4 4.5 5 5.5

(V)

85 C 25 C Avg -40 C

IPD (μA)

100

150

200

250

300

350

400

450

500

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(Volts)

125°C

85°C

25°C

0°C

-40°C

IPD (μA)

PIC16F627A/628A/648A

FIGURE 18-18: SUPPLY CURRENT (IDD vs. VDD, FOSC = 4 MHz (XT OSCILLATOR MODE)

FIGURE 18-19: SUPPLY CURRENT (IDD) v s. VDD, FOSC = 20 MHz (HS OSCILLATOR MODE)

200

300

400

500

600

700

800

900

1000

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(Volts)

125°C

85°C

25°C

0°C

-40°C

IPD (μA)

2.0

2.5

3.0

3.5

4.0

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

(Volts)

(mA)

125°C

85°C

25°C

0°C

-40°C

PIC16F627A/628A/648A

FIGURE 18-20: TYPICAL WDT PERIOD vs. VDD (-40°C TO +125°C)

WDT Time - o u t

2 2.5 3 3.5 4 4.5 5 5.5

(V)

Time (

mS)

-40

125

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

19.0 PACKAGING INFORMATION

19.1 Package Marking Information

18-Lead PDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC16F627A

0410017

18-Lead SOIC (.300”)

XXXXXXXXXXXX

YYWWNNN

Example

PIC16F628A

-E/SO

0410017

20-Lead SSOP

XXXXXXXXXXX

YYWWNNN

Example

PIC16F648A

-I/SS

0410017

28-Lead QFN

XXXXXXXX

YYWWNNN

Example

16F628A

-I/ML

0410017

-I/P

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

PIC16F627A/628A/648A







  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

 3&'!&"&4#*!(!!&4%&&#&

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& . - - -

##4>#& .   <

: 9&  <<  

&& 9  - 

9#4!!  <  

69#>#& )  ? 

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

123

  * ,1

PIC16F627A/628A/648A

!"!"#$%&'!"(



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = ?

##44!!   = =

&#%%+   = -

: >#& . -1,

##4>#& . 1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!   = --

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

123

  * ,1

PIC16F627A/628A/648A

)!*+,!"!!'&!!"



  !"#$%&"' ()"&'"!&)&#*&&&#

 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 

&  ?1,

: 8&  = = 

##44!!  ?  <

&#%%   = =

: >#& .  < <

##4>#& .  - ?

: 9&  ?  

3&9& 9   

3&& 9 .3

9#4!!   = 

3& B B <B

9#>#& )  = -<

A2 c

NOTE 1

  * ,1

PIC16F627A/628A/648A

)-.$,/0121-.

3*&''(/*



  !"#$%&"' ()"&'"!&)&#*&&&#

 4!!*!"&#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  <  

&#%%    

,&&4!! - .3

: >#& . ?1,

.$!##>#& . -? - 

: 9&  ?1,

.$!##9&  -? - 

,&&>#& ) - - -

,&&9& 9   

,&&&.$!## C  = =

DEXPOSED D2

NOTE 1

TOP VIEW BOTTOM VIEW

PAD

  * ,1

PIC16F627A/628A/648A

)-.$,/0121-.

3*&''(/*

&&255***''54

PIC16F627A/628A/648A

NOTES:

PIC16F627A/628A/648A

APPENDIX A: DATA SHE ET

REVISION HISTORY

Revision A

This is a new data sheet.

Revision B

Revised 28-Pin QFN Pin Diagram

Revised Figure 5-4 Block Diagram

Revised Register 7-1 TMR1ON

Revised Example 13-4 Data EEPROM Refresh Routine

Revised Instruction Set SUBWF, Example 1

Revised DC Characteristics 17-2 and 17-3

Revised Tables 17-4 and 17-6

Corrected Table and Figure numbering in Section 17.0

Revision C

General revisions throughout. Revisions to Section

14.0 – Special Features of the CPU. Section 18,

modified graphs.

Revision D

Revise Example 13-2, Data EEPROM Write

Revise Sections 17.2, Param No. D020 and 17.3,

Param No. D020E

Revise Section 18.0 graphs

Revision E

Section 19.0 Packaging Information: Replaced

package drawings and added note.

Revision F (03/2007)

Replaced Package Drawings (Rev. AM); Replaced

Development Support Section; Revised Product ID

System.

Revision G (10/2009)

Corrected 28-lead QFN Package in Section 19.1.

APPENDIX B: DEVICE

DIFFERENCES

The differences between the PIC16F627A/628A/648A

devices listed in this data sheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Device

Memory

Flash

Program RAM

Data EEPROM

Data

PIC16F627A 1024 x 14 224 x 8 128 x 8

PIC16F628A 2048 x 14 224 x 8 128 x 8

PIC16F648A 4096 x 14 256 x 8 256 x 8

PIC16F627A/628A/648A

APPENDIX C: DEVICE MIGRATIONS

This section describes the functional and electrical

specification differences when migrating between

functionally similar devices. (such as from a

PIC16F627 to a PIC16F627A).

C.1 PIC16F627/628 to a PIC16F627A/

628A

1. ER mode is now RC mode.

2. Code protection for the program memory has

changed from code-protect sections of memory

to code-protect of the whole memory. The

configuration bits CP0 and CP1 in the

PIC16F627/628 do not exist in the PIC16F627A/

628A. They have been replaced with one

configuration bit<13> CP

3. “Brown-out Detect (BOD)” terminology has

changed to “Brown-out Reset (BOR)” to better

represent the function of the Brown-out circuitry.

4. Enabling Brown-out Reset (BOR) does not

automatically enable the Power-up Timer

(PWRT) the way it did in the PIC16F627/628.

5. INTRC is now called INTOSC.

6. Timer1 Oscillator is now designed for

32.768 kHz operation. In the PIC16F627/628,

the Timer1 oscillator was designed to run up to

200 kHz.

7. The Dual-Speed Oscillator mode only works in

the INTOSC oscillator mode. In the PIC16F627/

628, the Dual-Speed Oscillator mode worked in

both the INTRC and ER oscillator modes.

APPENDIX D: MIGRATING FROM

OTHER PIC®

DEVICES

This discusses some of the issues in migrating from

other PIC MCU devices to the PIC16F627A/628A/

648A family of devices.

D.1 PIC16C62X/CE62X to PIC16F627A/

628A/648A Migration

See Microchip web site for availability

(www.microchip.com).

D.2 PIC16C622A to PIC16F627A/628A/

648A Migration

See Microchip web site for availability

(www.microchip.com).

Note: This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process

differences in the manufacture of this

device, this device may have different

performance characteristics than its earlier

version. These differences may cause this

device to perform differently in your

application than the earlier version of this

device.

PIC16F627A/628A/648A

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

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listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical suppo rt is avail able throug h the we b site

at: http://support.microchip.com

PIC16F627A/628A/648A

READER RESP ONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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DS40044GPIC16F627A/628A/648A

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

PIC16F627A/628A/648A

INDEX

A/D

Special Event Trigger (CCP)....................................... 59

Absolute Maximum Ratings .............................................. 135

ADDLW Instruction ........................................................... 119

ADDWF Instruction ........................................................... 119

ANDLW Instruction ........................................................... 119

ANDWF Instruction ........................................................... 119

Architectural Overview ........................................................ 11

Assembler

MPASM Assembler................................................... 132

Baud Rate Error .................................................................. 75

Baud Rate Formula ............................................................. 75

BCF Instruction ................................................................. 120

Block Diagrams

Comparator

I/O Operating Modes .......................................... 64

Modified Comparator Output .............................. 66

I/O Ports

RB0/INT Pin........................................................ 38

RB1/RX/DT Pin................................................... 39

RB2/TX/CK Pin ................................................... 39

RB3/CCP1 Pin .................................................... 40

RB4/PGM Pin ..................................................... 41

RB5 Pin............................................................... 42

RB6/T1OSO/T1CKI Pin ...................................... 43

RB7/T1OSI Pin ................................................... 44

RC Oscillator Mode................................................... 101

USART Receive.......................................................... 82

USART Transmit......................................................... 80

BRGH bit............................................................................. 75

Brown-Out Reset (BOR) ................................................... 103

BSF Instruction ................................................................. 120

BTFSC Instruction............................................................. 120

BTFSS Instruction............................................................. 121

C Compilers

MPLAB C18 .............................................................. 132

CALL Instruction ............................................................... 121

Capture (CCP Module) ....................................................... 58

Block Diagram............................................................. 58

CCP Pin Configuration................................................ 58

CCPR1H:CCPR1L Registers...................................... 58

Changing Between Capture Prescalers...................... 58

Prescaler..................................................................... 58

Software Interrupt ....................................................... 58

Timer1 Mode Selection ............................................... 58

Capture/Compare/PWM (CCP)........................................... 57

Capture Mode. See Capture

CCP1 .......................................................................... 57

CCPR1H Register............................................... 57

CCPR1L Register ............................................... 57

CCP2 .......................................................................... 57

Compare Mode. See Compare

PWM Mode. See PWM

Timer Resources......................................................... 57

CCP1CON Register ............................................................ 57

CCP1M Bits ................................................................ 57

CCP1X:CCP1Y Bits .................................................... 57

CCP2CON Register

CCP2M<3:2> Bits ....................................................... 57

CCP2X:CCP2Y Bits.................................................... 57

Clocking Scheme/Instruction Cycle .................................... 15

CLRF Instruction............................................................... 121

CLRW Instruction.............................................................. 122

CLRWDT Instruction......................................................... 122

CMCON Register................................................................ 63

Code Examples

Data EEPROM Refresh Routine ................................ 94

Code Protection ................................................................ 113

COMF Instruction.............................................................. 122

Comparator

Block Diagrams

I/O Operating Modes .......................................... 64

Modified Comparator Output .............................. 66

Comparator Module.................................................... 63

Configuration .............................................................. 64

Interrupts .................................................................... 67

Operation.................................................................... 65

Reference ................................................................... 65

Compare (CCP Module) ..................................................... 58

Block Diagram ............................................................ 58

CCP Pin Configuration ............................................... 59

CCPR1H:CCPR1L Registers ..................................... 58

Software Interrupt ....................................................... 59

Special Event Trigger ................................................. 59

Timer1 Mode Selection............................................... 59

CONFIG Register ............................................................... 98

Configuration Bits ............................................................... 97

Crystal Operation................................................................ 99

Customer Change Notification Service............................. 173

Customer Notification Service .......................................... 173

Customer Support............................................................. 173

Data EEPROM Memory...................................................... 91

EECON1 Register ...................................................... 91

EECON2 Register ...................................................... 91

Operation During Code Protection ............................. 95

Reading ...................................................................... 93

Spurious Write Protection........................................... 93

Using .......................................................................... 94

Write Verify ................................................................. 93

Writing to .................................................................... 93

Data Memory Organization................................................. 17

DECF Instruction .............................................................. 122

DECFSZ Instruction.......................................................... 123

Development Support....................................................... 131

Device Differences............................................................ 171

Device Migrations ............................................................. 172

Dual-speed Oscillator Modes............................................ 101

EECON1 Register............................................................... 92

EECON1 register................................................................ 92

EECON2 register................................................................ 92

Errata .................................................................................... 5

External Crystal Oscillator Circuit ..................................... 100

Fuses. See Configuration Bits

General-Purpose Register File ........................................... 17

GOTO Instruction.............................................................. 123

PIC16F627A/628A/648A

I/O Ports .............................................................................. 33

Bidirectional ................................................................ 46

Block Diagrams

RB0/INT Pin ........................................................ 38

RB1/RX/DT Pin...................................................39

RB2/TX/CK Pin ...................................................39

RB3/CCP1 Pin .................................................... 40

RB4/PGM Pin...................................................... 41

RB5 Pin............................................................... 42

RB6/T1OSO/T1CKI Pin ......................................43

RB7/T1OSI Pin ................................................... 44

PORTA........................................................................ 33

PORTB........................................................................ 38

Programming Considerations ..................................... 46

Successive Operations ...............................................46

TRISA ......................................................................... 33

TRISB ......................................................................... 38

ID Locations ...................................................................... 113

INCF Instruction ................................................................ 124

INCFSZ Instruction............................................................ 124

In-Circuit Serial Programming™ ....................................... 114

Indirect Addressing, INDF and FSR Registers.................... 30

Instruction Flow/Pipelining .................................................. 15

Instruction Set

ADDLW ..................................................................... 119

ADDWF..................................................................... 119

ANDLW ..................................................................... 119

ANDWF..................................................................... 119

BCF........................................................................... 120

BSF ........................................................................... 120

BTFSC ...................................................................... 120

BTFSS ...................................................................... 121

CALL ......................................................................... 121

CLRF......................................................................... 121

CLRW ....................................................................... 122

CLRWDT................................................................... 122

COMF ....................................................................... 122

DECF ........................................................................ 122

DECFSZ.................................................................... 123

GOTO ....................................................................... 123

INCF.......................................................................... 124

INCFSZ ..................................................................... 124

IORLW ...................................................................... 125

IORWF ...................................................................... 125

MOVF........................................................................ 125

MOVLW .................................................................... 125

MOVWF .................................................................... 126

NOP .......................................................................... 126

OPTION .................................................................... 126

RETFIE ..................................................................... 126

RETLW ..................................................................... 127

RETURN ................................................................... 127

RLF ........................................................................... 127

RRF........................................................................... 128

SLEEP ...................................................................... 128

SUBLW ..................................................................... 128

SUBWF ..................................................................... 129

SWAPF ..................................................................... 129

TRIS.......................................................................... 129

XORLW..................................................................... 130

XORWF..................................................................... 130

Instruction Set Summary................................................... 117

INT Interrupt......................................................................110

INTCON Register ................................................................ 26

Internet Address ............................................................... 173

Interrupt Sources

Capture Complete (CCP)............................................ 58

Compare Complete (CCP).......................................... 59

TMR2 to PR2 Match (PWM) ....................................... 60

Interrupts........................................................................... 109

Interrupts, Enable Bits

CCP1 Enable (CCP1IE Bit) ........................................ 58

Interrupts, Flag Bits

CCP1 Flag (CCP1IF Bit)............................................. 58

IORLW Instruction ............................................................ 125

IORWF Instruction ............................................................ 125

Memory Organization

Data EEPROM Memory.................................. 91, 93, 95

Microchip Internet Web Site.............................................. 173

Migrating from other PICmicro Devices ............................ 172

MOVF Instruction.............................................................. 125

MOVLW Instruction........................................................... 125

MOVWF Instruction .......................................................... 126

MPLAB ASM30 Assembler, Linker, Librarian ................... 132

MPLAB Integrated Development Environment Software.. 131

MPLAB PM3 Device Programmer .................................... 134

MPLAB REAL ICE In-Circuit Emulator System ................ 133

MPLINK Object Linker/MPLIB Object Librarian ................ 132

NOP Instruction ................................................................ 126

OPTION Instruction .......................................................... 126

OPTION Register................................................................ 25

OPTION_REG Register...................................................... 25

Oscillator Configurations..................................................... 99

Oscillator Start-up Timer (OST)........................................ 103

Package Marking Information ........................................... 163

Packaging Information ...................................................... 163

PCL and PCLATH............................................................... 30

Stack........................................................................... 30

PCON Register ................................................................... 29

PIE1 Register...................................................................... 27

Pin Functions

RC6/TX/CK........................................................... 73–89

RC7/RX/DT........................................................... 73–89

PIR1 Register ..................................................................... 28

PORTA ............................................................................... 33

PORTB ............................................................................... 38

PORTB Interrupt............................................................... 110

Power Control/Status Register (PCON)............................ 104

Power-Down Mode (Sleep)............................................... 112

Power-On Reset (POR) .................................................... 103

Power-up Timer (PWRT) .................................................. 103

PR2 Register ................................................................ 54, 60

Program Memory Organization........................................... 17

PWM (CCP Module) ........................................................... 60

Block Diagram ............................................................ 60

Simplified PWM .................................................. 60

CCPR1H:CCPR1L Registers...................................... 60

Duty Cycle .................................................................. 61

Example Frequencies/Resolutions ............................. 61

Period ......................................................................... 60

Set-Up for PWM Operation......................................... 61

TMR2 to PR2 Match ................................................... 60

PIC16F627A/628A/648A

Q-Clock ............................................................................... 61

Quick-Turnaround-Production (QTP) Devices ...................... 9

RC Oscillator..................................................................... 101

RC Oscillator Mode

Block Diagram........................................................... 101

Reader Response ............................................................. 174

Registers

CCP1CON (CCP Operation)....................................... 57

CMCON (Comparator Configuration).......................... 63

CONFIG (Configuration Word).................................... 98

EECON1 (EEPROM Control Register 1) .................... 92

INTCON (Interrupt Control)......................................... 26

Maps

PIC16F627A ................................................. 18, 19

PIC16F628A ................................................. 18, 19

OPTION_REG (Option) .............................................. 25

PCON (Power Control) ............................................... 29

PIE1 (Peripheral Interrupt Enable 1)........................... 27

PIR1 (Peripheral Interrupt Register 1) ........................ 28

Status.......................................................................... 24

T1CON Timer1 Control).............................................. 50

T2CON Timer2 Control).............................................. 55

Reset................................................................................. 101

RETFIE Instruction............................................................ 126

RETLW Instruction............................................................ 127

RETURN Instruction ......................................................... 127

Revision History ................................................................ 171

RLF Instruction.................................................................. 127

RRF Instruction ................................................................. 128

Serial Communication Interface (SCI) Module, See USART

Serialized Quick-Turnaround-Production (SQTP) Devices ... 9

SLEEP Instruction............................................................. 128

Software Simulator (MPLAB SIM)..................................... 133

Special Event Trigger. See Compare

Special Features of the CPU .............................................. 97

Special Function Registers ................................................. 20

Status Register ................................................................... 24

SUBLW Instruction............................................................ 128

SUBWF Instruction ........................................................... 129

SWAPF Instruction............................................................ 129

T1CKPS0 bit ....................................................................... 50

T1CKPS1 bit ....................................................................... 50

T1CON Register ................................................................. 50

T1OSCEN bit ...................................................................... 50

T2CKPS0 bit ....................................................................... 55

T2CKPS1 bit ....................................................................... 55

T2CON Register ................................................................. 55

Timer0

Block Diagrams

Timer0/WDT ....................................................... 48

External Clock Input.................................................... 47

Interrupt....................................................................... 47

Prescaler..................................................................... 48

Switching Prescaler Assignment................................. 49

Timer0 Module ............................................................ 47

Timer1

Asynchronous Counter Mode ..................................... 52

Capacitor Selection..................................................... 53

External Clock Input ................................................... 51

External Clock Input Timing........................................ 52

Oscillator..................................................................... 53

Prescaler .............................................................. 51, 53

Resetting Timer1 ........................................................ 53

Resetting Timer1 Registers ........................................ 53

Special Event Trigger (CCP) ...................................... 59

Synchronized Counter Mode ...................................... 51

Timer Mode ................................................................ 51

TMR1H ....................................................................... 52

TMR1L........................................................................ 52

Timer2

Block Diagram ............................................................ 54

Postscaler................................................................... 54

PR2 register................................................................ 54

Prescaler .............................................................. 54, 61

Timer2 Module............................................................ 54

TMR2 output............................................................... 54

TMR2 to PR2 Match Interrupt..................................... 60

Timing Diagrams

Timer0 ...................................................................... 147

Timer1 ...................................................................... 147

USART

Asynchronous Receiver...................................... 83

USART Asynchronous Master Transmission ............. 80

USART Asynchronous Reception .............................. 83

USART Synchronous Reception ................................ 89

USART Synchronous Transmission ........................... 87

Timing Diagrams and Specifications ................................ 144

TMR0 Interrupt.................................................................. 110

TMR1CS bit ........................................................................ 50

TMR1ON bit........................................................................ 50

TMR2ON bit........................................................................ 55

TOUTPS0 bit ...................................................................... 55

TOUTPS1 bit ...................................................................... 55

TOUTPS2 bit ...................................................................... 55

TOUTPS3 bit ...................................................................... 55

TRIS Instruction................................................................ 129

TRISA ................................................................................. 33

TRISB ................................................................................. 38

Universal Synchronous Asynchronous Receiver Transmitter

(USART) ..................................................................... 73

Asynchronous Receiver

Setting Up Reception.......................................... 85

Asynchronous Receiver Mode

Address Detect ................................................... 85

Block Diagram .................................................... 85

USART

Asynchronous Mode ................................................... 79

Asynchronous Receiver.............................................. 82

Asynchronous Reception............................................ 84

Asynchronous Transmission ...................................... 80

Asynchronous Transmitter.......................................... 79

Baud Rate Generator (BRG) ...................................... 75

Block Diagrams

Transmit.............................................................. 80

USART Receive ................................................. 82

BRGH bit .................................................................... 75

Sampling......................................................... 76, 77, 78

Synchronous Master Mode......................................... 86

Synchronous Master Reception ................................. 88

Synchronous Master Transmission ............................ 86

Synchronous Slave Mode........................................... 89

Synchronous Slave Reception ................................... 90

PIC16F627A/628A/648A

Synchronous Slave Transmit ...................................... 89

Voltage Reference

Configuration............................................................... 69

Voltage Reference Module ......................................... 69

Watchdog Timer (WDT) .................................................... 111

WWW Address..................................................................173

WWW, On-Line Support........................................................ 5

XORLW Instruction ...........................................................130

XORWF Instruction ........................................................... 130

PIC16F627A/628A/648A

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC16F627A/628A/648A:Standard VDD range 3.0V to

5.5V

PIC16F627A/628A/648AT:VDD range 3.0V to 5.5V

(Tape and Reel)

PIC16LF627A/628A/648A:VDD range 2.0V to 5.5V

PIC16LF627A/628A/648AT:VDD range 2.0V to 5.5V

(Tape and Reel)

Temperature

Range: I= -40°C to +85°C

E=-40°C to+125°C

Package: P=PDIP

SO = SOIC (Gull Wing, 7.50 mm body)

SS = SSOP (5.30 mm

ML = QFN (28 Lead)

Examples:

a) PIC16F627A - E/P 301 = Extended

Te m p .,

PDIP package, 20 MHz, normal VDD lim-

its, QTP pattern #301.

b) PIC16LF627A - I/SO = Industrial Temp.,

SOIC package, 20 MHz, extended VDD

limits.

AMERICAS

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WORLDWIDE SALES AND SERVICE

03/26/09